aboutsummaryrefslogtreecommitdiff
path: root/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
AgeCommit message (Expand)AuthorFilesLines
6 days[AMDGPU] MC support for v_fmaak_f64/v_fmamk_f64 gfx1250 intructions (#148282)Stanislav Mekhanoshin1-0/+27
7 days[AMDGPU] gfx1250: MC support for 64-bit literals (#147861)Stanislav Mekhanoshin1-0/+18
2025-06-25[AMDGPU] Add the support for `v_cvt_f32_bf16` on gfx1250 (#145632)Shilei Tian1-5/+9
2025-06-24[AMDGPU] Support v_lshl_add_u64 in gfx1250 (#145591)Stanislav Mekhanoshin1-0/+5
2025-06-23AMDGPU: Use reportFatalUsageError for unsupported disassembly error (#145264)Matt Arsenault1-1/+1
2025-06-21[AMDGPU] Rename call instructions from b64 to i64 (#145103)Stanislav Mekhanoshin1-0/+8
2025-06-17[llvm] annotate interfaces in llvm/Target for DLL export (#143615)Andrew Rogers1-1/+3
2025-05-09[AMDGPU][NFC] Remove _DEFERRED operands. (#139123)Ivan Kosarev1-55/+7
2025-05-08[AMDGPU][NFC] Get rid of OPW constants. (#139074)Ivan Kosarev1-136/+156
2025-05-08[AMDGPU][Disassembler][NFCI] Always defer immediate operands. (#138885)Ivan Kosarev1-109/+119
2025-04-18[LLVM][TableGen] Move DecoderEmitter output to anonymous namespace (#136214)Rahul Joshi1-0/+40
2025-03-19[AMDGPU] Add intrinsic and MI for image_bvh_dual_intersect_ray (#130038)Mariusz Sikora1-0/+1
2025-03-08[AMDGPU][MC] Don't crash on decoding invalid SOP1 ssrc0 operands. (#130302)Ivan Kosarev1-15/+19
2025-02-27[AMDGPU][MC] Disassembler warning for v_cmpx instructions (#127925)Jun Wang1-1/+13
2025-02-26[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)Pierre van Houtryve1-0/+1
2025-02-12[TableGen] Emit OpName as an enum class instead of a namespace (#125313)Rahul Joshi1-19/+21
2025-02-11[AMDGPU] Create new directive .amdhsa_inst_pref_size (#126622)Stanislav Mekhanoshin1-4/+4
2025-01-14[AMDGPU][True16][MC] true16 for v_cmp_lt_f16 (#122499)Brox Chen1-2/+17
2025-01-03[AMDGPU][MC] Allow null where 128b or larger dst reg is expected (#115200)Jun Wang1-0/+25
2024-11-25AMDGPU: Add support for v_dot2c_f32_bf16 instruction for gfx950 (#117598)Matt Arsenault1-0/+8
2024-11-25AMDGPU: Support v_cvt_scalef32_pk32_{bf|f}6_{bf|fp}16 for gfx950 (#117592)Matt Arsenault1-0/+1
2024-11-25AMDGPU: MC support for v_cvt_scalef32_pk32_f32_[fp|bf]6 of gfx950 (#117590)Matt Arsenault1-0/+1
2024-11-23AMDGPU: Remove wavefrontsize64 feature from dummy target (#117410)Matt Arsenault1-8/+8
2024-11-23AMDGPU: Move default wavesize hack for disassembler (#117422)Matt Arsenault1-18/+2
2024-11-21AMDGPU: Define v_mfma_f32_{16x16x128|32x32x64}_f8f6f4 instructions (#116723)Matt Arsenault1-0/+75
2024-11-20[AMDGPU][MC][True16] Support VOP2 instructions with true16 format (#115233)Brox Chen1-0/+19
2024-11-14[AMDGPU][True16][MC] VINTERP instructions supporting true16/fake16 (#113634)Brox Chen1-8/+30
2024-10-03[AMDGPU] Qualify auto. NFC. (#110878)Jay Foad1-18/+18
2024-09-28[AMDGPU] Use MCRegister. NFCCraig Topper1-7/+7
2024-09-24[AMDGPU][MC] Disallow null as saddr in flat instructions (#101730)Jun Wang1-0/+1
2024-09-20[AMDGPU] Do not use APInt for simple 64-bit arithmetic. NFC. (#109414)Jay Foad1-4/+2
2024-09-11[AMDGPU][True16][MC] 16bit vsrc and vdst support in MC (#104510)Brox Chen1-8/+14
2024-08-26[MC] Update MCOperand::getReg/setReg/createReg and MCInstBuilder::addReg to u...Craig Topper1-1/+1
2024-07-17[AMDGPU] clang-tidy: no else after return etc. NFC. (#99298)Jay Foad1-12/+10
2024-07-16[AMDGPU] Remove wavefrontsize feature from GFX10+ (#98400)Stanislav Mekhanoshin1-2/+18
2024-07-07[AMDGPU][MC] Allow UC_VERSION_* constant reuse (#96461)Carl Ritson1-2/+10
2024-06-27[AMDGPU] Only reinitialize disassembler Bytes array when needed. NFC. (#96666)Jay Foad1-6/+6
2024-06-18[AMDGPU][MC] Support UC_VERSION_* constants. (#95618)Ivan Kosarev1-0/+59
2024-05-04Add clarifying parenthesis around non-trivial conditions in ternary expressio...luolent1-2/+2
2024-04-26[AMDGPU] Support byte_sel modifier on v_cvt_sr_fp8_f32 and v_cvt_sr_bf8_f32 (...Stanislav Mekhanoshin1-8/+0
2024-04-18 [AMDGPU] Add disassembler diagnostics for invalid kernel descriptors (#87400)Emma Pilkington1-89/+159
2024-02-26[AMDGPU] Only try DecoderTables for the current subtarget. NFCI. (#82992)Jay Foad1-15/+30
2024-02-23[AMDGPU] Simplify AMDGPUDisassembler::getInstruction by removing Res. (#82775)Jay Foad1-142/+110
2024-02-22[AMDGPU] Remove DPP DecoderNamespaces. NFC. (#82491)Jay Foad1-52/+5
2024-02-22[AMDGPU] Clean up conversion of DPP instructions in AMDGPUDisassembler (#82480)Jay Foad1-74/+53
2024-02-22[AMDGPU] Split Dpp8FI and Dpp16FI operands (#82379)Jay Foad1-20/+13
2024-02-20[AMDGPU] Stop using SDWA DecoderNamespaces. NFCI. (#82233)Jay Foad1-12/+1
2024-02-20[AMDGPU] Try decoding instructions longest first. NFCI. (#82014)Jay Foad1-42/+42
2024-02-19[AMDGPU] Fix decoder for BF16 inline constants (#82276)Stanislav Mekhanoshin1-34/+76
2024-02-17[AMDGPU] Set predicates more consistently for BUF instructions (#81865)Jay Foad1-3/+0
generated by cgit v1.1 at 2025-07-17 16:08:13 +0000