aboutsummaryrefslogtreecommitdiff
path: root/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
AgeCommit message (Expand)AuthorFilesLines
34 hours[AMDGPU][gfx1250] Add `cu-store` subtarget feature (#150588)Pierre van Houtryve1-0/+6
9 days[AMDGPU] MC support for gfx1250 scale_offset modifier (#149881)Stanislav Mekhanoshin1-1/+27
9 days[AMDGPU] Verify asm VGPR alignment on gfx1250 (#149880)Stanislav Mekhanoshin1-2/+34
9 daysAMDGPU: Support v_wmma_f32_16x16x128_f8f6f4 on gfx1250 (#149684)Changpeng Fang1-0/+79
12 days[AMDGPU] Support nv memory instructions modifier on gfx1250 (#149582)Stanislav Mekhanoshin1-1/+25
2025-07-15[AMDGPU] Use a range-based for loop (NFC) (#148767)Kazu Hirata1-2/+2
2025-07-15AMDGPU: Implement MC layer support for gfx1250 wmma instructions. (#148570)Changpeng Fang1-3/+35
2025-07-11[AMDGPU] MC support for v_fmaak_f64/v_fmamk_f64 gfx1250 intructions (#148282)Stanislav Mekhanoshin1-4/+24
2025-07-10[AMDGPU] VOPD/VOPD3 changes for gfx1250 (#147602)Stanislav Mekhanoshin1-22/+185
2025-07-09[AMDGPU] gfx1250: MC support for 64-bit literals (#147861)Stanislav Mekhanoshin1-31/+95
2025-07-08[AMDGPU] Add support for `v_cvt_f32_fp8` on gfx1250 (#147579)Shilei Tian1-4/+4
2025-07-03AMDGPU: Implement tensor load and store instructions for gfx1250 (#146636)Changpeng Fang1-6/+21
2025-06-28MCParsedAsmOperand::print: Add MCAsmInfo parameterFangrui Song1-2/+2
2025-06-28MC: Migrate away from operator<< MCExprFangrui Song1-1/+4
2025-06-27[AMDGPU] Use StringRef::consume_back (NFC) (#146194)Kazu Hirata1-10/+10
2025-06-17[llvm] annotate interfaces in llvm/Target for DLL export (#143615)Andrew Rogers1-1/+3
2025-06-13[AMDGPU][AsmParser] Support true16 register suffix for valid register range (...Shilei Tian1-3/+16
2025-06-04[AMDGPU][True16][MC][CodeGen] true16 mode for v_cvt_pk_bf8/fp8_f32 (#141881)Brox Chen1-4/+8
2025-06-03[AMDGPU] Bugfix for scaled MFMA parsing FP literals (#142493)Vigneshwar Jayakumar1-8/+22
2025-05-27MCSymbol: Remove the default argument of getVariableValueFangrui Song1-1/+1
2025-05-26MCParser: Error when .set reassigns a non-redefinable variableFangrui Song1-0/+1
2025-05-26[AMDGPU] Use StringRef::consume_front (NFC) (#141442)Kazu Hirata1-2/+1
2025-05-25Replace #include MCAsmLexer.h with AsmLexer.hFangrui Song1-1/+1
2025-05-21[AMDGPU] Fix scale opsel flags for scaled MFMA operations (#140183)Vigneshwar Jayakumar1-7/+80
2025-05-09[AMDGPU][NFC] Remove _DEFERRED operands. (#139123)Ivan Kosarev1-17/+5
2025-05-08[AMDGPU][NFC] Remove unused operand types. (#139062)Ivan Kosarev1-34/+4
2025-05-07[AMDGPU] Fix regclass check for PackedF32InputMods in AsmParser. (#138767)Stanislav Mekhanoshin1-2/+2
2025-04-10[AMDGPU] Rename TH_STORE_RT_WB to TH_STORE_WB (#135171)Mirko BrkuĊĦanin1-2/+2
2025-03-28[AMDGPU] Hoist some constant stuff out of the loop in AMDGPUAsmParser.cpp. NF...Stanislav Mekhanoshin1-6/+6
2025-03-14[NFC][AMDGPU] Replace more direct arch comparison with isAMDGCN() (#131379)Shilei Tian1-3/+3
2025-03-02[MC] Move VariantKind info to MCAsmInfoFangrui Song1-16/+0
2025-03-02[MCParser] Extract some VariantKind from getVariantKindForNameFangrui Song1-0/+16
2025-02-12[TableGen] Emit OpName as an enum class instead of a namespace (#125313)Rahul Joshi1-30/+30
2025-02-11[AMDGPU] Create new directive .amdhsa_inst_pref_size (#126622)Stanislav Mekhanoshin1-0/+12
2025-02-05[AMDGPU][True16][MC] validate op_sel and .l/.h syntax (#125872)Brox Chen1-0/+44
2025-01-31[AMDGPU] Allow unaligned VGPR for ds_read_b96_tr_b6 (#125169)Pravin Jagtap1-1/+4
2025-01-30Revert "[AMDGPU][True16][MC] validate op_sel and .l/.h syntax (#123250)"Kazu Hirata1-44/+0
2025-01-30[AMDGPU][True16][MC] validate op_sel and .l/.h syntax (#123250)Brox Chen1-0/+44
2025-01-03[AMDGPU][MC] Allow null where 128b or larger dst reg is expected (#115200)Jun Wang1-2/+6
2024-12-04AMDGPU: Simplify definition of bitop3 operand. NFC. (#118648)Matt Arsenault1-17/+0
2024-11-26AMDGPU: Verify f8f6f4 formats in assembler (#117826)Matt Arsenault1-0/+32
2024-11-26AMDGPU: MC support for V_CVT_SCALE_SR_FP4 instructions (#117795)Matt Arsenault1-0/+4
2024-11-26Builtins & Codegen support for v_cvt_scalef32_pk_{fp|bf}8_{f|bf}16 for gfx950...Matt Arsenault1-1/+0
2024-11-25AMDGPU: MC support for v_cvt_scalef32_pk_fp4_{f|bf}16 on gfx950. (#117594)Matt Arsenault1-1/+3
2024-11-25AMDGPU: Add MC support for gfx950 V_BITOP3_B32/B16 (#117379)Matt Arsenault1-0/+25
2024-11-13[AMDGPU] Remove unused includes (NFC) (#116154)Kazu Hirata1-1/+0
2024-10-03[AMDGPU] Qualify auto. NFC. (#110878)Jay Foad1-5/+5
2024-09-28[AMDGPU] Use MCRegister. NFCCraig Topper1-82/+87
2024-09-27[AMDGPU][MC] Implement fft and rotate modes for ds_swizzle_b32 (#108064)Jun Wang1-10/+59
2024-09-23[AMDGPU] Include unused preload kernarg in KD total SGPR count (#104743)Austin Kerbow1-2/+11
generated by cgit v1.1 at 2025-07-30 19:47:27 +0000