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path: root/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
AgeCommit message (Expand)AuthorFilesLines
31 hours[AArch64][SVE] Add codegen support for partial reduction lowering to wide add...James Chesterman1-2/+58
2 days[AArch64] Remove unused includes (NFC) (#115685)Kazu Hirata1-3/+0
12 days[PAC][CodeGen][ELF][AArch64] Support signed GOT (#113811)Daniil Kovalev1-0/+5
14 days[SDAG] Simplify `SDNodeFlags` with bitwise logic (#114061)Yingwei Zheng1-11/+4
2024-10-29[AArch64] Add ComputeNumSignBits for VASHR. (#113957)David Green1-0/+5
2024-10-28[AArch64] Remove header dependencies of AArch64ISelLowering.h. NFCDavid Green1-2/+19
2024-10-24[aarch64] atan2 intrinsic lowering (p5) (#112611)Tex Riddell1-13/+16
2024-10-24[AArch64] Fix failure with inline asm and svcount (#112537)Sander de Smalen1-0/+32
2024-10-23[AArch64] Use INDEX for constant Neon step vectors (#113424)Ricardo Jesus1-1/+3
2024-10-22[LLVM][CodeGen][AArch64] while_le(#,max_int) -> all_active (#111183)Paul Walker1-0/+7
2024-10-22[AArch64] Improve index selection for histograms (#111150)James Chesterman1-10/+16
2024-10-21[AArch64] Add patterns for combining qxtn+rshr to qrshrnDavid Green1-0/+23
2024-10-21[AArch64] Add some basic patterns for qshrn.David Green1-0/+21
2024-10-21[AArch64] Convert aarch64_neon_sqxtn to ISD::TRUNCATE_SSAT_S and replace tabl...David Green1-0/+9
2024-10-20[DAG] isConstantIntBuildVectorOrConstantInt - peek through bitcasts (#112710)...Simon Pilgrim1-1/+1
2024-10-20Revert "[DAG] isConstantIntBuildVectorOrConstantInt - peek through bitcasts (...Martin Storsjö1-1/+1
2024-10-18[DAG] isConstantIntBuildVectorOrConstantInt - peek through bitcasts (#112710)Simon Pilgrim1-1/+1
2024-10-18[AArch64][SVE] Support lowering fixed-length BUILD_VECTORS to ZIPs (#111698)Benjamin Maxwell1-13/+62
2024-10-17[PowerPC][ISelLowering] Support -mstack-protector-guard=tls (#110928)Keith Packard1-2/+2
2024-10-17[LLVM] Make more use of IRBuilder::CreateIntrinsic. NFC. (#112706)Jay Foad1-9/+6
2024-10-17[APInt] Fix APInt constructions where value does not fit bitwidth (NFCI) (#80...Nikita Popov1-16/+16
2024-10-16[LLVM] Remove unused variables after #112546Jay Foad1-1/+0
2024-10-16[LLVM] Make more use of IRBuilder::CreateIntrinsic. NFC. (#112546)Jay Foad1-2/+1
2024-10-14[AArch64] Increase inline memmove limit to 16 stored registers (#111848)David Green1-1/+2
2024-10-11[AArch64] Disable consecutive store merging when Neon is unavailable (#111519)Benjamin Maxwell1-0/+15
2024-10-11[NFC] Rename `Intrinsic::getDeclaration` to `getOrInsertDeclaration` (#111752)Rahul Joshi1-13/+16
2024-10-11AArch64: Select FCANONICALIZE (#104429)YunQiang Su1-0/+3
2024-10-10AArch64: Add FMINNUM_IEEE and FMAXNUM_IEEE support (#107855)YunQiang Su1-8/+13
2024-10-09[TTI] NFC: Port TLI.shouldSinkOperands to TTI (#110564)Jeffrey Byrnes1-416/+0
2024-10-08[LLVM][CodeGen][SVE2] Implement nxvf64 fpround to nxvbf16. (#111012)Paul Walker1-0/+15
2024-10-07[LLVM][CodeGen] Add lowering for scalable vector bfloat operations. (#109803)Paul Walker1-0/+30
2024-10-03[AArch64] - Fold and and cmp into tst (#110347)Jorge Botto1-0/+26
2024-10-03[AArch64][SVE] Fix definition of bfloat fcvt intrinsics. (#110281)Paul Walker1-1/+8
2024-10-01[AArch64][NEON][SVE] Lower i8 to i64 partial reduction to a dot product (#110...James Chesterman1-4/+20
2024-10-01[Clang][LLVM][AArch64] Add intrinsic for MOVT SME2 instruction (#97602)CarolineConcatto1-0/+2
2024-09-24[LLVM][CodeGen][SVE] Implement nxvf32 fpround to nxvbf16. (#107420)Paul Walker1-3/+47
2024-09-19[AArch64][NEON][SVE] Lower mixed sign/zero extended partial reductions to usd...Sam Tebbs1-18/+37
2024-09-16[AArch64] Expand scmp/ucmp vector operations with sub (#108830)David Green1-0/+6
2024-09-11[AArch64] Allow i16->f64 uitofp tbl shufflesDavid Green1-5/+10
2024-09-10[AArch64] Lower __builtin_bswap16 to rev16 if bswap followed by any_extend (#...adprasad-nvidia1-0/+19
2024-09-07[AArch64] Do not generate uitofp(ld4) where and/shift can be used. (#107538)David Green1-0/+10
2024-09-06[AArch64] Prevent generating tbl instruction instead of smull (#106375)Igor Kirillov1-0/+10
2024-09-06[AArch64][NEON] Lower fixed-width add partial reductions to dot product (#107...Sam Tebbs1-7/+11
2024-09-05[AArch64] Fold away zext of extract of uzp. (#107367)David Green1-0/+66
2024-09-05[LLVM][CodeGen][SVE] Implement nxvbf16 fpextend to nxvf32/nxvf64. (#107253)Paul Walker1-1/+22
2024-09-05[AArch64] Combine zext of deinterleaving shuffle. (#107201)David Green1-0/+56
2024-09-04[LLVM][AArch64] Enable verifyTargetSDNode for scalable vectors and fix the fa...Paul Walker1-23/+64
2024-09-02[AArch64] Lower partial add reduction to udot or svdot (#101010)Sam Tebbs1-0/+70
2024-08-30[AArch64] Fix a presumed typo in isFPImmLegal limit. NFC (#106716)Marina Taylor1-1/+3
2024-08-30[LLVM][AArch64] Fix invalid use of AArch64ISD::UZP2 in performConcatVectorsCo...Paul Walker1-5/+9
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