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2019-08-05Removes support in the ARM assembler for the unsigned variants of the VQ(R)DM...Barnaby Wilks2-4/+9
2019-07-30RISC-V: Fix minor issues with FP csr instructions.Jim Wilson2-16/+24
2019-07-24[ARC] Update disassembler opcode selectionClaudiu Zissulescu2-1/+30
2019-07-24[ARC] Update ARC opcode tableClaudiu Zissulescu4-1461/+2256
2019-07-23[AArch64] Add support for GMID_EL1 register for +memtagKyrylo Tkachov2-1/+8
2019-07-23Add Changelog entry missing from previous delta.Nick Clifton1-0/+5
2019-07-22This patch addresses the change in the June Armv8.1-M Mainline specification,...Barnaby Wilks1-4/+0
2019-07-19cpu,opcodes,gas: use %r0 and %r6 instead of %a and %ctf in eBPF disassemblerJose E. Marchesi2-4/+8
2019-07-17x86: drop stale Mem enumeratorJan Beulich3-4/+24
2019-07-16x86: make RegMem an opcode modifierJan Beulich6-16487/+20423
2019-07-16x86: fold SReg{2,3}Jan Beulich7-23935/+13937
2019-07-15cpu,opcodes,gas: fix explicit arguments to eBPF ldabs instructionsJose E. Marchesi4-82/+47
2019-07-14cpu,opcodes,gas: fix arguments to ldabs and ldind eBPF instructionsJose E. Marchesi3-48/+53
2019-07-10arm-dis.c (print_insn_coprocessor): Rename index to index_operand.Hans-Peter Nilsson2-5/+10
2019-07-05Kito's 5-part patch set to improve .insn support.Jim Wilson2-4/+35
2019-07-02[AArch64] Allow MOVPRFX to be used with FMOVRichard Sandiford2-1/+6
2019-07-02[AArch64] Add missing C_MAX_ELEM flags for SVE conversionsRichard Sandiford2-28/+33
2019-07-02[AArch64] Fix bogus MOVPRFX warning for GPR form of CPYRichard Sandiford2-5/+5
2019-07-01[gas][aarch64][SVE2] Fix pmull{t,b} requirement on SVE2-AESMatthew Malcomson5-301/+340
2019-07-01x86: drop Vec_Imm4Jan Beulich6-9985/+9983
2019-07-01x86: limit ImmExt abuseJan Beulich3-126/+136
2019-07-01x86: optimize AND/OR with twice the same registerJan Beulich3-4/+10
2019-07-01x86-64: optimize certain commutative VEX-encoded insnsJan Beulich3-334/+371
2019-07-01x86: optimize EVEX packed integer logical instructionsJan Beulich3-8/+14
2019-07-01x86: add missing pseudo ops for VPCLMULQDQ ISA extensionJan Beulich4-1/+168
2019-07-01x86: drop bogus Disp8MemShift attributesJan Beulich3-6/+12
2019-07-01x86: remove ModRM.mod decoding layer from AVX512F VMOVS{S,D}Jan Beulich5-63/+35
2019-07-01x86: drop a few dead macrosJan Beulich2-5/+5
2019-06-27i386: Check vector length for scatter/gather prefetch instructionsH.J. Lu5-12/+132
2019-06-27x86: fold AVX scalar to/from int conversion insnsJan Beulich2-48/+15
2019-06-27x86: allow VEX et al encodings in 16-bit (protected) modeJan Beulich2-33/+42
2019-06-26RISC-V: Make objdump disassembly work right for binary files.Jim Wilson2-2/+12
2019-06-25x86: correct / adjust debug printingJan Beulich3-14/+29
2019-06-25x86: drop dqa_modeJan Beulich4-24/+15
2019-06-25x86: simplify OP_I64()Jan Beulich2-40/+8
2019-06-25x86: fix (dis)assembly of certain SSE2 insns in 16-bit modeJan Beulich4-9/+17
2019-06-25x86-64: also optimize ANDQ with immediate fitting in 7 bitsJan Beulich3-2/+7
2019-06-21i386: Break i386-dis-evex.h into small filesH.J. Lu8-3486/+3472
2019-06-19i386: Check vector length for EVEX broadcast instructionsH.J. Lu3-10/+113
2019-06-17i386: Check vector length for vshufXXX/vinsertXXX/vextractXXXH.J. Lu3-13/+135
2019-06-14Updated French translation for the opcodes subdirectory.Nick Clifton2-78/+86
2019-06-13opcodes/or1k: Regenerate opcodesStafford Horne9-273/+1195
2019-06-12Add missing ChangeLog entriesPeter Bergner1-0/+4
2019-06-12Remove the ldmx mnemonic that never made it into POWER9.Peter Bergner1-2/+0
2019-06-05i386: Check vector length for EVEX vextractfXX and vinsertfXXH.J. Lu3-9/+92
2019-06-04i386: Check for reserved VEX.vvvv and EVEX.vvvvH.J. Lu2-10/+27
2019-06-04Enable Intel AVX512_VP2INTERSECT insnH.J. Lu8-4142/+4240
2019-06-04Add support for Intel ENQCMD[S] instructionsH.J. Lu7-4064/+4190
2019-06-04Remove an unnecessary set of parentheses in the arm-dis.c source file.Alan Hayward2-1/+5
2019-06-03Don't waste space in prefix_opcd_indicesAlan Modra2-1/+5
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