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| author | Jim Wilson <jimw@sifive.com> | 2019-07-30 14:42:16 -0700 |
|---|---|---|
| committer | Jim Wilson <jimw@sifive.com> | 2019-07-30 14:42:16 -0700 |
| commit | c0d6f62fcec939ab896e4839f6aa14ebfcd43565 (patch) | |
| tree | 7fd7bc88c705fde3cbfb775f47aadf88e6d0937d /opcodes | |
| parent | aa3b653351504e262fb455af5efb6eea6d981597 (diff) | |
| download | gdb-c0d6f62fcec939ab896e4839f6aa14ebfcd43565.zip gdb-c0d6f62fcec939ab896e4839f6aa14ebfcd43565.tar.gz gdb-c0d6f62fcec939ab896e4839f6aa14ebfcd43565.tar.bz2 | |
RISC-V: Fix minor issues with FP csr instructions.
Mel Chen <mel.chen@sifive.com>
gas/
* testsuite/gas/riscv/alias-csr.s: Add testcase for CSR-access
alias instructions.
* testsuite/gas/riscv/no-aliases-csr.d: Run testcase alias-csr.s with
-Mno-aliases.
* testsuite/gas/riscv/alias-csr.d: Run testcase alias-csr.s.
* testsuite/gas/riscv/priv-reg.d: Update.
opcodes/
* riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
* riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
fscsr.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 8 | ||||
| -rw-r--r-- | opcodes/riscv-opc.c | 32 |
2 files changed, 24 insertions, 16 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index ba0be86..652b4bb 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,11 @@ +2019-07-30 Mel Chen <mel.chen@sifive.com> + + * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm, + fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions. + + * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr, + fscsr. + 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com> * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 113d1a5..b7e8d79 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -496,22 +496,22 @@ const struct riscv_opcode riscv_opcodes[] = {"remuw", 64, {"M", 0}, "d,s,t", MATCH_REMUW, MASK_REMUW, match_opcode, 0 }, /* Single-precision floating-point instruction subset */ -{"frsr", 0, {"F", 0}, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, 0 }, -{"fssr", 0, {"F", 0}, "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, 0 }, -{"fssr", 0, {"F", 0}, "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, 0 }, -{"frcsr", 0, {"F", 0}, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, 0 }, -{"fscsr", 0, {"F", 0}, "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, 0 }, -{"fscsr", 0, {"F", 0}, "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, 0 }, -{"frrm", 0, {"F", 0}, "d", MATCH_FRRM, MASK_FRRM, match_opcode, 0 }, -{"fsrm", 0, {"F", 0}, "s", MATCH_FSRM, MASK_FSRM | MASK_RD, match_opcode, 0 }, -{"fsrm", 0, {"F", 0}, "d,s", MATCH_FSRM, MASK_FSRM, match_opcode, 0 }, -{"fsrmi", 0, {"F", 0}, "d,Z", MATCH_FSRMI, MASK_FSRMI, match_opcode, 0 }, -{"fsrmi", 0, {"F", 0}, "Z", MATCH_FSRMI, MASK_FSRMI | MASK_RD, match_opcode, 0 }, -{"frflags", 0, {"F", 0}, "d", MATCH_FRFLAGS, MASK_FRFLAGS, match_opcode, 0 }, -{"fsflags", 0, {"F", 0}, "s", MATCH_FSFLAGS, MASK_FSFLAGS | MASK_RD, match_opcode, 0 }, -{"fsflags", 0, {"F", 0}, "d,s", MATCH_FSFLAGS, MASK_FSFLAGS, match_opcode, 0 }, -{"fsflagsi", 0, {"F", 0}, "d,Z", MATCH_FSFLAGSI, MASK_FSFLAGSI, match_opcode, 0 }, -{"fsflagsi", 0, {"F", 0}, "Z", MATCH_FSFLAGSI, MASK_FSFLAGSI | MASK_RD, match_opcode, 0 }, +{"frcsr", 0, {"F", 0}, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS }, +{"frsr", 0, {"F", 0}, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS }, +{"fscsr", 0, {"F", 0}, "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, INSN_ALIAS }, +{"fscsr", 0, {"F", 0}, "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, INSN_ALIAS }, +{"fssr", 0, {"F", 0}, "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, INSN_ALIAS }, +{"fssr", 0, {"F", 0}, "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, INSN_ALIAS }, +{"frrm", 0, {"F", 0}, "d", MATCH_FRRM, MASK_FRRM, match_opcode, INSN_ALIAS }, +{"fsrm", 0, {"F", 0}, "s", MATCH_FSRM, MASK_FSRM | MASK_RD, match_opcode, INSN_ALIAS }, +{"fsrm", 0, {"F", 0}, "d,s", MATCH_FSRM, MASK_FSRM, match_opcode, INSN_ALIAS }, +{"fsrmi", 0, {"F", 0}, "d,Z", MATCH_FSRMI, MASK_FSRMI, match_opcode, INSN_ALIAS }, +{"fsrmi", 0, {"F", 0}, "Z", MATCH_FSRMI, MASK_FSRMI | MASK_RD, match_opcode, INSN_ALIAS }, +{"frflags", 0, {"F", 0}, "d", MATCH_FRFLAGS, MASK_FRFLAGS, match_opcode, INSN_ALIAS }, +{"fsflags", 0, {"F", 0}, "s", MATCH_FSFLAGS, MASK_FSFLAGS | MASK_RD, match_opcode, INSN_ALIAS }, +{"fsflags", 0, {"F", 0}, "d,s", MATCH_FSFLAGS, MASK_FSFLAGS, match_opcode, INSN_ALIAS }, +{"fsflagsi", 0, {"F", 0}, "d,Z", MATCH_FSFLAGSI, MASK_FSFLAGSI, match_opcode, INSN_ALIAS }, +{"fsflagsi", 0, {"F", 0}, "Z", MATCH_FSFLAGSI, MASK_FSFLAGSI | MASK_RD, match_opcode, INSN_ALIAS }, {"flw", 32, {"F", "C", 0}, "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, {"flw", 32, {"F", "C", 0}, "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE }, {"flw", 0, {"F", 0}, "D,o(s)", MATCH_FLW, MASK_FLW, match_opcode, INSN_DREF|INSN_4_BYTE }, |