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author | Jan Beulich <jbeulich@novell.com> | 2019-06-25 09:41:33 +0200 |
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committer | Jan Beulich <jbeulich@suse.com> | 2019-06-25 09:41:33 +0200 |
commit | 2c70385689542a4c4cbe160601e54f9f18a4c4c5 (patch) | |
tree | 4e3fac1720511587ea3672d30794c14116a770b2 /opcodes | |
parent | 4970191fa557c4769697fb41db06f2dcb5f7de2e (diff) | |
download | gdb-2c70385689542a4c4cbe160601e54f9f18a4c4c5.zip gdb-2c70385689542a4c4cbe160601e54f9f18a4c4c5.tar.gz gdb-2c70385689542a4c4cbe160601e54f9f18a4c4c5.tar.bz2 |
x86: correct / adjust debug printing
For quite some time we've been using combinations of bits for
specifying various registers in operands and templates. I think it was
Alan who had indicated that likely the debug printing would need
adjustment as a result. Here we go.
Accumulator handling for GPRs gets changed to match that for FPU regs.
For this to work, OPERAND_TYPE_ACC{32,64} get repurposed, with their
original uses replaced by direct checks of the two bits of interest,
which is cheaper than operand_type_equal() invocations.
For SIMD registers nothing similar appears to be needed, as respective
operands get stripped from the (copy of the) template before pt() is
reached.
The type change on pi() is to silence a compiler diagnostic. Arguably
its other parameter could also be const-qualified.
Diffstat (limited to 'opcodes')
-rw-r--r-- | opcodes/ChangeLog | 8 | ||||
-rw-r--r-- | opcodes/i386-gen.c | 12 | ||||
-rw-r--r-- | opcodes/i386-init.h | 23 |
3 files changed, 29 insertions, 14 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index f7890e0..e669421 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,13 @@ 2019-06-25 Jan Beulich <jbeulich@suse.com> + * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG + entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and + OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and + OPERAND_TYPE_ACC64 entries. + * i386-init.h: Re-generate. + +2019-06-25 Jan Beulich <jbeulich@suse.com> + * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1): Delete. (intel_operand_size, OP_E_register, OP_E_memory): Drop handling diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index e80085a..c0325ed 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -435,7 +435,7 @@ static initializer operand_type_init[] = { "OPERAND_TYPE_TEST", "Test" }, { "OPERAND_TYPE_DEBUG", - "FloatReg" }, + "Debug" }, { "OPERAND_TYPE_FLOATREG", "FloatReg" }, { "OPERAND_TYPE_FLOATACC", @@ -444,8 +444,6 @@ static initializer operand_type_init[] = "SReg2" }, { "OPERAND_TYPE_SREG3", "SReg3" }, - { "OPERAND_TYPE_ACC", - "Acc" }, { "OPERAND_TYPE_JUMPABSOLUTE", "JumpAbsolute" }, { "OPERAND_TYPE_REGMMX", @@ -460,10 +458,14 @@ static initializer operand_type_init[] = "RegMask" }, { "OPERAND_TYPE_ESSEG", "EsSeg" }, + { "OPERAND_TYPE_ACC8", + "Acc|Byte" }, + { "OPERAND_TYPE_ACC16", + "Acc|Word" }, { "OPERAND_TYPE_ACC32", - "Reg32|Acc|Dword" }, + "Acc|Dword" }, { "OPERAND_TYPE_ACC64", - "Reg64|Acc|Qword" }, + "Acc|Qword" }, { "OPERAND_TYPE_DISP16_32", "Disp16|Disp32" }, { "OPERAND_TYPE_ANYDISP", diff --git a/opcodes/i386-init.h b/opcodes/i386-init.h index 1d9c17f..735403a 100644 --- a/opcodes/i386-init.h +++ b/opcodes/i386-init.h @@ -1458,8 +1458,8 @@ 0, 0 } } #define OPERAND_TYPE_DEBUG \ - { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \ + { { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0 } } #define OPERAND_TYPE_FLOATREG \ @@ -1482,11 +1482,6 @@ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0 } } -#define OPERAND_TYPE_ACC \ - { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0, 0 } } - #define OPERAND_TYPE_JUMPABSOLUTE \ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -1522,13 +1517,23 @@ 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0 } } +#define OPERAND_TYPE_ACC8 \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0 } } + +#define OPERAND_TYPE_ACC16 \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0 } } + #define OPERAND_TYPE_ACC32 \ - { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0 } } #define OPERAND_TYPE_ACC64 \ - { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \ 0, 0 } } |