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19 hoursPowerPC: Add support for RFC02657 - AES acceleration instructionsSurya Kumari Jangala1-1/+79
4 daysUpdate translations for various sub-directoriesNick Clifton3-496/+497
5 daysChange version to 2.44.50 and regenerate filesNick Clifton2-170/+159
5 daysAdd markers for bihnutils 2.44 branchNick Clifton1-0/+4
7 daysaarch64: Fix sve2p1 gating and add missing instructionsAndrew Carlotti2-333/+457
7 daysx86: Add CpuGMISM2 and CpuGMICCSMayShao-oc5-2310/+2326
7 daysx86/APX: convert runtime special case to build-time oneJan Beulich2-4/+18
7 daysRISC-V: Use t2 for tail if Zicfilp enabledKito Cheng1-0/+1
7 daysRISC-V: Support CFI Zicfiss and Zicfilp instructions and CSR.Monk Chiang1-0/+45
7 daysRISC-V: Support ssctr/smctr extensions with version 1.0.Nelson Chu1-2/+3
7 daysx86: Ignore rounding for vcvt[,u]si2sd under r32 and vcvt[,u]dq2pd instead of...Haochen Jiang2-4/+3
8 daysx86: Support x86 Zhaoxin PadLock PHE2 instructionsMayShao-oc7-4496/+4546
8 daysdisassemble_free_powerpcAlan Modra3-0/+12
10 daysx86: Remove "NE" in mnemonics for convert insns related to AI data typesHaochen Jiang4-2133/+2133
10 daysx86: Rename VCOMSBF16 to VCOMISBF16Haochen Jiang4-2102/+2102
10 daysx86: Remove "P" and "NE" in mnemonics for BF16 arithmetic insnsHaochen Jiang4-2238/+2238
10 daysSupport Intel AMX-AVX512Haochen Jiang12-1787/+2078
10 daysSupport Intel AMX-MOVRSHu, Lin111-2622/+2830
10 daysSupport Intel MOVRSHu, Lin110-2649/+2792
10 daysx86: Remove mod_table pass for MVexSIBMEMHaochen Jiang1-28/+18
14 daysaarch64: Add support for FEAT_SME_B16B16 feature.Srinath Parvathaneni2-311/+535
14 daysaarch64: Add support for FEAT_SVE_B16B16 min and max instructions.Srinath Parvathaneni2-218/+283
14 daysaarch64: Add support for FEAT_SVE_B16B16 feature.Srinath Parvathaneni1-14/+14
14 daysaarch64: Make VGx4 symbol mandatory for fvdotb and fvdottAndrew Carlotti1-2/+2
14 daysaarch64: Rename AARCH64_OPND_SME_ZT0_INDEX2_12Andrew Carlotti3-5/+5
14 daysaarch64: Remove redundant sme-lutv2 qualifiers and operandsAndrew Carlotti6-96/+70
14 daysaarch64: Fix incorrect gating of sme-lutv2 instructionsAndrew Carlotti1-4/+10
14 daysaarch64: Add support for FEAT_SME_F16F16 fcvt and fcvtl instructions.Srinath Parvathaneni2-218/+246
14 daysaarch64: Add support for FEAT_SME_F16F16 fmla and fmls instructions.Srinath Parvathaneni2-286/+430
14 daysaarch64: Add support for FEAT_SME_F16F16 fmops and fmopa instructions.Srinath Parvathaneni2-185/+221
14 daysx86: Support x86 Zhaoxin PadLockRNG2 instructionMayShao-oc7-4432/+4483
2025-01-09RISC-V: Fix display of partial instructionsCharlie Jenkins1-4/+49
2025-01-08Support Intel AMX-FP8Liwei Xu7-1058/+1179
2025-01-06x86/APX: simplify ENQCMD[,S} opcode table entriesJan Beulich2-8/+8
2025-01-02Support Intel AMX-TF32Haochen Jiang7-1090/+1172
2025-01-02Support Intel AMX-TRANSPOSEHaochen Jiang8-11454/+11755
2025-01-01Update year range in copyright notice of binutils filesAlan Modra272-276/+276
2024-12-24arc: add_to_decodelistAlan Modra1-147/+124
2024-12-23Support Intel AVX10.2 minmax, vector copy and compare instructionsHaochen Jiang8-2255/+2562
2024-12-18Support Intel SM4 AVX10.2 extensionHaochen Jiang6-9281/+9309
2024-12-16Update translations for the opcodes directory for the French and Serbian lang...Nick Clifton2-976/+861
2024-12-09PowerPC: Disallow r0 as a base register for the hashst and hashchk insnsPeter Bergner1-7/+7
2024-12-09LoongArch: Assign DWARF register numbers to register aliasesLulu Cai1-0/+32
2024-12-05Support Intel AVX10.2 satcvt instructionsHu, Lin17-658/+1176
2024-12-05x86: Eliminate unnecessary {evex} prefixesH.J. Lu4-11/+29
2024-12-03PowerPC: Add support for RFC02680 - PQC Acceleration InstructionsSurya Kumari Jangala1-0/+10
2024-12-03Support Intel AVX10.2 BF16 instructionsKong Lingling6-2042/+2642
2024-12-02x86: default to not accepting MPX insnsJan Beulich2-2/+2
2024-11-29s390: Treat addressing operand sequence as one in disassemblerJens Remus1-18/+66
2024-11-29s390: Fix disassembly of optional addressing operandsJens Remus1-12/+22
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