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riscv
riscv-debug-spec
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command
4852f737
·
\Rcommand is not readable.
·
Aug 02, 2018
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regno
d049e6c8
·
Document cmderr when writing dcsr while running.
·
Aug 14, 2018
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asid_trigger
87f62ac2
·
Address review feedback.
·
Sep 27, 2018
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compliance
c39ef671
·
Clarify "all registers."
·
Oct 01, 2018
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minimum_378
78a10c9f
·
DM contains->tracks bits of state.
·
Oct 02, 2018
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clarify_383
d67f5c2d
·
Clean up language of #383.
·
Oct 02, 2018
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release
4e0bb0fc
·
Don't run text off a page when longtable is used. (#435)
·
Mar 25, 2019
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v0.13-release
4e0bb0fc
·
Don't run text off a page when longtable is used. (#435)
·
Mar 25, 2019
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command_discovery
2e1fef23
·
Allow trigger section to be parsed without knowing DXLEN.
·
Nov 06, 2019
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mwachs5-patch-1
9d55a575
·
Make the emitted registers chisel3
·
Nov 21, 2019
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resumegroup
b5b33391
·
Add resume groups.
·
Dec 03, 2019
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for_riscv
95a7f792
·
Rename to Debug Specification for RISC-V.
·
Jul 14, 2020
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maskmax
59c2d52e
·
Improve formatting.
·
Dec 18, 2020
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license
57816130
·
Be more verbose about the license.
·
Jun 09, 2021
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dmi_clarify
67fbfe78
·
dmi.{data,address} are unspecified after write/nop
·
Oct 14, 2022
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timing_compatibility
b1260894
·
Debuggers should accept mcontrol6.20 reading back 1.
·
Feb 10, 2023
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a_extension
2fdf271e
·
Document trigger behavior with vector/push/pop accesses.
·
Mar 08, 2023
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halt_resume_groups
6a56dea7
·
External trigger signals inputs don't cause trigger output.
·
Jun 12, 2023
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implementations
314b09fc
·
Fix type in execution appendix: execute -> postexec
·
Jul 26, 2023
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master_slave
f44beaf1
·
AR: Use manager/subordinate for master/slave.
·
Jul 31, 2023
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