\section{JTAG Debug Transport Module} \label{sec:jtagdtm}

This Debug Transport Module is based around a normal JTAG Test Access Port
(TAP).  The JTAG TAP allows access to arbitrary JTAG registers by first
selecting one using the JTAG instruction register (IR), and then accessing it
through the JTAG data register (DR).

\subsection{JTAG Background}

JTAG refers to IEEE Std 1149.1-2013. It is a standard that defines test logic
that can be included in an integrated circuit to test the interconnections
between integrated circuits, test the integrated circuit itself, and observe or
modify circuit activity during the component’s normal operation.
This specification uses the latter functionality.
The JTAG standard defines a Test Access Port (TAP) that
can be used to read and write a few custom registers, which can be used to
communicate with debug hardware in a component.

\subsection{JTAG DTM Registers}

JTAG TAPs used as a DTM must have an IR of at least 5 bits.
When the TAP is reset, IR must default to
00001, selecting the IDCODE instruction. A full list of JTAG registers along
with their encoding is in Table~\ref{table:jtag_registers}.
If the IR actually has more than 5 bits, then the encodings in
Table~\ref{table:jtag_registers} should be extended with 0's in their
most significant bits.
The only regular JTAG registers a debugger might use are BYPASS and IDCODE, but this
specification leaves IR space for many other standard JTAG instructions.
Unimplemented instructions must select the BYPASS register.

\input{jtag_registers.tex}

\subsection{Recommended JTAG Connector}

To make it easy to
acquire debug hardware, this spec recommends a connector that is compatible
with the Atmel AVR JTAG Connector, as described below.

The connector is a .05"-spaced, gold-plated male header with .016" thick
hardened copper or beryllium bronze square posts (SAMTEC FTSH-105 or
equivalent). Female connectors are compatible $20\mu m$ gold
connectors.

Viewing the male header from above (the pins pointing at your eye), a target's
connector looks as it does in Table~\ref{tab:header}. The function of each pin
is described in Table~\ref{tab:pinout}.

\begin{table}[htp]
    \centering
    \caption{JTAG Connector Diagram}
    \label{tab:header}
    \begin{tabulary}{\textwidth}{|R|c|c|L|}
        \hline
        TCK & 1 & 2 & GND \\
        \hline
        TDO & 3 & 4 & VCC \\
        \hline
        TMS & 5 & 6 & (SRSTn) \\
        \hline
        (NC) & 7 & 8 & (TRSTn) \\
        \hline
        TDI & 9 & 10 & GND \\
        \hline
    \end{tabulary}
\end{table}

\begin{table}[htp]
    \centering
    \caption{JTAG Connector Pinout}
    \label{tab:pinout}
    \begin{tabulary}{\textwidth}{|r|c|L|}
      \hline
      1 & TCK & JTAG TCK signal, driven by the debug adapter.
      This pin must be clearly marked in both male and female headers.\\
      \hline
      5 & TMS & JTAG TMS signal, driven by debug adapter. \\
      \hline
      9 & TDI & JTAG TDI signal, driven by the debug adapter. \\
      \hline
      3 & TDO & JTAG TDO signal, driven by the target. \\
      \hline
      8 & TRSTn & Test Reset (optional, only used by some devices. Used to reset the JTAG TAP Controller).\\
      \hline
      4 & VCC &
      Reference voltage for logic high. A debug adapter may attempt to draw up
      to 20mA from this pin to power itself, but a target is not obligated to
      provide that power. \\
      \hline
      2, 10 & GND & Target ground. \\
      \hline
      6 & SRSTn & Active-low reset signal, driven by the debug adapter.
      Asserting reset should
      reset any RISC-V cores as well as any other peripherals on the PCB.
      It should not reset the debug logic.
      Although connecting this pin is optional, it is recommended as it allows
      the debugger to hold the target device in a reset state, which may be essential
      to debug some scenarios.
      If not implemented in a target, this pin must not be connected. \\
      \hline
    \end{tabulary}
\end{table}

Target connectors may be shrouded. In that case the key slot should be next to
pin 5. Female headers should have a matching key.

Debug adapters should be tagged or marked with their isolation voltage
threshold (i.e. unisolated, 250V, etc.).

All debug adapter pins other than GND should be current-limited to 20mA.
