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riscv
riscv-debug-spec
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makefile
c287f4ff
·
Make `make clean` more exhaustive.
·
Aug 15, 2023
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native
5a5c86fc
·
AR: Define "native debug" in Background section.
·
Aug 15, 2023
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execute_cache
e3671acb
·
Recommend debug ROM is not cached.
·
Aug 15, 2023
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message_reg
b6cbb1cb
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AR: Clarify message register uses.
·
Aug 15, 2023
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nonexistent
83483b1f
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AR: Don't use "non-existent" in reference to register.
·
Aug 21, 2023
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exception
4970b557
·
AR: Can't require exception for CSR access.
·
Aug 22, 2023
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dmi_address
470ca90a
·
Clarify that each DMI address points at a 32-bit register.
·
Aug 24, 2023
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debug_defines_make
0b46055c
·
Fix debug_defines make process.
·
Nov 01, 2023
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concise_regdump
bdae19a8
·
Make register dump output more concise.
·
Nov 03, 2023
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invalid_virtual_address
eccbb902
·
Clarify matching on invalid virtual addresses may not be possible.
·
Nov 03, 2023
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uncertain
c62e4ccc
·
uncertain is updated when trigger fires.
·
Nov 29, 2023
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tm_reg
f6adeec0
·
Refer to "trigger registers" as "Trigger Module Registers"
·
Dec 01, 2023
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trigger_access
d785d172
·
Trigger CSRs provide access to underlying triggers.
·
Dec 04, 2023
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full_tdata2
be76e080
·
Don't allow tdata2 to be smaller for address matches.
·
Dec 04, 2023
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sdtrig_reset
a75169ef
·
CSR reset values apply to underlying triggers.
·
Dec 05, 2023
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parens
59225942
·
tools: Remove unnecessary parens.
·
Dec 06, 2023
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rpsene-patch-ghactions-update
d6917da7
·
Update verify.yml
·
Dec 19, 2023
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adoc_xml
2815a237
·
Install python3-sympy for build.
·
Dec 19, 2023
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verify_pr
03ec4d1c
·
Also run verify in PR relative to asciidoc.
·
Dec 20, 2023
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adoc_fmt
d6ea223f
·
Get register table formatting closer to what we want.
·
Dec 20, 2023
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