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riscv
riscv-debug-spec
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dmactive
ca36be78
·
DM may ignore things when dmactive is changing.
·
Jun 13, 2024
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main
55b11d12
·
Merge pull request #1042 from albert-azcarate/mepc-typo
·
Jun 05, 2024
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native_trigger_typo
72a0ccf1
·
"Native Triggers": Add in mepc/mcause back in.
·
Apr 25, 2024
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maskmax6_detect
8e09b386
·
Update maskmax6 detection algorithm to always work
·
Apr 25, 2024
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action_warl
68a7eb81
·
Simplify WARL description for dmode=0 and action=1.
·
Apr 25, 2024
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extcause
75e1d26f
·
Rephrase critical error value; expand cetrig note
·
Apr 24, 2024
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Sddbltrp
646d02aa
·
Add dcsr.cetrig for Sddbltrp
·
Apr 15, 2024
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action_table
34e80267
·
Fix Action encoding table column width.
·
Apr 12, 2024
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formatting
e80c1b85
·
Add missing space.
·
Mar 29, 2024
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rc2
766491ca
·
Merge branch 'main' into rc2
·
Mar 21, 2024
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load_data_before
f8dad44a
·
Load data before trigger priority was ambiguous.
·
Mar 21, 2024
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context
762ae29c
·
In Sdtrig, XLEN refers to the current mode.
·
Mar 18, 2024
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xlen
ceb87097
·
Remove Section 4.9: XLEN
·
Mar 12, 2024
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dxlen
dce58976
·
Fix asciidoc conversion for DXLEN definition.
·
Mar 11, 2024
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csr_xlen
bf099ee7
·
Clarify textra behavior when XLEN changes.
·
Mar 04, 2024
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table_space
f5275482
·
Ensure a newline at the end of registers description
·
Feb 29, 2024
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hartset
6c800cde
·
Fix `hartset` -> {hartsel}
·
Feb 23, 2024
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master
default
protected
cc2b4600
·
Merge pull request #971 from riscv/merge_asciidoc
·
Feb 21, 2024
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merge_asciidoc
a1bef9b5
·
Update README links to "latest" versions.
·
Feb 21, 2024
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asciidoc
b079fc1d
·
Merge pull request #970 from riscv/diagram_spacing
·
Feb 14, 2024
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