<registers name="Debug Module Debug Bus Registers" prefix="DMI_">

    <!-- =============== halt/reset/select hart  =============== -->

    <register name="Debug Module Status" short="dmstatus" address="0x11">
        This register reports status for the overall Debug Module as well as
        the currently selected harts, as defined in \Fhasel.  Its address will
        not change in the future, because it contains \Fversion.  It has
        changed from version 0.11 of this spec.

        Harts are nonexistent if they will never be part of this system, no
        matter how long a user waits. Eg. in a simple single-hart system only
        one hart exists, and all others are nonexistent. Debuggers may assume
        that a system has no harts with indexes higher than the first
        nonexistent one.

        Harts are unavailable if they might exist/become available at a later
        time, or if there are other harts with higher indexes than this one. Eg.
        in a multi-hart system some might temporarily be powered down, or a
        system might support hot-swapping harts. Systems with very large number
        of harts may permanently disable some during manufacturing, leaving
        holes in the otherwise continuous hart index space. In order to let the
        debugger discover all harts, they must show up as unavailable even if
        there is no chance of them ever becoming available.

        <field name="0" bits="31:23" access="R" reset="0" />
        <field name="impebreak" bits="22" access="R" reset="Preset">
            If 1, then there is an implicit {\tt ebreak} instruction at the
            non-existent word immediately after the Program Buffer. This saves
            the debugger from having to write the {\tt ebreak} itself, and
            allows the Program Buffer to be one word smaller.

            This must be 1 when \Fprogbufsize is 1.
        </field>
        <field name="0" bits="21:20" access="R" reset="0" />
        <field name="allhavereset" bits="19" access="R" reset="-">
          This field is 1 when all currently selected harts have been reset but the reset has not been acknowledged.
        </field>
        <field name="anyhavereset" bits="18" access="R" reset="-">
          This field is 1 when any currently selected hart has been reset but the reset has not been acknowledged.
        </field>
        <field name="allresumeack" bits="17" access="R" reset="-">
            This field is 1 when all currently selected harts have acknowledged
            the previous resume request.
        </field>
        <field name="anyresumeack" bits="16" access="R" reset="-">
            This field is 1 when any currently selected hart has acknowledged
            the previous resume request.
        </field>
        <field name="allnonexistent" bits="15" access="R" reset="-">
          This field is 1 when all currently selected harts do not exist in this system.
        </field>
        <field name="anynonexistent" bits="14" access="R" reset="-">
          This field is 1 when any currently selected hart does not exist in this system.
        </field>
        <field name="allunavail" bits="13" access="R" reset="-">
          This field is 1 when all currently selected harts are unavailable.
        </field>
        <field name="anyunavail" bits="12" access="R" reset="-">
          This field is 1 when any currently selected hart is unavailable.
        </field>
        <field name="allrunning" bits="11" access="R" reset="-">
          This field is 1 when all currently selected harts are running.
        </field>
        <field name="anyrunning" bits="10" access="R" reset="-">
          This field is 1 when any currently selected hart is running.
        </field>
        <field name="allhalted" bits="9" access="R" reset="-">
          This field is 1 when all currently selected harts are halted.
        </field>
        <field name="anyhalted" bits="8" access="R" reset="-">
          This field is 1 when any currently selected hart is halted.
        </field>

        <!-- Fields that apply to the entire DM. -->
        <field name="authenticated" bits="7" access="R" reset="Preset">
            0 when authentication is required before using the DM.  1 when the
            authentication check has passed. On components that don't implement
            authentication, this bit must be preset as 1.
        </field>
        <field name="authbusy" bits="6" access="R" reset="0">
            0: The authentication module is ready to process the next
            read/write to \Rauthdata.

            1: The authentication module is busy. Accessing \Rauthdata results
            in unspecified behavior.

            \Fauthbusy only becomes set in immediate response to an access to
            \Rauthdata.
        </field>
        <field name="hasresethaltreq" bits="5" reset="Preset" access="R">
            1 if this Debug Module supports halt-on-reset functionality
            controllable by the \Fsetresethaltreq and \Fclrresethaltreq bits.
            0 otherwise.
        </field>
        <field name="devtreevalid" bits="4" reset="Preset" access="R">
            0: \Rdevtreeaddrzero--\Rdevtreeaddrthree hold information which
            is not relevant to the Device Tree.

            1: \Rdevtreeaddrzero--\Rdevtreeaddrthree registers hold the address of the
            Device Tree.
        </field>
        <field name="version" bits="3:0" reset="2" access="R">
            0: There is no Debug Module present.

            1: There is a Debug Module and it conforms to version 0.11 of this
            specification.

            2: There is a Debug Module and it conforms to version 0.13 of this
            specification.

            15: There is a Debug Module but it does not conform to any
            available version of this spec.
        </field>
    </register>

    <register name="Debug Module Control" short="dmcontrol" address="0x10">
        This register controls the overall Debug Module
        as well as the currently selected harts, as defined in \Fhasel.

\label{hartsel}
\index{hartsel}
        Throughout this document we refer to \Fhartsel, which is \Fhartselhi
        combined with \Fhartsello. While the spec allows for 20 \Fhartsel bits,
        an implementation may choose to implement fewer than that. The actual
        width of \Fhartsel is called {\tt HARTSELLEN}. It must be at least 0
        and at most 20. A debugger should discover {\tt HARTSELLEN} by writing
        all ones to \Fhartsel (assuming the maximum size) and reading back the
        value to see which bits were actually set.

        <!-- Fields that apply to all selected hart(s) -->
        <field name="haltreq" bits="31" access="W" reset="-">
            Writes the halt request bit for all currently selected harts.
            When set to 1, each selected hart will halt if it is not currently
            halted.

            Writing 1 or 0 has no effect on a hart which is already halted, but
            the bit must be cleared to 0 before the hart is resumed.

            Writes apply to the new value of \Fhartsel and \Fhasel.
        </field>
        <field name="resumereq" bits="30" access="W" reset="-">
            Writes the resume request bit for all currently selected harts.
            When set to 1, each selected hart will resume if it is currently
            halted.

            The resume request bit is ignored while the halt request bit is
            set.

            Writes apply to the new value of \Fhartsel and \Fhasel.
        </field>
        <field name="hartreset" bits="29" access="R/W" reset="0">
            This optional field writes the reset bit for all the currently
            selected harts.  To perform a reset the debugger writes 1, and then
            writes 0 to deassert the reset signal.

            If this feature is not implemented, the bit always stays 0, so
            after writing 1 the debugger can read the register back to see if
            the feature is supported.

            Writes apply to the new value of \Fhartsel and \Fhasel.
        </field>
        <field name="ackhavereset" bits="28" access="W" reset="-">
            Writing 1 to this bit clears the {\tt havereset} bits for
            any selected harts.

            Writes apply to the new value of \Fhartsel and \Fhasel.
        </field>
        <field name="0" bits="27" access="R" reset="0" />
        <field name="hasel" bits="26" access="R/W" reset="0">
            Selects the  definition of currently selected harts.

            0: There is a single currently selected hart, that selected by \Fhartsel.

            1: There may be multiple currently selected harts -- that selected by \Fhartsel,
               plus those selected by the hart array mask register.

            An implementation which does not implement the hart array mask register
            must tie this field to 0. A debugger which wishes to use the hart array
            mask register feature should set this bit and read back to see if the functionality
            is supported.
        </field>
        <field name="hartsello" bits="25:16" access="R/W" reset="0">
            The low 10 bits of \Fhartsel: the DM-specific index of the hart to
            select. This hart is always part of the currently selected harts.
        </field>
        <field name="hartselhi" bits="15:6" access="R/W" reset="0">
            The high 10 bits of \Fhartsel: the DM-specific index of the hart to
            select. This hart is always part of the currently selected harts.
        </field>
        <field name="0" bits="5:4" access="R" reset="0" />
        <field name="setresethaltreq" bits="3" access="W" reset="0">
            This optional field writes the halt-on-reset request bit for all
            currently selected harts.
            When set to 1, each selected hart will halt upon the next deassertion
            of its reset. The halt-on-reset request bit is not automatically
            cleared. The debugger must write to \Fclrresethaltreq to clear it.

            Writes apply to the new value of \Fhartsel and \Fhasel.

            If \Fhasresethaltreq is 0, this field is not implemented.
        </field>
        <field name="clrresethaltreq" bits="2" access="W" reset="0">
            This optional field clears the halt-on-reset request bit for all
            currently selected harts.

            Writes apply to the new value of \Fhartsel and \Fhasel.
        </field>
        <!-- Fields that apply to the entire DM. -->
        <field name="ndmreset" bits="1" access="R/W" reset="0">
            This bit controls the reset signal from the DM to the rest of the
            system. The signal should reset every part of the system, including
            every hart, except for the DM and any logic required to access the
            DM.
            To perform a system reset the debugger writes 1,
            and then writes 0
            to deassert the reset.
        </field>
        <field name="dmactive" bits="0" access="R/W" reset="0">
            This bit serves as a reset signal for the Debug Module itself.

            0: The module's state, including authentication mechanism,
            takes its reset values (the \Fdmactive bit is the only bit which can
            be written to something other than its reset value).

            1: The module functions normally.

            No other mechanism should exist that may result in resetting the
            Debug Module after power up, including the platform's system reset
            or Debug Transport reset signals.

            A debugger may pulse this bit low to get the Debug Module into a
            known state.

            Implementations may use this bit to aid debugging, for example by
            preventing the Debug Module from being power gated while debugging
            is active.
        </field>
    </register>

    <register name="Hart Info" short="hartinfo" address="0x12">
      This register gives information about the hart currently
      selected by \Fhartsel.

      This register is optional. If it is not present it should
      read all-zero.

      If this register is included, the debugger can do more with
      the Program Buffer by writing programs which
      explicitly access the {\tt data} and/or {\tt dscratch}
      registers.

        <field name="0" bits="31:24" access="R" reset="0" />
        <field name="nscratch" bits="23:20" access="R" reset="Preset">
            Number of {\tt dscratch} registers available for the debugger
            to use during program buffer execution, starting from \Rdscratchzero.
            The debugger can make no assumptions about the contents of these
            registers between commands.
        </field>
        <field name="0" bits="19:17" access="R" reset="0" />
        <field name="dataaccess" bits="16" access="R" reset="Preset">
            0: The {\tt data} registers are shadowed in the hart by CSR
            registers. Each CSR register is MXLEN bits in size, and corresponds
            to a single argument, per Table~\ref{tab:datareg}.

            1: The {\tt data} registers are shadowed in the hart's memory map.
            Each register takes up 4 bytes in the memory map.
        </field>
        <field name="datasize" bits="15:12" access="R" reset="Preset">
            If \Fdataaccess is 0: Number of CSR registers dedicated to
            shadowing the {\tt data} registers.

            If \Fdataaccess is 1: Number of 32-bit words in the memory map
            dedicated to shadowing the {\tt data} registers.

            Since there are at most 12 {\tt data} registers, the value in this
            register must be 12 or smaller.
        </field>
        <field name="dataaddr" bits="11:0" access="R" reset="Preset">
            If \Fdataaccess is 0: The number of the first CSR dedicated to
            shadowing the {\tt data} registers.

            If \Fdataaccess is 1: Signed address of RAM where the {\tt data}
            registers are shadowed, to be used to access relative to \Rzero.
        </field>
    </register>

    <!-- =============== Hart Array Registers =============== -->

    <register name="Hart Array Window Select" short="hawindowsel" address="0x14">
      This register selects which of the 32-bit portion of the hart array mask
      register (see Section~\ref{hartarraymask}) is accessible in \Rhawindow.

      <field name="0" bits="31:15" access="R/W" reset="0" />
      <field name="hawindowsel" bits="14:0" access="R/W" reset="0">
          The high bits of this field may be tied to 0, depending on how large
          the array mask register is.  Eg. on a system with 48 harts only bit 0
          of this field may actually be writable.
      </field>
    </register>

    <register name="Hart Array Window " short="hawindow" address="0x15">
      This register provides R/W access to a 32-bit portion of the
      hart array mask register (see Section~\ref{hartarraymask}).
      The position of the window is determined by \Rhawindowsel. I.e. bit 0
      refers to hart $\Rhawindowsel * 32$, while bit 31 refers to hart
      $\Rhawindowsel * 32 + 31$.

      Since some bits in the hart array mask register may be constant 0, some
      bits in this register may be constant 0, depending on the current value
      of \Fhawindowsel.
      <field name="maskdata" bits="31:0" access="R/W" reset="0" />
    </register>

    <!-- =============== abstract commands =============== -->

    <register name="Abstract Control and Status" short="abstractcs" address="0x16">
        Writing this register while an abstract command is executing causes
        \Fcmderr to be set to 1 (busy) if it is 0.

        \begin{commentary}
            \Fdatacount must be at least 1 to support RV32 harts, 2 to support
            RV64 harts, or 4 to support RV128 harts.
        \end{commentary}

                <field name="0" bits="31:29" access="R" reset="0" />
        <field name="progbufsize" bits="28:24" access="R" reset="Preset">
            Size of the Program Buffer, in 32-bit words. Valid sizes are 0 - 16.
        </field>
        <field name="0" bits="23:13" access="R" reset="0" />
        <field name="busy" bits="12" access="R" reset="0">
            1: An abstract command is currently being executed.

            This bit is set as soon as \Rcommand is written, and is
            not cleared until that command has completed.
        </field>
        <field name="0" bits="11" access="R" reset="0" />
        <field name="cmderr" bits="10:8" access="R/W1C" reset="0">
            Gets set if an abstract command fails. The bits in this field remain set until
            they are cleared by writing 1 to them. No abstract command is
            started until the value is reset to 0.

            This field only contains a valid value if \Fbusy is 0.

            0 (none): No error.

            1 (busy): An abstract command was executing while \Rcommand,
            \Rabstractcs, \Rabstractauto was written, or when one
            of the {\tt data} or {\tt progbuf} registers was read or written.
            This status is only written if \Fcmderr contains 0.

            2 (not supported): The requested command is not supported,
            regardless of whether the hart is running or not.

            3 (exception): An exception occurred while executing the command
            (eg. while executing the Program Buffer).

            4 (halt/resume): The abstract command couldn't execute because the
            hart wasn't in the required state (running/halted).

            5 (bus): The abstract command failed due to a bus error (eg.
            alignment, access size, timeout).

            7 (other): The command failed for another reason.
        </field>
        <field name="0" bits="7:4" access="R" reset="0"/>
        <field name="datacount" bits="3:0" access="R" reset="Preset">
            Number of {\tt data} registers that are implemented as part of the
            abstract command interface. Valid sizes are 1 -- 12.
        </field>
    </register>

    <register name="Abstract Command" short="command" address="0x17">
        Writes to this register cause the corresponding abstract command to be
        executed.

        Writing this register while an abstract command is executing causes
        \Fcmderr to be set to 1 (busy) if it is 0.

        If \Fcmderr is non-zero, writes to this register are ignored.

        \begin{commentary}
            \Fcmderr inhibits starting a new command to accommodate debuggers
            that, for performance reasons, send several commands to be executed
            in a row without checking \Fcmderr in between. They can safely do
            so and check \Fcmderr at the end without worrying that one command
            failed but then a later command (which might have depended on the
            previous one succeeding) passed.
        \end{commentary}

        <field name="cmdtype"    bits="31:24" access="W" reset="0">
            The type determines the overall functionality of this
            abstract command.
        </field>
        <field name="control" bits="23:0" access="W" reset="0" >
            This field is interpreted in a command-specific manner,
            described for each abstract command.
        </field>
    </register>

    <register name ="Abstract Command Autoexec" short="abstractauto" address="0x18">
        This register is optional. Including it allows more efficient burst
        accesses.  A debugger can detect whether it is support by setting bits
        and reading them back.

        Writing this register while an abstract command is executing causes
        \Fcmderr to be set to 1 (busy) if it is 0.

        <field name="autoexecprogbuf" bits="31:16" access="R/W" reset="0">
            When a bit in this field is 1, read or write accesses to the
            corresponding {\tt progbuf} word cause the command in \Rcommand to
            be executed again.
        </field>
        <field name="0" bits ="15:12" access="R" reset = "0"/>
        <field name="autoexecdata" bits="11:0" access="R/W" reset="0">
            When a bit in this field is 1, read or write accesses to the
            corresponding {\tt data} word cause the command in \Rcommand to be
            executed again.
        </field>
    </register>

    <register name="Device Tree Addr 0" short="devtreeaddr0" address="0x19">
      When {\tt devtreevalid} is set, reading this register returns bits 31:0
      of the Device Tree address. Reading the other {\tt devtreeaddr}
      registers returns the upper bits of the address.

      When system bus mastering is implemented, this must be an
      address that can be used with the System Bus Access module. Otherwise,
      this must be an address that can be used to access the
      Device Tree from the hart with ID 0.

      If {\tt devtreevalid} is 0, then the {\tt devtreeaddr} registers
      hold identifier information which is not
      further specified in this document.

      The Device Tree itself is described in the RISC-V Privileged
      Specification.
      <field name="addr" bits="31:0" access="R" reset="Preset"/>
    </register>
    <register name="Device Tree Addr 1" short="devtreeaddr1" address="0x1a"/>
    <register name="Device Tree Addr 2" short="devtreeaddr2" address="0x1b"/>
    <register name="Device Tree Addr 3" short="devtreeaddr3" address="0x1c"/>

    <register name="Next Debug Module" short="nextdm" address="0x1d">
        If there is more than one DM accessible on this DMI, this register
        contains the base address of the next one in the chain, or 0 if this is
        the last one in the chain.

        <field name="addr" bits="31:0" access="R" reset="Preset"/>
    </register>

    <register name="Abstract Data 0" short="data0" address="0x04">
        \Rdatazero through \Rdataeleven are basic read/write registers that may
        be read or changed by abstract commands. \Fdatacount indicates how many
        of them are implemented, starting at \Rdatazero, counting up.
        Table~\ref{tab:datareg} shows how abstract commands use these
        registers.

        Accessing these registers while an abstract command is executing causes
        \Fcmderr to be set to 1 (busy) if it is 0.

        Attempts to write them while \Fbusy is set does not change their value.

        The values in these registers may not be preserved after an abstract
        command is executed. The only guarantees on their contents are the ones
        offered by the command in question. If the command fails, no
        assumptions can be made about the contents of these registers.

        <field name="data" bits="31:0" access="R/W" reset="0" />
    </register>
    <!--
    <register name="Abstract Data 1" short="data1" address="0x05" />
    <register name="Abstract Data 2" short="data2" address="0x06" />
    <register name="Abstract Data 3" short="data3" address="0x07" />
    <register name="Abstract Data 4" short="data4" address="0x08" />
    <register name="Abstract Data 5" short="data5" address="0x09" />
    <register name="Abstract Data 6" short="data6" address="0x0a" />
    <register name="Abstract Data 7" short="data7" address="0x0b" />
    <register name="Abstract Data 8" short="data8" address="0x0c" />
    <register name="Abstract Data 9" short="data9" address="0x0d" />
    <register name="Abstract Data 10" short="data10" address="0x0e" />
    -->
    <register name="Abstract Data 11" short="data11" address="0x0f" />

    <!-- =============== Program Buffer =============== -->

    <register name="Program Buffer 0" short="progbuf0" address="0x20">
        \Rprogbufzero through \Rprogbuffifteen provide read/write access to the
        optional program buffer. \Fprogbufsize indicates how many of them are
        implemented starting at \Rprogbufzero, counting up.

        Accessing these registers while an abstract command is executing causes
        \Fcmderr to be set to 1 (busy) if it is 0.

        Attempts to write them while \Fbusy is set does not change their value.

        <field name="data" bits="31:0" access="R/W" reset="0" />
    </register>
    <!--
    <register name="Program Buffer 1" short="progbuf1" address="0x21" />
    <register name="Program Buffer 2" short="progbuf2" address="0x22" />
    <register name="Program Buffer 3" short="progbuf3" address="0x23" />
    <register name="Program Buffer 4" short="progbuf4" address="0x24" />
    <register name="Program Buffer 5" short="progbuf5" address="0x25" />
    <register name="Program Buffer 6" short="progbuf6" address="0x26" />
    <register name="Program Buffer 7" short="progbuf7" address="0x27" />
    <register name="Program Buffer 8" short="progbuf8" address="0x28" />
    <register name="Program Buffer 9" short="progbuf9" address="0x29" />
    <register name="Program Buffer 10" short="progbuf10" address="0x2a" />
    <register name="Program Buffer 11" short="progbuf11" address="0x2b" />
    <register name="Program Buffer 12" short="progbuf12" address="0x2c" />
    <register name="Program Buffer 13" short="progbuf13" address="0x2d" />
    <register name="Program Buffer 14" short="progbuf14" address="0x2e" />
    -->
    <register name="Program Buffer 15" short="progbuf15" address="0x2f" />
 
    <!-- =============== authentication =============== -->

    <register name="Authentication Data" short="authdata" address="0x30">
        This register serves as a 32-bit serial port to the authentication
        module.

        When \Fauthbusy is clear, the debugger can communicate with the
        authentication module by reading or writing this register. There is no
        separate mechanism to signal overflow/underflow.

        <field name="data" bits="31:0" access="R/W" reset="0" />
    </register>

    <register name="Halt Summary 0" short="haltsum0" address="0x40">
        Each bit in this read-only register indicates whether one specific hart
        is halted or not. Unavailable/nonexistent harts are not considered to
        be halted.

        The LSB reflects the halt status of hart \{hartsel[19:5],5'h0\}, and the
        MSB reflects halt status of hart \{hartsel[19:5],5'h1f\}.

        <field name="haltsum0" bits="31:0" access="R" reset="0" />
    </register>

    <register name="Halt Summary 1" short="haltsum1" address="0x13">
        Each bit in this read-only register indicates whether any of a group of
        harts is halted or not. Unavailable/nonexistent harts are not considered to
        be halted.

        This register may not be present in systems with fewer than
        33 harts.

        The LSB reflects the halt status of harts \{hartsel[19:10],10'h0\}
        through \{hartsel[19:10],10'h1f\}.
        The MSB reflects the halt status of harts \{hartsel[19:10],10'h3e0\}
        through \{hartsel[19:10],10'h3ff\}.

        <field name="haltsum1" bits="31:0" access="R" reset="0" />
    </register>

    <register name="Halt Summary 2" short="haltsum2" address="0x34">
        Each bit in this read-only register indicates whether any of a group of
        harts is halted or not. Unavailable/nonexistent harts are not considered to
        be halted.

        This register may not be present in systems with fewer than
        1025 harts.

        The LSB reflects the halt status of harts \{hartsel[19:15],15'h0\}
        through \{hartsel[19:15],15'h3ff\}.
        The MSB reflects the halt status of harts \{hartsel[19:15],15'h7c00\}
        through \{hartsel[19:15],15'h7fff\}.

        <field name="haltsum2" bits="31:0" access="R" reset="0" />
    </register>

    <register name="Halt Summary 3" short="haltsum3" address="0x35">
        Each bit in this read-only register indicates whether any of a group of
        harts is halted or not. Unavailable/nonexistent harts are not considered to
        be halted.

        This register may not be present in systems with fewer than
        32769 harts.

        The LSB reflects the halt status of harts 20'h0 through 20'h7fff.
        The MSB reflects the halt status of harts 20'hf8000 through 20'hfffff.

        <field name="haltsum3" bits="31:0" access="R" reset="0" />
    </register>

    <!-- =============== system bus mastering =============== -->

    <register name="System Bus Address 127:96" short="sbaddress3" address="0x37">
        If \Fsbasize is less than 97, then this register is not present.

        When the system bus master is busy, writes to this register will set
        \Fsbbusyerror and don't do anything else.

        <field name="address" bits="31:0" access="R/W" reset="0">
            Accesses bits 127:96 of the physical address in {\tt sbaddress} (if
            the system address bus is that wide).
        </field>
    </register>

    <register name="System Bus Access Control and Status" short="sbcs" address="0x38">
        <field name="sbversion" bits="31:29" access="R" reset="1">
            0: The System Bus interface conforms to mainline drafts of this
            spec older than 1 January, 2018.

            1: The System Bus interface conforms to this version of the spec.

            Other values are reserved for future versions.
        </field>
        <field name="0" bits="28:23" access="R" reset="0" />
        <field name="sbbusyerror" bits="22" access="R/W1C" reset="0">
            Set when the debugger attempts to read data while a read is in
            progress, or when the debugger initiates a new access while one is
            already in progress (while \Fsbbusy is set). It remains set until
            it's explicitly cleared by the debugger.

            While this field is non-zero, no more system bus accesses can be
            initiated by the Debug Module.
        </field>
        <field name="sbbusy" bits="21" access="R" reset="0">
            When 1, indicates the system bus master is busy. (Whether the
            system bus itself is busy is related, but not the same thing.) This
            bit goes high immediately when a read or write is requested for any
            reason, and does not go low until the access is fully completed.

            Writes to \Rsbcs while \Fsbbusy is high result in undefined
            behavior.  A debugger must not write to \Rsbcs until it reads
            \Fsbbusy as 0.
        </field>
        <field name="sbreadonaddr" bits="20" access="R/W" reset="0">
            When 1, every write to \Rsbaddresszero automatically triggers a
            system bus read at the new address.
        </field>
        <field name="sbaccess" bits="19:17" access="R/W" reset="2">
            Select the access size to use for system bus accesses.

            0: 8-bit

            1: 16-bit

            2: 32-bit

            3: 64-bit

            4: 128-bit

            If \Fsbaccess has an unsupported value when the DM starts a bus
            access, the access is not performed and \Fsberror is set to 3.
        </field>
        <field name="sbautoincrement" bits="16" access="R/W" reset="0">
            When 1, {\tt sbaddress} is incremented by the access size (in
            bytes) selected in \Fsbaccess after every system bus access.
        </field>
        <field name="sbreadondata" bits="15" access="R/W" reset="0">
            When 1, every read from \Rsbdatazero automatically triggers a
            system bus read at the (possibly auto-incremented) address.
        </field>
        <field name="sberror" bits="14:12" access="R/W1C" reset="0">
            When the Debug Module's system bus
            master causes a bus error, this field gets set. The bits in this
            field remain set until they are cleared by writing 1 to them.
            While this field is non-zero, no more system bus accesses can be
            initiated by the Debug Module.

            An implementation may report "Other" (7) for any error condition.

            0: There was no bus error.

            1: There was a timeout.

            2: A bad address was accessed.

            3: There was an alignment error.

            4: An access of unsupported size was requested.

            7: Other.
        </field>
        <field name="sbasize" bits="11:5" access="R" reset="Preset">
            Width of system bus addresses in bits. (0 indicates there is no bus
            access support.)
        </field>
        <field name="sbaccess128" bits="4" access="R" reset="Preset">
            1 when 128-bit system bus accesses are supported.
        </field>
        <field name="sbaccess64" bits="3" access="R" reset="Preset">
            1 when 64-bit system bus accesses are supported.
        </field>
        <field name="sbaccess32" bits="2" access="R" reset="Preset">
            1 when 32-bit system bus accesses are supported.
        </field>
        <field name="sbaccess16" bits="1" access="R" reset="Preset">
            1 when 16-bit system bus accesses are supported.
        </field>
        <field name="sbaccess8" bits="0" access="R" reset="Preset">
            1 when 8-bit system bus accesses are supported.
        </field>
    </register>

    <register name="System Bus Address 31:0" short="sbaddress0" address="0x39">
        If \Fsbasize is 0, then this register is not present.

        When the system bus master is busy, writes to this register will set
        \Fsbbusyerror and don't do anything else.

        \begin{steps}{If \Fsberror is 0, \Fsbbusyerror is 0, and \Fsbreadonaddr
        is set then writes to this register start the following:}
            \item Set \Fsbbusy.
            \item Perform a bus read from the new value of {\tt sbaddress}.
            \item If the read succeeded and \Fsbautoincrement is set, increment
            {\tt sbaddress}.
            \item Clear \Fsbbusy.
        \end{steps}

        <field name="address" bits="31:0" access="R/W" reset="0">
            Accesses bits 31:0 of the physical address in {\tt sbaddress}.
        </field>
    </register>

    <register name="System Bus Address 63:32" short="sbaddress1" address="0x3a">
        If \Fsbasize is less than 33, then this register is not present.

        When the system bus master is busy, writes to this register will set
        \Fsbbusyerror and don't do anything else.

        <field name="address" bits="31:0" access="R/W" reset="0">
            Accesses bits 63:32 of the physical address in {\tt sbaddress} (if
            the system address bus is that wide).
        </field>
    </register>

    <register name="System Bus Address 95:64" short="sbaddress2" address="0x3b">
        If \Fsbasize is less than 65, then this register is not present.

        When the system bus master is busy, writes to this register will set
        \Fsbbusyerror and don't do anything else.

        <field name="address" bits="31:0" access="R/W" reset="0">
            Accesses bits 95:64 of the physical address in {\tt sbaddress} (if
            the system address bus is that wide).
        </field>
    </register>

    <register name="System Bus Data 31:0" short="sbdata0" address="0x3c">
        If all of the {\tt sbaccess} bits in \Rsbcs are 0, then this register
        is not present.

        Any successful system bus read updates {\tt sbdata}. If the width of
        the read access is less than the width of {\tt sbdata}, the contents of
        the remaining high bits may take on any value.

        If \Fsberror or \Fsbbusyerror both aren't 0 then accesses do nothing.

        If the bus master is busy then accesses set \Fsbbusyerror, and don't do
        anything else.

        \begin{steps}{Writes to this register start the following:}
            \item Set \Fsbbusy.
            \item Perform a bus write of the new value of {\tt sbdata} to {\tt sbaddress}.
            \item If the write succeeded and \Fsbautoincrement is set,
            increment {\tt sbaddress}.
            \item Clear \Fsbbusy.
        \end{steps}

        \begin{steps}{Reads from this register start the following:}
            \item ``Return'' the data.
            \item Set \Fsbbusy.
            \item If \Fsbautoincrement is set, increment {\tt sbaddress}.
            \item If \Fsbreadondata is set, perform another system bus read.
            \item Clear \Fsbbusy.
        \end{steps}

        Only \Rsbdatazero has this behavior. The other {\tt sbdata} registers
        have no side effects. On systems that have buses wider than 32 bits, a
        debugger should access \Rsbdatazero after accessing the other {\tt
        sbdata} registers.

        <field name="data" bits="31:0" access="R/W" reset="0">
            Accesses bits 31:0 of {\tt sbdata}.
        </field>
    </register>

    <register name="System Bus Data 63:32" short="sbdata1" address="0x3d">
        If \Fsbaccesssixtyfour and \Fsbaccessonetwentyeight are 0, then this
        register is not present.

        If the bus master is busy then accesses set \Fsbbusyerror, and don't do
        anything else.

        <field name="data" bits="31:0" access="R/W" reset="0">
            Accesses bits 63:32 of {\tt sbdata} (if the system bus is that
            wide).
        </field>
    </register>

    <register name="System Bus Data 95:64" short="sbdata2" address="0x3e">
        This register only exists if \Fsbaccessonetwentyeight is 1.

        If the bus master is busy then accesses set \Fsbbusyerror, and don't do
        anything else.

        <field name="data" bits="31:0" access="R/W" reset="0">
            Accesses bits 95:64 of {\tt sbdata} (if the system bus is that
            wide).
        </field>
    </register>

    <register name="System Bus Data 127:96" short="sbdata3" address="0x3f">
        This register only exists if \Fsbaccessonetwentyeight is 1.

        If the bus master is busy then accesses set \Fsbbusyerror, and don't do
        anything else.

        <field name="data" bits="31:0" access="R/W" reset="0">
            Accesses bits 127:96 of {\tt sbdata} (if the system bus is that
            wide).
        </field>
    </register>

</registers>
