<registers name="Virtual Core Debug Registers" prefix="VIRT_">
  Users of the debugger shouldn't need to know about the core debug registers,
  but may want to change things affected by them. 
     A virtual register is one that doesn't exist directly in the hardware, but that the debugger exposes as if it does. 
    
     <register name="Privilege Level" short="priv" address="virtual">
        User can read this register to inspect the privilege level that
        the hart was running in when the hart halted.
        User can write this register to change the privilege level that
        the hart will run in when it resumes.

        This register contains \Fprv from \Rdcsr, but in a place that the user
        is expected to access. The user should not access \Rdcsr directly,
        because doing so might interfere with the debugger.

        \begin{table}
        \centering
        \caption{Privilege Level Encoding}
        \label{tab:privlevel}
        \begin{tabular}{|r|l|}
        \hline
        Encoding &amp; Privilege Level \\
        \hline
        0 &amp; User/Application \\
        1 &amp; Supervisor \\
        3 &amp; Machine \\
        \hline
        \end{tabular}
        \end{table}

        <field name="prv" bits="1:0" access="R/W" reset="0">
            Contains the privilege level the hart was operating in when Debug
            Mode was entered. The encoding is described in Table
            \ref{tab:privlevel}, and matches the privilege level encoding from
            the RISC-V Privileged ISA Specification. A user can write this
            value to change the hart's privilege level when exiting Debug Mode.
        </field>
    </register>
</registers>
