- Feb 19, 2020
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Anup Patel authored
The MIDELEG and MEDELEG CSR checks at end of delegate_traps() were added for initial bring-up on SiFive Unleashed and QEMU. These checks are not required any more and in-future these checks can cause failures because some of the MIDELEG/MEDELEG bits will be hard-wired to 0 or 1. For related discussion, refer github issue: https://github.com/riscv/opensbi/issues/157 Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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- Feb 18, 2020
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Bin Meng authored
When building 32-bit OpenSBI images, we get: lib/utils/sys/htif.c: In function '__check_fromhost': lib/utils/sys/htif.c:12:31: error: left shift count >= width of type [-Werror=shift-count-overflow] #define HTIF_DATA_MASK ((1UL << HTIF_DATA_BITS) - 1) ^~ Fixes: c2f23cc6 ("platform: Add Spike initial support") Signed-off-by:Bin Meng <bmeng.cn@gmail.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
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Anup Patel authored
This reverts commit 897b8fbd . We are seeing compile errors using newlib based GCC cross-toolchain so we restore back old ctz() implementation. Signed-off-by:
Anup Patel <anup.patel@wdc.com>
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Bin Meng authored
- make title underline the same length as the title itself - satisfy the 80 character per line rule as much as possible Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
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Bin Meng authored
- make title underline the same length as the title itself - put all URLs at the end of the doc Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
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Bin Meng authored
Remove the unnecessary blank line at the end of the doc. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
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Bin Meng authored
Various styles fixes including: - satisfy the 80 character per line rule as much as possible - make title underline the same length as the title itself - remove the redundant FPGA (was FPGA FPGA SoC) Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
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Bin Meng authored
Various styles fixes including: - satisfy the 80 character per line rule as much as possible - remove unnecessary spaces between words Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
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Bin Meng authored
Remove the unnecessary blank line at the end of the doc. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
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Bin Meng authored
- put all URLs at the end of the doc - satisfy the 80 character per line rule as much as possible Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
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Bin Meng authored
Remove the unnecessary blank line at the end of the doc. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
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- Feb 17, 2020
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Anup Patel authored
This patch adds documentation to build and run OpenSBI on Spike simulator and QEMU Spike machine. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
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Anup Patel authored
The Spike platform support works perfectly fine on QEMU RV64 Spike machine and Spike emulator. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
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Anup Patel authored
This patch removes stale options from config.mk files of Ariane FPGA and QEMU virt platform support. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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James Clarke authored
This patch adds initial platform support Spike emulator. Signed-off-by:
James Clarke <jrtc27@jrtc27.com> Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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- Feb 13, 2020
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Atish Patra authored
To initialize PLIC in sane state, we should: 1. set maximum threshold value of M-mode PLIC contexts 2. set maximum threshold value of S-mode PLIC contexts 3. set irq priorities to miniumum Fix the comment and initialize the threshold/priorities correctly. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Signed-off-by:
Atish Patra <atish.patra@wdc.com>
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Atish Patra authored
As per the SBI specification, the return value in sbiret is undefined if not explicitly described in the function. However, supervisor may check this value by mistake and get a garbage value. Initialize it to zero to avoid nasty supervisor bugs. Signed-off-by:
Atish Patra <atish.patra@wdc.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
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Li Jinpei authored
We should should __builtin_ctzl() in pmp_get() instead of custom ctz() function. Signed-off-by:
Li Jinpei <leekingp1994@163.com> Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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Li Jinpei authored
Instead of using loop to make "size" machine word aligned, we should use bitwise ops. Signed-off-by:
Li Jinpei <leekingp1994@163.com> Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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- Feb 11, 2020
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Bin Meng authored
Document that when U-Boot v2020.01 (or higher) is used as the payload, we need adjust the instructions a little bit when testing OpenSBI with QEMU 'sifive_u' machine. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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- Feb 07, 2020
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Bin Meng authored
This adds sifive/fu540 specific QEMU run command. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
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Bin Meng authored
With QEMU v4.2 RISC-V changes to improve the emulation fidelity of 'sifive_u' machine, OpenSBI v0.4 / U-Boot v2019.10 / Linux kernel v5.3 images built for the SiFive HiFive Unleashed board can be used out of the box without any special hack. Hence there is no need for us to continue supporting such a special target in OpenSBI. Going forward, sifive/fu540 platform can be used on both real hardware and QEMU 'sifive_u' machine. Signed-off-by:
Bin Meng <bmeng.cn@gmail.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
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- Feb 06, 2020
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Alex Richardson authored
On macOS the readlink command does not include a -f flag. Instead default to using GNU readlink (which is often installed as greadlink). Signed-off-by:
Alex Richardson <Alexander.Richardson@cl.cam.ac.uk> Signed-off-by:
Anup Patel <anup.patel@wdc.com>
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- Feb 05, 2020
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Atish Patra authored
It was reported that tlb range flush is not working on fu540. Only tlb full flush seems to work on fu540 probably due to some hardware errata. Set the tlb flush limit to zero so that all tlb flush requests are converted to full flush. Signed-off-by:
Atish Patra <atish.patra@wdc.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
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Atish Patra authored
If a platform requires to perform a tlb full flush, they should set the tlb_range_flush_limit value to zero. However, corresponding platform API ignore the value and continue to return the default value. Add a platform ops to retrieve platform specific tlb range flush limit. The platform variable becomes redundant in presence of the platform ops. Take this opportunity to remove the variable as well. The default is still set to smallest page size in RISC-V (4KB), as there is no way to figure out a best value for all platforms. Individual platform should set it to the optimal value for their platform. Signed-off-by:
Atish Patra <atish.patra@wdc.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
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- Jan 25, 2020
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Nikita Ermakov authored
In the QEMU [1] there was a change of the UART base addresses for sifive_u machine to match the hardware. Make corresponding changes in the opensbi for qemu/sifive_u platform. [1] https://git.qemu.org/?p=qemu.git;a=commitdiff;h=4b55bc2b5f7ff065da5d2b813ee5153c598d3764 Signed-off-by:
Nikita Ermakov <coffe92@gmail.com> Reviewed-by:
Anup Patel <anup.patel@wdc.com>
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- Jan 24, 2020
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Jiuyang Liu (Sequencer) authored
This patch does minor typo fix in system reboot/shutdown names in platform operations. Signed-off-by:
Jiuyang Liu (Sequencer) <liujiuyang1994@gmail.com> Reviewed-by:
Alistair Francis <alistair.francis@wdc.com> Signed-off-by:
Anup Patel <anup.patel@wdc.com>
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- Jan 22, 2020
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Anup Patel authored
This patch factor-out SBI base extension into its own source for better modularity of SBI implementation. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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Anup Patel authored
This patch factor-out SBI vendor extension into its own source for better modularity of SBI implementation. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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Anup Patel authored
This patch factor-out SBI replacement extensions (such as RFENCE, IPI, and TIME) into its own source for better modularity of SBI implementation. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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Anup Patel authored
This patch factor-out SBI legacy extension into its own source for better modularity of SBI implementation. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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Anup Patel authored
This patch extends our SBI ecall implementation to allow dynamic registration of various SBI extensions. Using this dynamic registration we can break-up SBI ecall implementation into multiple files and even register experimental/custom SBI extensions from platform code. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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Anup Patel authored
This patch adds generic and simple list handling APIs adapted from Xvisor sources. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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Anup Patel authored
Currently, the remote TLB management is initialized via IPI init which is counter intuitive. This patch initializes remote TLB management directly from init_coldboot() and init_warmboot() after IPI init is done. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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Anup Patel authored
This patch drops _fifo from the name of various sbi_tlb_fifo_xyz() functions because all these functions deal with remote TLB managment and FIFO is the per-HART data structure used internally by remote TLB implementation. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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Anup Patel authored
This patch introduces sbi_ipi_event_create/destroy() APIs and struct sbi_ipi_event_ops for creating/destroying IPI events at runtime based of event operations. This new APIs will help platform code and utils code to create custom IPI events which are not part of generic OpenSBI library. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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Anup Patel authored
Instead of directly calling sbi_ipi_send_many(), we introduce sbi_tlb_fifo_request() for halting a set of HARTs. This way in future we can assign any IPI event number for remote FENCE within sbi_tlb.c only. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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Anup Patel authored
Instead of directly calling sbi_ipi_send_many(), we introduce sbi_ipi_send_halt() for halting a set of HARTs. This way in future we can assign any IPI event number for HART halting within sbi_ipi.c only. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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Anup Patel authored
Instead of directly calling sbi_ipi_send_many(), we introduce sbi_ipi_send_smode() for injecting S-mode software interrupts. This way in future we can assign any IPI event number for S-mode IPIs within sbi_ipi.c only. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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Anup Patel authored
The struct sbi_ipi_data is only used in sbi_ipi.c so move it to sbi_ipi.c from sbi_ipi.h. Signed-off-by:
Anup Patel <anup.patel@wdc.com> Reviewed-by:
Atish Patra <atish.patra@wdc.com>
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