This patch expands `G_{U|S}DIVREM` into `G_{U|S}DIV + G_{U|S}REM`.
`G_{U|S}DIVREM` is generated by the following fold:

https://github.com/llvm/llvm-project/blob/4ea21a0261cd8599a9ffa15f5c554ab0d4bbbe27/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp#L1410-L1471

It always folds `div + rem` pairs into `divrem` during pre-legalization.
I tried to change `isLegalOrBeforeLegalizer` to `isLegal`, but it
produced worse codegen on AArch64.

We were still matching the expected diagnostic, but this ensures we
match the opening quotation mark as well.

This patch fixes:

  lldb/source/Plugins/ABI/PowerPC/ABISysV_ppc64.cpp:839:7: error:
  ignoring return value of function declared with 'nodiscard'
  attribute [-Werror,-Wunused-result]

Re-enables the single, symbol and threadprivate tests

For distributed ThinLTO, the LTO indexing step generates combined
summary for each module, and postlink pipeline reads the combined
summary which stores the information for link-time optimization.

This patch populates the 'import type' of a summary in bitcode, and
updates bitcode reader to parse the bit correctly.

This upstreams more recent, mostly EH changes from libcxx and libcxxabi:
- `__cxa_init_primary_exception`-related changes made when updating to
LLVM 18.1.2 (https://github.com/emscripten-core/emscripten/pull/21638)
- Removes ctype macros
(https://github.com/emscripten-core/emscripten/pull/20960)
- Guard destructor changes with `__wasm__`
(https://github.com/emscripten-core/emscripten/pull/21974)

Adding a release note about this as discussed in #92439. 

---------

Co-authored-by: cor3ntin <corentinjabot@gmail.com>

Drop unimplemented solveMCF and remnants of it.

Remove calls to std::unordered_map::at, std::map::at, and
std::vector::at.

Unbreak shared build after
https://github.com/llvm/llvm-project/pull/91683

Extends `tensor.empty` folding patterns with pack and unpack consumers
to fold away the operations when their source is empty.

Summary:
CUDA does its versioning by putting a redirection in the header so the
API functions remain the same while the symbol changes. These weren't
being used for some functions that required it in the dynamic cuda
version.

These functions have newer verisons that should be used. These are
fairly old as far as I'm aware so we should be able to sweep backward
compatibility under the rug.

This is a followup to #81014 and #84582: Before this patch, Clang 
would accept `__attribute__((assume))` and `[[clang::assume]]` as 
nonstandard spellings for the `[[omp::assume]]` attribute; this 
resulted in a potentially very confusing name clash with C++23’s 
`[[assume]]` attribute (and GCC’s `assume` attribute with the same
semantics).

This pr replaces every usage of `__attribute__((assume))`  with 
`[[omp::assume]]` and makes `__attribute__((assume))` and 
`[[clang::assume]]` alternative spellings for C++23’s `[[assume]]`; 
this shouldn’t cause any problems due to differences in appertainment
and because almost no-one was using this variant spelling to begin
with (a use in libclc has already been changed to use a different
attribute).

This change is a general improvement of the internal API. My motivation
is to use this in the Swift typesystem plugin.

`SelectCaseOp::getCompareOperands` may return an empty range for the
"default" case. Do not dereference the range until it is expected to be
non-empty.

This was detected by address-sanitizer.

This pass is module-level and then runs on all operations implementing
the ordered assignment interface. It should not matter which top-level
operation the assignment is inside of.

This commit removes some unnecessary boilerplate that we can generate
automatically with tablegen.

Fixes #71161

[D64087](https://reviews.llvm.org/D64087

) updated some locations of the
instantiated method but forgot `DNLoc`.

`FunctionDecl::getNameInfo()` constructs a `DeclarationNameInfo` using
`Decl::Loc` as the beginning of the declaration name, and
`FunctionDecl::DNLoc` to compute the end of the declaration name. The
former was updated, but the latter was not, so
`DeclarationName::getSourceRange()` would return a range where the end
of the declaration name could come before its beginning.

Patch by Alejandro Alvarez Ayllon
Co-authored-by: steakhal

CPP-5166

Co-authored-by: Alejandro Alvarez Ayllon <alejandro.alvarez@sonarsource.com>

This patch widens the illegal shamt type `i48` -> `i64` to fix
legalization failure: https://godbolt.org/z/4zMTnoW7h

Fixes an error that llc fails to legalize `G_CONSTANT_FOLD_BARRIER` with
i16/i128: https://godbolt.org/z/f9n6xM3sv

There's currently no way to control whether a null terminator should be
appended to the string created in `CreateGlobalString` /
`CreateGlobalStringPtr`, since the methods don't expose an additional
argument.
This change adds an additional argument to the methods that has the same
default value, `true`, as in `ConstantDataArray::getString`, and passes
it down to this internal method.

This is an enabler for https://github.com/llvm/llvm-project/pull/92855

This allows an NTTP default argument to be set as an arbitrary
TemplateArgument, not just an expression.
This allows template parameter packs to have default arguments in the
AST, even though the language proper doesn't support the syntax for it.

This allows NTTP default arguments to be other kinds of arguments, like
packs, integral constants, and such.

Need to check if the loads node is masked gather. Only vectorized loads
can be converted to strided.

I noticed this was possibly buggy with implicit operands with the same
dest register, and should maybe be using addRegisterDead. However, this
is never called in a situation where the operand wasn't already marked
dead. This is eliminateDeadDef, implying the def was already known to be
dead.

Add an assert to detect inconsistencies in dead flags. This was
apparently added in 9a16d655.

This was breaking the CFG connection between uses of virtual registers
after the trap and their definitions before it. Fixes SWDEV-460384.

Fixes a bug in #85854.

The option pairs include:
	-mfpxx -mips1
	-msoft-float -mmsa
	-mmsa -mabi=32 with 32bit pre-R2 CPUs
	-mfpxx -mmsa
	-mfp32 -mmsa

to avoid circular dependency introduced in
a9b67490

If the RHS is a constant with X trailing zeros, then the X MSBs of the
LHS are not demanded.

Alive2: https://alive2.llvm.org/ce/z/F5CyJW
Fixes https://github.com/llvm/llvm-project/issues/56645.

Since #87009, libomptarget directly links all the plugins statically.
All the dependencies of plugins got exposed to libomptarget. The CUDA
plugin depends on libcuda and the amdgpu plugin depends on libhsa if not
forced using dlopen. On a cluster with different compute node
architectures, libomptarget can be built and run on different nodes. In
the build stage, if cmake founds libcuda and
`LIBOMPTARGET_FORCE_DLOPEN_LIBCUDA=OFF`, libomptarget links libcuda.so
directly and the result libomptarget may not run a node without a NVIDIA
driver for example a CPU or AMD GPU only machine with a complaint that
libcuda.so not found.

The solution is setting `LIBOMPTARGET_FORCE_DLOPEN_LIBCUDA` and
`LIBOMPTARGET_FORCE_DLOPEN_LIBHSA` `ON`. Preferably this should be
default to maximize the usability of libomptarget. If cmake detects
NVIDIA or AMD software on an OS imaging building node, the resulted
libomptarget may not be able to function on the user side due to the
requirement the existence of vendor runtime libraries.

Report an error if a required value for a command line argument is
missing.

This commit adds conversion to EmitC for arith dialect casts between integer types (trunc, extsi, extui), excluding indexes for now.

This patch overrides the clearsSuperRegisters method defined in
MCInstrAnalysis to identify register writes that clear the upper portion
of all super-registers on AArch64 architecture.

On AArch64, a write to a general-purpose register of 32-bit data size is
defined to use the lower 32-bits of the register and zero extend the
upper 32-bits.
Similarly, SIMD and FP instructions operating on scalar data only access
the lower bits of the SIMD&FP register. The unused upper bits are
cleared to zero on a write.
This also applies to SIMD vector registers when the element size in bits
multiplied by the number of lanes is lower than 128. The upper 64 bits
of the vector register are cleared to zero on a write.

This resolves an older FIXME comment.