Scalar FMUL, FMULX instructions perform better or the same compared to indexed
FMUL, FMULX.

For example, the Arm Cortex-A55 Software Optimization Guide lists the following
instructions with a throughput of 2 IPC:
 - "FP multiply" FMUL
 - "ASIMD FP multiply" FMULX

whereas it lists the following with a throughput of 1 IPC:
 - "ASIMD FP multiply, by element" FMUL, FMULX

The Arm Cortex-A510 Software Optimization Guide, however, does not separately
list "by element" variants of the "ASIMD FP multiply" instructions, which are
listed with the same throughput as the non-ASIMD ones.

Fixes #60817.

Differential Revision: https://reviews.llvm.org/D153207

When the analysis of hlfir.region_assign determined that the LHS region
evaluation may be impacted by the assignment effects, all LHS must be
fully evaluated and saved before any assignment is done.

This patch adds TemporaryStorage variants to save address, including
vector subscripted entities addresses whose shape must be saved.
It uses the DescriptorStack runtime to deal with complex cases inside
forall. For the sake of simplicity, this is also used for vector
subscripted LHS outside of foralls (each element address is saved as
a descriptor on this stack. This is a bit suboptimal, but it is a safe
start that will work with all kinds of type (polymorphic, PDTs...)
without further work). Another approach would be to saved only the
values that are conflicting in the LHS computation, but this would
require a much more complex analysis of the LHS region DAG.

Differential Revision: https://reviews.llvm.org/D154057

Differential Revision: https://reviews.llvm.org/D153652

Similar to AffineMap and IntegerSet parsing, this change makes the more fine-grained AffineExpr available for general parsing, using a preset symbol set to recognize variables.

Motivation:
The AffineExpr parser will be used by the new sparse tensor encoding surface syntax. Originally, we planned to duplicate the affine parser completely, but that would be a terrible waste of a good thing. With this minor API change, we prepare the way for the sparse tensor dialect (and others) to reuse the AffineExpr parser outside the context of a more restricted AffineMap parser.

Reviewed By: Peiming

Differential Revision: https://reviews.llvm.org/D154177

Previously, we would try to transform cmpinst in
simplifyTerminatorLeadingToRet if we found it was a constant. However,
this is incorrect.

Since the resolved constants in simplifyTerminatorLeadingToRet are not
truely constants. They are basically constants along cerntain code
paths.

In this way, it is clearly incorrect to transform the compare
instruction to a constant.

It will cause confusing miscompilations. This patch tries to fix this.

Differential Revision: https://reviews.llvm.org/D154114

At some point we alloed the CGSCC traversal to look at the entire module
slice (see definition below). However, we don't allow that anymore,
mostly for compile time and complexity reasons. Consequently, there is
no need to build the ModuleSlice as we can replacve it with the SCC
wherever it was still used.

If the IR has a boolean attribute, or the function is not IPO amendable,
we can avoid creating AAs that would just be forced into a trivial
fixpoint anyway. Since we check boolean IR attributes via
`AA::hasAssumedIRAttr`, we don't need AAs even if they would be fixed
optimistic right away. The only change is in the dependency graph
ordering as we move AAs around to simplify the code flow. There is no
reason for the order we seed AAs, so this order is just as fine.

Reviewed By: #bolt, rafauler

Differential Revision: https://reviews.llvm.org/D154115

Explicitly inserting undef is overly defensive. Any values computed
nside the loop that are referenced by dbg.values should naturally
become undef when the loop is deleted, and all other values that
are loop invariant must be preserved.

Reviewed By: scott.linder

Differential Revision: https://reviews.llvm.org/D153539

The missing info is gathered from X86.td.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D154181

This reverts commit f0b45fba.

The stack broke https://lab.llvm.org/buildbot/#/builders/252.

This reverts commit 8f7c53ef.

The stack broke https://lab.llvm.org/buildbot/#/builders/252.

This revision fixes a typo, where printIntegerSet() was used where it should have been parseIntegerSet().It also removes a dangling getDimsAndSymbolSSAIds() declaration that is never used.

Differential Revision: https://reviews.llvm.org/D154179

This reverts commit fcd58ea5.

Causes crashes, see comments on D154114.

Previously when targeting 68020+, instruction selection attempted to
emit a 32-bit register-register multiplication, but failed at instruction
selection. With this, it succeeds.

Differential Revision: https://reviews.llvm.org/D152120

This reverts commit a699921b.

Seems to cause miscompiles (https://crbug.com/1459232), following up with author.

These extensions don't contain any instructions on their own, they
are just aliases for a set of extensions. We should set the preprocessor
define anytime all the sub-extensions are supported.

Reviewed By: kito-cheng, eopXD

Differential Revision: https://reviews.llvm.org/D154171

Reviewed By: zixuan-wu

Differential Revision: https://reviews.llvm.org/D153326

Remove kind=10 test variant, which is not universally supported.

[LoongArch] Reuse LoongArchRegWithSubRegs class to shorten some code in LoongArchRegisterInfo.td. NFC

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D153940

Make sure there is no single line for '{' to be consistent with
other codes.

`InvalidIndex` is removed since it's unused now. And comments are
updated.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D153939

This reverts commit 02c3724d.

This change breaks instrumented Clang:
https://lab.llvm.org/buildbot/#/builders/252/builds/2700

This reverts commit ad4e0770.
Breaks BOLT upstream testing:
https://lab.llvm.org/buildbot/#/builders/244/builds/13736

the list of generic registers is meant to include
LLDB_REGNUM_GENERIC_FLAGS but it copy & pasted the
name "fp".

rdar://100857252

The bots reported that we changed the IR w/o reporting it. The reason
was that internalization was not reported as changed. Forwarding the
result solves the problem.

Test coverage via
llvm/test/Transforms/Attributor/reduced/openmp_opt_constant_type_crash.ll

Commit d6223a24 introduced an ld64 workaround
that disables local relocations for many pointer-sized relocations (e.g.
relocations referencing `__DATA,__literal*`).

ld64 has been fixed long ago (2015). Drop this workaround so that the
behavior matches x86-64.

Reviewed By: pete

Differential Revision: https://reviews.llvm.org/D152831

ObjectFileMachO::SetLoadAddress() should allow for a DATA segment
that has no file content to be slid in the vmaddr, it is valid
to have such a section.

Differential Revision: https://reviews.llvm.org/D154037
rdar://99744343

Differential Revision: https://reviews.llvm.org/D152339

Reviewed By: qiucf

[PowerPC][NFC] expose issue on absol-jump-table-enabled.ll (relocation-model=pic + ppc-use-absolute-jumptables)

Differential Revision: https://reviews.llvm.org/D154047

Differential Revision: https://reviews.llvm.org/D154114

A command to dump the Target's SectionLoadList, to debug
possible issues with the table.

Differential Revision: https://reviews.llvm.org/D154169