A caveat here is that we can only preserve nusw if the offset
additions did not overflow.

Proofs: https://alive2.llvm.org/ce/z/u56z_u

[clang-tidy] fix false positives for the functions with the same name as standard library functions in misc-include-cleaner (#94923)

Fixes: #93335
For decl with body, we should provide physical locations also. Because
it may be the function which have the same name as std library.

The main goal of this PR (and subsequent PRs), is to add more tests with
scalable vectors to:
  * vector-transfer-collapse-inner-most-dims.mlir

There's quite a few cases to consider, hence this is split into multiple
PRs. In this PR, the very first test is complemented with all the
possible combinations:
  * scalable (rather than fixed) unit trailing dim,
  * dynamic (rather than static) trailing dim in the source memref.

Also,
  * `@leading_scalable_dimension_transfer_read` and
    `@trailing_scalable_one_dim_transfer_read`,

are replaced with:
  * `@contiguous_inner_most_scalable_inner_dim` and
    `@negative_scalable_unit_dim`,

respectively, and added to the list above (i.e. alongside other
variations for the very first test).

In addition:
  * "_view" is removed from function names (it's not clear to me what it
    was meant to signify)
  * extra comments are added to separate tests for vector.transfer_read
    and vector.transfer_write

NOTE: This PR is limited to tests for `vector.transfer_read`.

Following from the previous commit, this patch converts to the
appropriate debug info format before printing LLVM IR.

See: https://github.com/llvm/llvm-project/pull/95098

Reapplies the original patch with some additional conversion layers added
to the MLIR translator, to ensure that we don't write the new debug info
format unless WriteNewDbgInfoFormat is set.

This reverts commit 8c5d9c79.

Some cases should be legal for gfx940.

Add a section about fence & address spaces that covers amdgpu-as.

Reverted due to failure on buildbot due to missing use of the
WriteNewDbgInfoFormat flag in MLIR.

This reverts commit ca920bb6.

This PR is required to fix
`std/algorithms/alg.nonmodifying/mismatch/mismatch.pass.cpp` test for
big endian platrofrms such as z/OS.

Those BitVectors get expensive on targets like AMDGPU with thousands of
registers, and RegAliasIterator is also expensive.

We can move all liveness calculations to use RegUnits instead to speed
it up for targets where RegAliasIterator is expensive, like AMDGPU.
On targets where RegAliasIterator is cheap, this alternative can be a little more expensive, but I believe the tradeoff is worth it.

This commit reimplements the functionality of the Clang Static Analyzer
checker `alpha.core.SizeofPointer` within clang-tidy by adding a new
(off-by-default) option to bugprone-sizeof-expression which activates
reporting all the `sizeof(ptr)` expressions (where ptr is an expression
that produces a pointer).

The main motivation for this change is that `alpha.core.SizeofPointer`
was an AST-based checker, which did not rely on the path sensitive
capabilities of the Static Analyzer, so there was no reason to keep it
in the Static Analyzer instead of the more lightweight clang-tidy.

After this commit I'm planning to create a separate commit that deletes
`alpha.core.SizeofPointer` from Clang Static Analyzer.

It was natural to place this moved logic in bugprone-sizeof-expression,
because that check already provided several heuristics that reported
various especially suspicious classes of `sizeof(ptr)` expressions.

The new mode `WarnOnSizeOfPointer` is off-by-default, so it won't
surprise the existing users; but it can provide a more through coverage
for the vulnerability CWE-467 ("Use of sizeof() on a Pointer Type") than
the existing partial heuristics.

Previously this checker had an exception that the RHS of a
`sizeof(array) / sizeof(array[0])` expression is not reported; I
generalized this to an exception that the check doesn't report
`sizeof(expr[0])` and `sizeof(*expr)`. This idea is taken from the
Static Analyzer checker `alpha.core.SizeofPointer` (which had an
exception for `*expr`), but analysis of open source projects confirmed
that this indeed eliminates lots of unwanted results.

Note that the suppression of `sizeof(expr[0])` and `sizeof(*expr)`
reports also affects the "old" mode `WarnOnSizeOfPointerToAggregate`
which is enabled by default.

This commit also replaces the old message "suspicious usage of
'sizeof(A*)'; pointer to aggregate" with two more concrete messages; but
I feel that this tidy check would deserve a through cleanup of all the
diagnostic messages that it can produce. (I added a FIXME to mark one
outright misleading message.)

MLIR's LLVM dialect does not internally support debug records, only
converting to/from debug intrinsics. To smooth the transition from
intrinsics to records, there is a step prior to IR->MLIR translation
that switches the IR module to intrinsic-form; this patch adds the
equivalent conversion to record-form at MLIR->IR translation, and also
modifies the flang front end to use the WriteNewDbgInfoFormat flag when
it is emitting LLVM IR.

The case-list of the switches generated by this pass were not
"deterministic" (based on allocation patterns).
This is because the CaseList order relied on an unordered_set order.
Using the sorted exit target list for those should solve the problem.

Fixes #94961

Signed-off-by: Nathan Gauër <brioche@google.com>

There were four tests in Driver that actually tested bits of Driver and
bits of CodeGen, and therefore had target restrictions. Rework those
four tests into one Driver test (with no target restrictions) and two
target-specific CodeGen tests.

The current logic tests for inf/inf and 0/0 inputs using a NaN check.
This doesn't work with all fastmath flags. With nnan and ninf, we can
just check for a 0 maximum. With only nnan, we have to check for both
cases separately.

Function `getNeutralElement` already indicates "cannot find neutral
element" by returning nullptr through the return value, and no
additional error log needs to be output.

"[Flang] Update test to not check for tail calls on debug intrinsics" &
"Reapply#3 "[RemoveDIs] Load into new debug info format by default in LLVM (#89799)"

Recent updates to flang have added debug info generation via MLIR, a path
which currently does not support debug records. The patch that enables
debug records by default (and a small followup patch) are thus being
reverted until the MLIR path has been fixed.

This reverts commits:
  21396be8
  c5aeca73

Copying an MCInst isn't cheap (copies all operands) and the whole
instruction is only used for the Intel erratum mitigation, which is off
by default. In all other cases, the opcode alone suffices.

This slightly pessimizes code that uses moves to segment registers --
but that's uncommon and not performance-sensitive anyway.

As a related change, also call canPadInst() only when the result is
actually used, which is typically only the case in emitInstrEnd.

This gives a minor performance improvement.

This allows tested passes to depend on the AMX model in the function
info. Preparatory work for to adopt #94358 for other AMX passes.

Follow up of #94887.

Context:
https://github.com/llvm/llvm-project/pull/94887#pullrequestreview-2106213891

This was previously set to 4uops which was including the cost of extra register moves in the original test code.

This addresses a review comment for PR #94987 Because that PR is a big
automatic change, this change was moved in a separate one.

This is still not perfect, but an improvement in general.

Use DEFINE: %{res} = ... instead of $(cat ...). Rewrite one use of a
subshell to write to a temporary file instead.

Fixes #95036 #95033 #94933 #94930

This matches the other two functions AddOverflow and SubOverflow.

This was pointed out in PR #93940.

This patch adds APFloat type support for two FP6 data types,
E2M3 and E3M2. The definitions for the two formats are detailed
in section 5.3.2 of the OCP specification, which can be accessed here:

https://www.opencompute.org/documents/ocp-microscaling-formats-mx-v1-0-spec-final-pdf



Signed-off-by: Durgadoss R <durgadossr@nvidia.com>

Without this gcc (9.3.0) warns with
 ../lib/Target/AArch64/GISel/AArch64CallLowering.cpp: In function 'unsigned int getCallOpcode(const llvm::MachineFunction&, bool, bool, std::optional<llvm::CallLowering::PtrAuthInfo>&, llvm::MachineRegisterInfo&)':
 ../lib/Target/AArch64/GISel/AArch64CallLowering.cpp:1025: warning: enumeral and non-enumeral type in conditional expression [-Wextra]
  1025 |       return IsIndirect ? getBLRCallOpcode(CallerF) : AArch64::BL;
       |

This commit adds a test for lea_rsp_pattern_p which was previously due
as FIXME.

This PR generates dwarf to extract the information about the arrays from
descriptor. The DWARF needs the offset of the fields like `lower_bound`
and `extent`. The getComponentOffset has been added to calculate
them which pushes the issue of host and target data size into
getDescFieldTypeModel.

As we use data layout now, some tests needed to be adjusted to have a
dummy data layout to avoid failure.

With this change in place, GDB is able show the assumed shape arrays
correctly.

  subroutine ff(n, m, arr)
    integer n, m
    integer :: arr(:, :)
    print *, arr
    do i = 1, n
      do j = 1, m
        arr(j, i) = (i * 5) + j + 10
      end do
    end do
    print *, arr
  end subroutine ff

Breakpoint 1, ff (n=4, m=3, arr=...) at test1.f90:13
13          print *, arr
(gdb) p arr
$1 = ((6, 7, 8, 9) (11, 12, 13, 14) (16, 17, 18, 19))
(gdb) ptype arr
type = integer (4,3)
(gdb) c
Continuing.
 6 7 8 9 11 12 13 14 16 17 18 19

The pass pipeline of some architecture splits register allocation phase
based on different register classes. As some analyses need to be
computed at the beginning of the register allocation and kept alive till
all values are assigned to some physical registers.

This poses challenge with objective of introducing StackSlotColoring
after partial virtual registers are assigned to physical registers, in
order to optimize stack slots usage.As this pass doesn't preserve few
analysis yet to be needed by the register allocation of the remaining
virtual registers, necessiating them to be kept preserved.

The patch includes a repro for a case where we were returning a null
`FieldDecl`
when calling `getReferencedDecls()` on the `InitListExpr` for a union.

Also, I noticed while working on this that `RecordInitListHelper` has a
bug
where it doesn't work correctly for empty unions. This patch also
includes a
repro and fix for this bug.