This PR updates removeFnAttrFromReachable in AMDGPUMemoryUtils to accept
array of function attributes as argument.
Helps to remove multiple attributes in one CallGraph walk.

LD_LIBRARY_PATH will become invalid when LIBPATH is also set on AIX.

See below example on AIX:
```
$ldd a.out
a.out needs:
	 /usr/lib/libc.a(shr.o)
Cannot find libtest.a
	 /unix
	 /usr/lib/libcrypt.a(shr.o)

$./a.out
Could not load program ./a.out:
	Dependent module libtest.a could not be loaded.
Could not load module libtest.a.
System error: No such file or directory

$export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:/tmp
$./a.out ; echo $?
10

$export LIBPATH=./
$./a.out ; echo $?  >>>>>> Now LD_LIBRARY_PATH is not used by system loader
Could not load program ./a.out:
	Dependent module libtest.a could not be loaded.
Could not load module libtest.a.
System error: No such file or directory
```

This breaks many AIX LIT cases on our downstream buildbots which sets
LIBPATH.

---------

Co-authored-by: Anh Tuyen Tran <34661776+anhtuyenibm@users.noreply.github.com>
Co-authored-by: David Tenty <daltenty.dev@gmail.com>

This is similar to what the current interpreter does.

When trying to add a file to clang's VFS via `addFile` and a directory
of the same name already exists, we run into a [out-of-bound
access](https://github.com/llvm/llvm-project/blob/145815c180fc82c5a55bf568d01d98d250490a55/llvm/lib/Support/Path.cpp#L244).

The problem is that the file name is [recognised as existing path](
https://github.com/llvm/llvm-project/blob/145815c180fc82c5a55bf568d01d98d250490a55/llvm/lib/Support/VirtualFileSystem.cpp#L896)
and thus continues to process the next part of the path which doesn't
exist.

This patch adds a check if we have reached the last part of the filename
and return false in that case.
This we reject to add a file if a directory of the same name already
exists.

This is in sync with [this
check](https://github.com/llvm/llvm-project/blob/145815c180fc82c5a55bf568d01d98d250490a55/llvm/lib/Support/VirtualFileSystem.cpp#L903)
that rejects adding a path if a file of the same name already exists.

058e4454 added an XFAIL for this test on AIX because of a backend
limitation. That backend limitation
has been resolved by 0295c2ad and will be available for clang 19, so we
should update the test to
limit the XFAIL to clang versions before that.

This trims off 8 bytes from llvm::SUnit:
```
--- before	2024-06-05 12:13:00
+++ after	2024-06-05 12:12:58
@@ -1,65 +1,65 @@
 *** Dumping AST Record Layout
          0 | class llvm::SUnit
          0 |   SDNode * Node
          8 |   MachineInstr * Instr
         16 |   SUnit * OrigNode
         24 |   const MCSchedClassDesc * SchedClass
         32 |   class llvm::SmallVector<class llvm::SDep, 4> Preds
         32 |     class llvm::SmallVectorImpl<class llvm::SDep> (base)
         32 |       class llvm::SmallVectorTemplateBase<class llvm::SDep> (base)
         32 |         class llvm::SmallVectorTemplateCommon<class llvm::SDep> (base)
         32 |           class llvm::SmallVectorBase<uint32_t> (base)
         32 |             void * BeginX
         40 |             unsigned int Size
         44 |             unsigned int Capacity
         48 |     struct llvm::SmallVectorStorage<class llvm::SDep, 4> (base)
         48 |       char[64] InlineElts
        112 |   class llvm::SmallVector<class llvm::SDep, 4> Succs
        112 |     class llvm::SmallVectorImpl<class llvm::SDep> (base)
        112 |       class llvm::SmallVectorTemplateBase<class llvm::SDep> (base)
        112 |         class llvm::SmallVectorTemplateCommon<class llvm::SDep> (base)
        112 |           class llvm::SmallVectorBase<uint32_t> (base)
        112 |             void * BeginX
        120 |             unsigned int Size
        124 |             unsigned int Capacity
        128 |     struct llvm::SmallVectorStorage<class llvm::SDep, 4> (base)
        128 |       char[64] InlineElts
        192 |   unsigned int NodeNum
        196 |   unsigned int NodeQueueId
        200 |   unsigned int NumPreds
        204 |   unsigned int NumSuccs
        208 |   unsigned int NumPredsLeft
        212 |   unsigned int NumSuccsLeft
        216 |   unsigned int WeakPredsLeft
        220 |   unsigned int WeakSuccsLeft
        224 |   unsigned short NumRegDefsLeft
        226 |   unsigned short Latency
    228:0-0 |   _Bool isVRegCycle
    228:1-1 |   _Bool isCall
    228:2-2 |   _Bool isCallOp
    228:3-3 |   _Bool isTwoAddress
    228:4-4 |   _Bool isCommutable
    228:5-5 |   _Bool hasPhysRegUses
    228:6-6 |   _Bool hasPhysRegDefs
    228:7-7 |   _Bool hasPhysRegClobbers
    229:0-0 |   _Bool isPending
    229:1-1 |   _Bool isAvailable
    229:2-2 |   _Bool isScheduled
    229:3-3 |   _Bool isScheduleHigh
    229:4-4 |   _Bool isScheduleLow
    229:5-5 |   _Bool isCloned
    229:6-6 |   _Bool isUnbuffered
    229:7-7 |   _Bool hasReservedResource
-       232 |   Sched::Preference SchedulingPref
-   236:0-0 |   _Bool isDepthCurrent
-   236:1-1 |   _Bool isHeightCurrent
-       240 |   unsigned int Depth
-       244 |   unsigned int Height
-       248 |   unsigned int TopReadyCycle
-       252 |   unsigned int BotReadyCycle
-       256 |   const TargetRegisterClass * CopyDstRC
-       264 |   const TargetRegisterClass * CopySrcRC
-           | [sizeof=272, dsize=272, align=8,
-           |  nvsize=272, nvalign=8]
+       230 |   Sched::Preference SchedulingPref
+   231:0-0 |   _Bool isDepthCurrent
+   231:1-1 |   _Bool isHeightCurrent
+       232 |   unsigned int Depth
+       236 |   unsigned int Height
+       240 |   unsigned int TopReadyCycle
+       244 |   unsigned int BotReadyCycle
+       248 |   const TargetRegisterClass * CopyDstRC
+       256 |   const TargetRegisterClass * CopySrcRC
+           | [sizeof=264, dsize=264, align=8,
+           |  nvsize=264, nvalign=8]
```

#93566

2214026e didn't fix an unused variable
warning correctly.

The pass iterates over the IR multiple times, but most code doesn't use
AMX. Therefore, do a single iteration in advance to check whether a
function uses AMX at all, and exit early if it doesn't. This makes the
function-has-AMX path slightly more expensive, but AMX users probably
care a lot less about compile time than JIT users (which tend to not use
AMX).

For us, it reduces the time spent in this pass from 0.62% to 0.12%.

Ideally, we wouldn't even need to iterate over the function to determine
that it doesn't use AMX.

The size of the properties is fixed, so no need for a BitVector.
Assigning small, fixed-size bitsets is faster.

It's a minor performance improvement.

Otherwise code that depends on those targets being enabled might not get
compiled correctly even if the targets are explicitly included in the
configuration (in my case NVVM target for MLIR).

This PR adds transpose + pack/unpack folding support for transpose ops
in the form of `linalg.generic` ops. There were also some bugs with the
permutation composing in the previous patterns, so this PR fixes these
bugs and adds tests for them as well.

When a float attribute is printed with Hex, we should not elide the type
because it is parsed back as i64 otherwise.

Followup to #94487

There is simply way too much going on inside getNode. The complicated
constant folding of vector handling works by looking for build_vector
operands, and then tries to getNode the scalar element and then checks
if
constants were the result. As a side effect, this produces unused scalar
operation nodes (previously, without flags). If the vector operation
were later scalarized, it would find the flagless constant folding
temporary and lose the flag. I don't think this is a reasonable way for
constant folding to operate, but for now fix this by ensuring flags
on the original operation are preserved in the temporary.
    
This yields a clear code improvement for AMDGPU when f16 isn't legal.
The Wasm cases switch from using a libcall to compare and select. We are
evidently
missing the fcmp+select to fminimum/fmaximum handling, but this would be
further
improved when that's handled. AArch64 also avoids the libcall, but looks
worse and
has a different call for some reason.

We already assert that the given PC is in range and that the
function has a body, so the SrcMap should generally never be empty.
However, when generating destructors, we create quite a few instructions
for which we have no source information, which may cause the previous
assertion to fail. Return the end of the source map in this case.

Extra tests for https://github.com/llvm/llvm-project/pull/94610.

This PR is to add validation to the test case with
get_image_array_size/get_image_dim calls
(transcoding/check_ro_qualifier.ll). This test case didn't pass
validation because of invalid emission of OpCompositeExtract instruction
(Result Type must be the same type as Composite.).

In order to fix the problem this PR improves type inference in general
and partially addresses issues:
* https://github.com/llvm/llvm-project/issues/91998
* https://github.com/llvm/llvm-project/issues/91997

A reproducer from the description of the latter issue is added as a new
test case as a part of this PR.

Oryon is an ARM V8 AArch64 CPU from Qualcomm.

---------

Co-authored-by: Wei Zhao <wezhao@qti.qualcomm.com>

Create a new class and file for functions that update GDB index.

Extend the folding ability of the RewriteAsConstant patterns to include
tensor.pad operations on constants. The new pattern with constant fold
tensor.pad operations which operate on tensor constants and have
statically resolvable padding sizes/values.

    %init = arith.constant dense<[[6, 7], [8, 9]]> : tensor<2x2xi32>
    %pad_value = arith.constant 0 : i32

    %0 = tensor.pad %init low[1, 1] high[1, 1] {
      ^bb0(%arg1: index, %arg2: index):
        tensor.yield %pad_value : i32
    } : tensor<2x2xi32> to tensor<4x4xi32>

becomes

    %cst = arith.constant dense<[[0, 0, 0, 0],
                                 [0, 6, 7, 0],
                                 [0, 8, 9, 0],
                                 [0, 0, 0, 0]]> : tensor<4x4xi32>

Co-authored-by: Spenser Bauman <sabauma@fastmail>

`unmerge_i64` and `unmerge_i32` were exactly the same test cases. This
PR would fix that, so `unmerge_i32` would actually unmerge a 32 bit
value into two 16 bit values.

PR #75125 introduced upward propagation of some OMPT-related CMake
variables.
For stand-alone builds this results in a warning that `SCOPE_PARENT` has
no meaning in a top-level directory.

Co-authored-by: Marianne Mailhot-Sarrasin <marianne.mailhot-sarrasin@octasic.com>

/llvm-project/llvm/lib/Target/NVPTX/NVVMIntrRange.cpp:33:12:
error: private field 'SmVersion' is not used [-Werror,-Wunused-private-field]
  unsigned SmVersion;
           ^
1 error generated.

Adds an AArch64-specific version of isLSRCostLess, changing the relative
importance of the various terms from the formulae being evaluated.

This has been split out from my vscale-aware LSR work, see the RFC for
reference:
https://discourse.llvm.org/t/rfc-vscale-aware-loopstrengthreduce/77131

Revamp the NVVMIntrRange pass making the following updates:
- Use range attributes over range metadata. This is what instcombine has
move to for ranges on intrinsics in
https://github.com/llvm/llvm-project/pull/88776 and it seems a bit
cleaner.
- Consider the `!"maxntid{x,y,z}"` and `!"reqntid{x,y,z}"` function
metadata when adding ranges for `tid` srge instrinsics. This can allow
for smaller ranges and more optimization.
- When range attributes are already present, use the intersection of the
old and new range. This complements the metadata change by allowing
ranges to be shrunk when an intrinsic is in a function which is inlined
into a kernel with metadata. While we don't call this more then once
yet, we should consider adding a second call after inlining, once this
has had a chance to soak for a while and no issues have arisen.

I've also re-enabled this pass in the TM, it was disabled years ago due
to "numerical discrepancies" https://reviews.llvm.org/D96166. In our
testing we haven't seen any issues with adding ranges to intrinsics, and
I cannot find any further info about what issues were encountered.

Summary:
This reverts commit 574ab7e7.

IceLakeServer/SkylakeServer can only use Port01 for the FADD/FSUB stage

Confirmed with uops.info + Agner

IceLakeServer was copying these from SkylakeServer, but integer HADD/SUB can now run on an extra port

Summary:
Currently, we register images into a linear table according to the
logical OpenMP device identifier. We then initialize all of these images
as one block. This logic requires that images are compatible with *all*
devices instead of just the one that it can run on. This prevents us
from running on systems with heterogeneous devices (i.e. image 1 runs on
device 0 image 0 runs on device 1).

This patch reworks the logic by instead making the compatibility check a
per-device query. We then scan every device to see if it's compatible
and do it as they come.

This fixes compile time regression after #93692.

This will be used for a new CI job that runs the static analyzer.