* Fixes #286 for cases not covered by prior fix
* Closes #512
* Closes #840
* Closes #913
* Closes #1161

Enhance CheckCombLoops errors with connection info

* Closes #1203

* Add Scaladoc for EdgeData API

* Include stringified vertices in EdgeNotFoundException

Emit Verilog else-if for Register Updates

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Modifies the Verilog emitter to emit "else if" blocks as opposed to
more deeply nested "else begin if" blocks. This improves the output
Verilog readability.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Fix handling of read enables for write-first (default) memories in VerilogMemDelays

* Additional refactoring to clean up pass implementation

* Make register names match old scheme to appease CI

Major features:

- Added Interval type, as well as PrimOps asInterval, clip, wrap, and sqz.
- Changed PrimOp names: bpset -> setp, bpshl -> incp, bpshr -> decp
- Refactored width/bound inferencer into a separate constraint solver
- Added transforms to infer, trim, and remove interval bounds
- Tests for said features

Plan to be released with 1.3

Make TopWiringTransform Idempotent

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

This changes TopWiringTransform to remove TopWiringAnnotations after
it runs.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* Replace instance analysis code with InstanceGraph API calls

* Add convenience implicits for using TargetTokens as safe boxed strings

Fix minor regression from #1124

Implement read-first memory behavior in Verilog

* Corrects behavior under write collisions
* Avoids heavily refactoring pass

* Stop ignoring read-under-write (RUW) parameter
* Add conservative check: blackbox only when RUW is "undefined"
* VerilogMemDelays now throws InternalError for read-first memories
* Previously, read-first mems were incorrectly implemented as write-first

* Make the read-under-write (RUW) parameter typesafe
* Add RUW support to the FIRRTL proto and CHIRRTL grammar

* Define read-write collison for independently clocked mem ports

* Included definition of initiating write/read operation

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* dont chain inline and refix RenameMaps

* cache already inlined modules

* reduce number of chained RenameMaps

* InlineInstances: cleanup and add comments

Create instance maps once for each Module

Gender to Flow

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

The following names are changed:
  - gender        -> flow
  - Gender        -> Flow
  - MALE          -> SourceFlow
  - FEMALE        -> SinkFlow
  - BIGENDER      -> DuplexFlow
  - UNKNOWNGENDER -> UnknownFlow

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* Copy benchmark.py from https://github.com/jackkoenig/firrtlbench
* Make benchmark use this repo instead of hardcoded subdirectory

Example Use:
  benchmark/scripts/benchmark_cold_compile.py -N 8 --designs regress/*.fir --version master master^

* Update Travis stage names to match new versions

* Drop minor versions from Travis stage names and delete old comment

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

Adds a space to correct in an exception message. Corrects
capitalization in Github to it's official name (GitHub) and adds a
link to file an issue.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

* Refactor: remove redundancy code

* Fixed coding style