Disallow memory ports being declared in a when scope and referenced
elsewhere.  Add one test of this behavior.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Update the ICache.fir regression test from Rocket Chip.  This was built
using Chisel3 3.4.3 with an unmerged fix that includes a wire to avoid
letting an mport escape the when scope in which it is defined.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

This will make it easier for formal verification
libraries to make use of these emitters.

Both transforms are (most likely) not needed.

The SMT backend actually needs to run PropagatePresetAnnotations
(as will treadle at some point).
None of the Verilog specific passes were actually required!

* implement NoCommonSubexpressionElimination to resolve chipsalliance/chisel3#2006

* Update src/main/scala/firrtl/passes/CommonSubexpressionElimination.scala

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Correct incorrect type specified for memories in the FIRRTL
specification.  This is important because the memory type determines
what is a legal bundle to try to connect to a memory port.

I based this off of FIRRTL accepting the following circuit:

    circuit MemOrder:
      module MemOrder:
        input r: {addr : UInt<3>, en : UInt<1>, clk : Clock, flip data : UInt<1>}
        input w: {addr : UInt<3>, en : UInt<1>, clk : Clock, data : UInt<1>, mask : UInt<1>}
        input rw: {addr : UInt<3>, en : UInt<1>, clk : Clock, flip rdata : UInt<1>, wmode : UInt<1>, wdata : UInt<1>, wmask : UInt<1>}

        mem memory:
          data-type => UInt<1>
          depth => 8
          reader => r
          writer => w
          readwriter => rw
          read-latency => 1
          write-latency => 1
          read-under-write => undefined

        memory.r <= r
        memory.w <= w
        memory.rw <= rw

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

This reverts commit 2630537c.

Fix an OG bug where Andr, Orr, and Xorr would accept an arbitrary number
of operands.  Verilog emission doesn't support this and will silently
drop all operands after the first.  E.g., "andr(a, b)" would emit as
"&a".  After this commit, "andr(a, b)" will be rejected by checking
passes.

For archaeological purposes, this appears to have been the behavior
dating back to when this was added in d2d3260a

.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

This has outlived its usefulness.

* rearrange passes to enable optimized firrtl emission

* Support ConstProp on padded arguments to comparisons with literals

* Move shr legalization logic into ConstProp

Continue calling ConstProp of shr in Legalize.

Co-authored-by: Jack Koenig <koenig@sifive.com>

Co-authored-by: Jack Koenig <koenig@sifive.com>

Change the FIRRTL spec to disallow a zero-width multiplexer select.
Clarify that the select line can be either one-bit or zero-bit, but will
infer to one-bit.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Add new util "groupByIntoSeq"
* Restore annotation order when dedupping annotations
* Attribute annotations now deduplicate
* Implement doc string anno dedup

Co-authored-by: Jack Koenig <koenig@sifive.com>

* deprecate DependencyAPIMigration.

This will allow chiseltest to save
the hash code to disk for the purpose
of caching simulation binaries.

Add typedef in DependencyManager.

This is a bug fix, before this PR, Scala compiler will infer `Nothing`, which makes code below failed to compile:
```
class UserCompiler extends TransformManager(Seq(Dependency(UserPass))) {
  override def optionalPrerequisiteOf: Seq[TransformDependency] = Seq(
    Dependency[DedupModules]
  )
}
```

* Add transform to deduplicate memory annotations
* Add annotation deduplication to Dedup stage
* ResolveAnnotationPaths and EliminateTargetPaths now invalidate the dedup annotations transform
* Verilog emitter now throws exception when memory annotations fail to dedup

Co-authored-by: Jack Koenig <koenig@sifive.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Update sbt-scalafmt to 2.4.3

Relax spec on 0-bit mux select, use SFC behavior

Change the FIRRTL specification document to allow for 0-bit mux selects.
The existing ZeroWidths pass will promote these to a 1-bit, 0-valued
select signal (which effectively means that the mux can be optimized
away to just the false path).

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

The pass injects pipe registers immediately after the declaration of the
memory. This can be problematic if the clock for the associated memory
port is defined after the declaration of the memory. For any memory port
clocks that are driven by non-ports, we now inject a wire before the
pipe register declarations to be sure there are no
use-before-declaration issues.

* Fixes #2206

* Restore parsed MultiInfo structure in firrtl parser

* Change erroneous expected output in InfoSpec test

FileInfo compression sorts the outputted entries alphabetically, but
this test did not reflect that fact

* Fix typo in comment

* Add unit tests for file locator parsing

* Fix syntax issues and typos

* More redundant braces removed

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* smt: include firrtl statement names in SMT and btor2 output

* smt: remove println

* smt: make tests run again and fix stale ones

Apparently `private` classes aren't found by th sbt test runner.

Add a new option to the FIRRTL compiler, "--start-from = <form>".  If
used, this will cause the compiler to assume that the input FIRRTL
circuit is already in the specific form.  It will then skip unnecessary
passes given this information.

E.g., if a user requests to run "firrtl -X verilog --start-from low"
then the compiler will only run transforms necessary to get from low
FIRRTL to Verilog.  Transforms necessary for ingesting FIRRTL IR will be
run if needed (checks and type/kind/flow resolution).

To implement this, a CurrentFirrtlStateAnnotation is added.  Advanced
users can use this directly to tell the FIRRTL compiler exactly what
transforms have already been run, including the ability to ignore checks
or type/kind/flow resolution if they so desire.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Add Protocol Buffer emission export

This adds infrastructure and annotations that let a user emit a FIRRTL
circuit as a Protocol Buffer.

Fixes #1696.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* fixup! Add Protocol Buffer emission export

* make PresetRegAnnotation public

this annotation is useful outside the firrtl compiler:
- to implement a pass that creates registers which
  need to be initialized at the beginning of simulation
  (e.g., for formal verification)
- to support preset registers in treadle

* add PresetRegAnnotation test and deal with annotation correctly in RemoveReset pass

Add a compiler/emitter that can target minimal high form.  This will
produce output that only has CHIRRTL constructs removed.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Remove java.io in MustDedup