Stop allowing Chisel users to describe circuits where a CHIRRTL memory
port escapes its when scope.  Previously, this was special-cased to
allow for existing Chisel standard library constructions to work.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Change the read with enable method on SyncReadMem to not return the
CHIRRTL mport.  This results in saner code generation in CHIRRTL where
the mport can't be used in subsequent code blocks.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* Change Chisel warnings to use logger instead of println

It also uses the same logger as the Builder so that if we ever refactor
that to be passed as an argument, it will be the same logger for both
Builder and warning reporting.

(cherry picked from commit 04caf395)

* Add ChiselEnum.safe factory method and avoid warning

Previously, ChiselEnum would warn any time a UInt is converted to an
Enum. There was no way to suppress this warning. Now there is a factory
method (`.safe`) that does not warn and returns (Enum, Bool) where the
Bool is the result of calling .isValid on an Enum object. The regular
UInt cast is also now smarter and will not warn if all bitvectors of the
width of the Enum are legal states.

(cherry picked from commit 5fe539c7)

# Conflicts:
#	src/test/scala/chiselTests/ChiselSpec.scala

* Update docs for ChiselEnum

(cherry picked from commit bfb77d4c

)

* Resolve merge conflicts and waive false bincompat issue

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Restore aop.Select behavior for CloneModuleAsRecord

(cherry picked from commit 0531cb53)

* Change behavior of aop.Select to not include CloneModuleAsRecord

Previously, CloneModuleAsRecord clones would result in the same
BaseModule object coming up multiple times when using APIs like
.instances, .collectDeep, and .getDeep. This was not the intended
behavior and can lead to very subtle bugs.

(cherry picked from commit 25a84b56

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Fix CloneModuleAsRecord support for .toTarget

(cherry picked from commit d3e13ce2)

# Conflicts:
#	core/src/main/scala/chisel3/RawModule.scala

* Set refs for ModuleClone and ClonePorts in less hacky way

(cherry picked from commit b87107ad

)

* Fixup for backport

* Resolve merge conflicts
* Fix semantic meaning change of Module -> MultiIOModule on master
* Waive bincompat errors that cannot impact Scala users

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit 44c7fca8

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

(cherry picked from commit 6a806918

)

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>

(cherry picked from commit a5cfd8bf

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Add Clock
* Add Analog
* Add Interval
* Add line from User Types (...) to Record

(cherry picked from commit 5e8ef455

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit 04de237e

)

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>

* explain sub-projects

* Update README.md

Co-authored-by: Megan Wachs <megan@sifive.com>

Co-authored-by: Megan Wachs <megan@sifive.com>
(cherry picked from commit ea84a176

)

Co-authored-by: Deborah Soung <debs@sifive.com>

(cherry picked from commit ac31c62e

)

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>

* Add test to check ShiftRegister(s) with delay is 0.

This should break ShiftRegister(x, 0) since last is not exist in a empty
Seq. Originally, test only test 1 to 4, which missed a potential bug
from #1723.

* Fix ShiftRegister with 0 delay.

if ShiftRegisters is empty, java will complain:
```
  java.util.NoSuchElementException
    scala.collection.LinearSeqOptimized.last(LinearSeqOptimized.scala:150)
```
This fix this issue and return `in` directly when ShiftRegister size is 0.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

* Stop Emitting BlackBoxResourceAnno (#1954)

* Change HasBlackBoxResource to Resolve Resources

Change HasBlackBoxResource to resolve resources immediately and emit
BlackBoxInlineAnno instead of a BlackBoxResourceAnno.  This removes the
need for a FIRRTL compiler to grok the Java Resource API in order to
handle BlackBoxResourceAnno.

Emit BlackBoxInlineAnno from HasExtModuleResource instead of
BlackBoxResourceAnno.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
(cherry picked from commit 820200b7

)

# Conflicts:
#	src/main/scala/chisel3/util/BlackBoxUtils.scala

* fixup! Stop Emitting BlackBoxResourceAnno (#1954)

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

(cherry picked from commit 1875d3da

)

Co-authored-by: Martin Schoeberl <martin@jopdesign.com>

* Implement PLA (#1912)

* implement pla

* implement test for pla

* implement inverter matrix of PLA generator

* fix for review.

Co-authored-by: Boyang Han <yqszxx@gmail.com>
(cherry picked from commit 1c1a4d72

)

* fix 2.11

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>

* add ShiftRegisters to expose register inside ShiftRegister.

* use Seq.iter for oneline implementation.

(cherry picked from commit 361e4433

)

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>

* Fix RegInit of Bundle lits (#1688)

Implemented by folding Element.ref into Data.ref. Element.ref had
special handling for literals, but because Bundles can also be literals,
there were code paths that tried to get the ref of a Bundle literal
which was non-existent. Now, all literals are handled together.

Because FIRRTL does not have support for Bundle literals, Bundle literal
refs are implemented by materializing a Wire.

(cherry picked from commit 5a6ce660

)

* Waive bincompat issue on package private method

Co-authored-by: Jack Koenig <koenig@sifive.com>

* add convert(chirrtl: cir.Circuit): fir.Circuit to convert chirrtl to firrtl.

* add scaladoc.

* add test.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit 7dd2d7db

)

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>

(cherry picked from commit 4d8fed00

)

Co-authored-by: Kevin Laeufer <laeufer@cs.berkeley.edu>

* Cookbook: clean up desiredName example

* Update cookbook.md

(cherry picked from commit 9fdea534

)

Co-authored-by: Megan Wachs <megan@sifive.com>

* Add some error context to Converter .getRefs (#1878)

(cherry picked from commit c7142802

)

* Waive package private binary incompatibilities

Co-authored-by: Jack Koenig <koenig@sifive.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit 23b3fe8a

)

Co-authored-by: Megan Wachs <megan@sifive.com>

(cherry picked from commit 804271ea

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

* fixing context bug (#1874)

(cherry picked from commit 2c7264a6

)

# Conflicts:
#	src/main/scala/chisel3/aop/injecting/InjectingAspect.scala
#	src/test/scala/chiselTests/aop/InjectionSpec.scala

* Resolve conflicts

Co-authored-by: Deborah Soung <debs@sifive.com>

(cherry picked from commit da5e5cb5

)

Co-authored-by: Martin Schoeberl <martin@jopdesign.com>

nitpick

(cherry picked from commit 83eeda2e

)

Co-authored-by: Fabien Marteau <fabien.marteau@armadeus.com>

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
(cherry picked from commit 0cc35a26

)

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>

* Remove space between backticks and language
* Make code examples in memories explanation work

Co-authored-by: Jack Koenig <koenig@sifive.com>
(cherry picked from commit f39ec2ef

)

Co-authored-by: Carlos Eduardo <me@carlosedp.com>

(cherry picked from commit 6e22d91e

)

Co-authored-by: Megan Wachs <megan@sifive.com>

* Add documentation guide about memory initialization

* Move information to experimental and add ref

(cherry picked from commit e0da5ae4

)

Co-authored-by: Carlos Eduardo <me@carlosedp.com>

(cherry picked from commit d3e2b346

)

Co-authored-by: XinJun Ma <xinjun.ma@qq.com>

(cherry picked from commit a54d37d2

)

Co-authored-by: Kalamár Ödön <kalamarodon@gmail.com>

(cherry picked from commit 9c9bc131

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

* Add CCC2021 info

* Update README.md

* Update README.md

(cherry picked from commit 7b8fbbe8

)

Co-authored-by: Jiuyang Liu <liu@jiuyang.me>

* Update the FAQ and add doc on versioning
* Update modules.md

Co-authored-by: Megan Wachs <megan@sifive.com>
(cherry picked from commit 03ec2156

)

Co-authored-by: Jack Koenig <koenig@sifive.com>

Updates to chisel3 documentation for website:
* guard code examples with mdoc and fix errors encountered along the way
* move some website content here vs splitting the content across two repos
* Bring in the interval-types and loading memories content so that it will be visible from the website
* remove all references to the wiki (deprecated)
* Remove reference to Wiki from the README
* fix tabbing and compile of chisel3-vs-chisel2 section
* Appendix: faqs now guarded and compile
* FAQs: move to resources section

(cherry picked from commit f1ad5b58

)

Co-authored-by: Megan Wachs <megan@sifive.com>

Change top.cpp to deassert reset one time unit before the clock asserts.
This avoids a Verilator simultation issue in top.cpp where the eval()
function is only called once per simultation loop.  If the clock and
reset are both changed and eval() is only called once, then any
combinational update due to a change in reset is not visible to the
sequential logic.  This avoids issues where the downstream compilation
utilities move synchronous reset logic outside of an always block that
describes a synchronous reset flip flop.

Reset now deasserts on time unit 10 and the clock ticks on time unit
11.

h/t @albert-magyar

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
(cherry picked from commit ac094a5e

)

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

Change a test to use emitChirrtl instead of emitFirrtl. This test
isn't supposed to be running the Scala FIRRTL Compiler, but the latter
method causes this to happen.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
(cherry picked from commit 492a71d6

)

Co-authored-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* [plugin] Split ChiselComponent into its own file

(cherry picked from commit e80e9a3b)

* [plugin] Implement autoclonetype in the compiler plugin

(cherry picked from commit 14942312)

* [plugin] Stop autoclonetype stack traces when using plugin

The compiler plugin obviates the need for using stack traces to
determine outer objects in autoclonetype. When the plugin was used to
compile a given Bundle, it will no longer collect a stack trace upon
construction. This should have massive benefits to elaboration runtime.

(cherry picked from commit a8d32388)

* [plugin] Disable BundleComponent by default, add option to enable

(cherry picked from commit 3bea6167

)

* Fix plugin scalacOptions for 2.11

* allowReflectiveAutoCloneType must work outside of Builder context

Co-authored-by: Jack Koenig <koenig@sifive.com>