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  35. Oct 07, 2021
    • mergify[bot]'s avatar
      ~Remove all Bundle cloneTypes and~ chiselRuntimeDeprecate its use (backport #2052) (#2151) · 6d794802
      mergify[bot] authored 
      

* Remove all Bundle cloneTypes and chiselRuntimeDeprecate its use (#2052)

* Remove all manual cloneTypes and make it chisel runtime deprecated to add one
* runtime deprecate cloneType with runtime reflection
* [Backport this commit] Bundle: add check that override def cloneType still works (will be made an error later)
* Plugin: make it an error to override cloneType and add a test for that
* Docs: can't compile the cloneType anymore
* BundleSpec: comment out failing test I cannot get to fail or ignore

Co-authored-by: default avatarJack Koenig <koenig@sifive.com>
(cherry picked from commit ce15ad50

)

# Conflicts:
#	src/test/scala/chiselTests/BundleSpec.scala

* BundleSpec: fix merge conflict and change test to check that it does compile with a cloneType, just a warning not an error

* Downgrade warning to error

* restore import that is still needed on the backport

* Put back override def cloneType

* Checkpoint -- tests pass but with more errors than one would expect

* Bundle Spec: tests still passing despite throwing runtime deprecation errors

* BundleSpec: clean up some assertTesterPasses so I can check they don't have the runtime exception

* bundles-and-vecs: docs now more strict about warnings

* BundleSpec:  stop trying to test plugin things because 2.11 doesn't use plugin

Co-authored-by: default avatarMegan Wachs <megan@sifive.com>
      6d794802
  37. Oct 06, 2021
  39. Oct 05, 2021
  41. Sep 18, 2021
  43. Sep 16, 2021
  45. Sep 09, 2021
  47. Aug 31, 2021
  49. Aug 30, 2021
  51. Aug 25, 2021
    • mergify[bot]'s avatar
      Lazy .fir Emission (backport #2083) (#2084) · 927212b7
      mergify[bot] authored 
      * Remove chisel3's own firrtl Emitter, use firrtl Serializer

This will be slightly slower as it involves converting from Chisel
modules to FIRRTL modules before turning them into Strings. This cost is
somewhat mitigated by doing that conversion lazily such that we never
materialize the entire firrtl Circuit in memory, only 1 module at a
time.

(cherry picked from commit 73bd4ee6)

# Conflicts:
#	src/main/scala/chisel3/internal/firrtl/Emitter.scala
#	src/test/scala/chiselTests/PrintableSpec.scala
#	src/test/scala/chiselTests/VecLiteralSpec.scala
#	src/test/scala/chiselTests/experimental/verification/VerificationSpec.scala

* Emit .fir lazily, overcomes JVM 2 GiB String limit

(cherry picked from commit d9c30ea0)

# Conflicts:
#	src/main/scala/chisel3/internal/firrtl/Emitter.scala

* Use BufferedCustomFileEmission in CircuitSerializationAnnotation

(cherry picked from commit a6eb2ad8

)

* Resolve backport conflicts

* Waive binary compatibility issues

Co-authored-by: default avatarJack Koenig <koenig@sifive.com>
      927212b7
  53. Aug 18, 2021
  55. Aug 06, 2021
    • mergify[bot]'s avatar
      Small changes to memory doc (#2062) (#2063) · 6a943006
      mergify[bot] authored 
      * Small changes to memory doc
- Fixed typo "except" => "accept"
- Use `Counter` explicitly in ROM section example.

* Fix counter doc compile error

* remove invisible doc block in memory example

* more small fixes to make mem example pass doc compile

* Get rid of sine wave iterator in memory doc

* get rid of tabs on VecInit example

* get rid of tabs on VecInit example

(cherry picked from commit 75c00606

)

Co-authored-by: default avatarChick Markley <chick@qrhino.com>
      6a943006
  57. Jul 23, 2021
  59. Jul 15, 2021
  61. Jul 10, 2021
  63. Jul 09, 2021
  65. Jul 08, 2021