- Nov 14, 2020
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Adam Izraelevitz authored
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- Nov 06, 2020
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mergify[bot] authored
This is a refinement of the assertion added in #1616 then removed in #1654. Because Records now set the refs of children upon binding, later, unbound Records could incorrectly override the refs. The first set should win. (cherry picked from commit 8187318e ) Co-authored-by:
Jack Koenig <koenig@sifive.com>
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mergify[bot] authored
* Remove Data.setRef assertion (#1654) It causes issues for some legal (if awkward) patterns. A larger refactor of when refs are set could reinstate this check. (cherry picked from commit 679dd54a ) # Conflicts: # core/src/main/scala/chisel3/internal/Builder.scala * Fix merge conflict Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Nov 03, 2020
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mergify[bot] authored
Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 70538487 ) Co-authored-by:
John Ingalls <43973001+ingallsj@users.noreply.github.com>
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mergify[bot] authored
* Bugfix - adding external modules was broken (#1649) (cherry picked from commit d21fe713 ) * Remove test because not backportable * Remove extra space Co-authored-by:
Adam Izraelevitz <azidar@gmail.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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mergify[bot] authored
* ExtModule's lacked support built in support for providing the verilog source. This changes creates traits that can be used with ExtModule to provide the support currently found in BlackBox - Add support for ExtModule helpers - HasExtModuleResource to use addResource - HasExtModuleInline to use setInline - HasExtModulePath to use addPath - Add tests of the above support. - Note: These tests use Stage instead of Driver - Added ScalaDoc for HasBlackBoxInline#setInline * Fix the danged trailing commas. * Change to use `.transform` as the correct API for `ChiselStage` (cherry picked from commit fd92809e ) Co-authored-by:
Chick Markley <chick@qrhino.com>
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- Oct 31, 2020
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mergify[bot] authored
This requires a combination of things, but it happens to be a combination used by Diplomacy in Rocket Chip. It must be a Record in compatibility code with Vecs as fields and a mix of components with and without set directions. (cherry picked from commit 0979133b ) Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Oct 28, 2020
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mergify[bot] authored
(cherry picked from commit 362a3e35 ) Co-authored-by:
Adam Izraelevitz <azidar@gmail.com>
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- Oct 27, 2020
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mergify[bot] authored
* Fix crosslinks in mdoc. Can't use md suffix * Removed all .md crossrefs Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 58fa3c11 ) Co-authored-by:
Adam Izraelevitz <azidar@gmail.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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mergify[bot] authored
* Use Data refs for name prefixing with aggregate elements (#1616) * Use Data refs for name prefixing with aggregate elements Vecs set the refs of their elements upon construction of those elements. In the past, Records haven't set their elements refs until module close, but it can be done sooner. Doing it upon binding means that refs will at least be available for Records used in hardware elements. Since only bound Data can be connected to anyway, Aggregate elements being connected to will always have a ref which we can then use for creating naming prefixes. * Add tighter correctness checks * Handle more cases in connection prefixing Add support for forcing setRef to override a previous setting. This is only used by BlackBox ports which need to drop their io prefix. Also add a Try() around Data.bindingToString which sometimes throws exceptions when being used to .toString a Data in an error message. * Strip trailing spaces in names in compiler plugin (cherry picked from commit 0745dede ) * Resolve binary compatibility issues Change to Builder.scala is cleaner than waiving all of the (safe to waive) failures. Co-authored-by:
Jack Koenig <koenig@sifive.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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mergify[bot] authored
* Bugfix - module name collision for injecting aspect (#1635) * Bugfix - module name collision for injecting aspect * Fixed mechanism to avoid module name collisions * Added comments for reviewer feedback Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 1b6bd89d ) * Update InjectingAspect.scala Add additional function for backwards compatibility. Co-authored-by:
Adam Izraelevitz <azidar@gmail.com>
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mergify[bot] authored
* Added forcename transform and tests * Added documentation and additional error checking * Added mdoc. Added RunFirrtlTransform trait * Removed TODO comment * Addressed reviewer feedback * Removed trailing comma Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 2d98132d ) Co-authored-by:
Adam Izraelevitz <azidar@gmail.com>
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mergify[bot] authored
Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@sifive.com> Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit d5db3881 ) Co-authored-by:
PENGUINLIONG <admin@penguinliong.moe>
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mergify[bot] authored
Causes issues when building the website, using these docs. Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 55809b1d ) Co-authored-by:
Adam Izraelevitz <azidar@gmail.com>
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- Oct 22, 2020
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mergify[bot] authored
* Fix `-e` option causing ChiselStage.emit* to error Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@sifive.com> * Add test of `-e` ChiselStage behavior Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@sifive.com> * fixup! Add test of `-e` ChiselStage behavior (cherry picked from commit 26deb770 ) Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@sifive.com>
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- Oct 20, 2020
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mergify[bot] authored
* Change prefix stack to List[String] (#1617) This allows for sharing of the prefix stacks between Data, and removes a boxing per prefix stack element that is no longer necessary. Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit fef0b68a ) * Add binary compatibility waivers Co-authored-by:
Jack Koenig <koenig@sifive.com>
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mergify[bot] authored
* Return 0.U for asUInt of a zero-element Seq Add a condition to SeqUtils.asUInt to have it return an unspecified width 0.U when applied to an empty sequence. This enables the ability to do a Cat of a zero-element sequence. Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@sifive.com> * Test elaboration of Cat on zero-element Seq Signed-off-by:
Schuyler Eldridge <schuyler.eldridge@sifive.com> (cherry picked from commit ac641fb1 ) Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@sifive.com>
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- Oct 15, 2020
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mergify[bot] authored
Package chisel3 was not properly marked as an internal package so source locators in reported errors would point to files like Bits.scala. (cherry picked from commit baea2da8 ) Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Oct 14, 2020
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mergify[bot] authored
* When prefixing with a data, eagly get local name (#1614) Fixes #1606 Previously, the Data itself would be put on the prefix stack and its full name would be used as the prefix for subsequent names. This meant that prefixes would grow quadratically as the prefix is present both on the Data pushed to the stack, and on the stack itself. This is fixed by just using the "local" name of the Data being pushed on the stack. A related issue is deferring the name resolution. This led to unintuitive behavior when the name of a Data used as a prefix is overridden later (usually when the Data is a return value). The overriding name would show up in prefixes twice instead of once. It is much more intuitive to grab the name at the moment of the connection creating the prefix rather than deferring to later. Co-authored-by:
mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> (cherry picked from commit 1b15dca5 ) * Waive MiMa failures on package private methods Co-authored-by:
Jack Koenig <koenig@sifive.com>
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- Oct 10, 2020
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Jack Koenig authored
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- Oct 06, 2020
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Schuyler Eldridge authored
* Fix broken mdoc (#1600) * Fix broken mdoc * Added test-chisel-docs to ci workflow * Move Chisel3 to SPDX license conventions (#1604) Change source and other relevant files to use SPDX license LICENSE file moved from src/ to ./ Changed license file to refer to this per recommendation using_spdx_license_list_short_identifiers WARNING: Tests fail with as of yet undiagnosed error ``` [error] Failed: Total 691, Failed 19, Errors 0, Passed 672, Ignored 15 [error] Failed tests: [error] chiselTests.QueueSpec [error] examples.VendingMachineGeneratorSpec [error] chiselTests.HarnessSpec [error] chiselTests.ConnectSpec [error] chiselTests.aop.SelectSpec [error] chiselTests.PopCountSpec [error] chiselTests.CloneModuleSpec [error] (Test / test) sbt.TestsFailedException: Tests unsuccessful [error] Total time: 379 s (06:19), completed Sep 30, 2020 12:38:17 AM sbt:chisel3> ``` * Move more docs (#1601) * Fix broken mdoc * Added test-chisel-docs to ci workflow * Add requirement on build-treadle job * Added forgotton colon * Forgot cd into chisel3 dir * moved three docs into explanations * Updated reference Co-authored-by:
Schuyler Eldridge <schuyler.eldridge@gmail.com> Co-authored-by:
Adam Izraelevitz <azidar@gmail.com> Co-authored-by:
Chick Markley <chick@qrhino.com>
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- Sep 23, 2020
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chick authored
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- Sep 22, 2020
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Jack Koenig authored
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- Sep 18, 2020
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chick authored
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- Sep 16, 2020
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Albert Chen authored
Co-authored-by:Megan Wachs <megan@sifive.com>
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Jack Koenig authored
Use caching to reduce number of expensive lookups
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- Sep 15, 2020
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Adam Izraelevitz authored
* Added documentation. Bugfix in plugin. Moved plugin APIs to separate package * Revert reg naming behavior (omit underscore) * Added documentation and a test * Addressed reviewer feedback.
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- Sep 10, 2020
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Jerry Zhao authored
Test all cases in ParameterizedOneHotTesters Co-authored-by:Jack Koenig <koenig@sifive.com>
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Jack Koenig authored
ChiselCircuitAnnotation no longer extends CustomFileEmission, rather it is Unserializable. Also the --chisel-output-file is added to the ChiselCli. New phase AddSerializationAnnotations constructs a CircuitSerializationAnnotation from ChiselCircuitAnnotation and ChiselOutputFileAnnotation. Both .fir and .pb file formats are supported. Default format is .fir unless a --chisel-output-file is specified with a .pb extension.
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HappyQuark authored
* fix loadMemoryFromFile to work with binary Passed in hexOrBinary parameter to ChiselLoadMemoryAnnotation * Added test for binary format support in loadMemoryFromFile * Added test for binary format support in loadMemoryFromFile
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- Sep 05, 2020
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Jack Koenig authored
Using JVM system properties sbt.sourcemode and sbt.workspace, one can now easily build chisel3 with firrtl from source Example use: Assuming firrtl is cloned into the chisel3 root directory: $ sbt -Dsbt.sourcemode=true -Dsbt.workspace=$PWD Alternatively, one can set these properties in .sbtopts which can then be committed, enabling building from source by default
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- Sep 03, 2020
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Jiuyang Liu authored
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Jiuyang Liu authored
* add chisel plugin to mill build system. * update for review.
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- Aug 28, 2020
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Jack Koenig authored
It shouldn't be removed until we also remove the underlying chisel3.Driver.
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Martin Schoeberl authored
A quick fix for the developer's confusion
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- Aug 27, 2020
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Schuyler Eldridge authored
* Add ChiselPhase * Use ChiselPhase in ChiselStage, remove targets Switch from a one-off PhaseManager inside ChiselStage to actually using the newly added ChiselPhase. This removes the targets method (and API) from ChiselStage. * Stop writing to files in ChiselStage$ methods Change the ChiselStage companion object methods, elaborate and convert, to not write files. Under the hood, these are switched from using ChiselStage (which, like all phases, will write files) to using ChiselPhase. * Test that ChiselStage$ methods write no files Modify existing ChiselStage object method tests to check that no files are written. * Expand ChiselStage$ API with more helpers This adds additional methods to the ChiselStage object for going directly from a Chisel module to a string including: CHIRRTL, high FIRRTL IR, Verilog, and SystemVerilog. Differing from their ChiselStage class counterparts, these take no arguments other than the module and write no files. * Add tests of new ChiselStage$ helper methods * Use ChiselStage object in tests Signed-off-by:Schuyler Eldridge <schuyler.eldridge@ibm.com>
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- Aug 26, 2020
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Jack Koenig authored
It must run after the typer, but doesn't need to "run right after". The stricter dependency conflicted with the semanticdb-typer.
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- Aug 22, 2020
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Adam Izraelevitz authored
* Updated PR template to include checklist and documentation updates * Change milestones to 3.x.x * updated milestones
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Adam Izraelevitz authored
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Adam Izraelevitz authored
* Added website docs and mdoc. Removed all warnings * Updated README and added build to circle ci * Added how to build documentation, deprecated wiki * Fix copypasta Co-authored-by:mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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