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  1. Aug 31, 2021
    • mergify[bot]'s avatar
      Fix chisel3 <> for compatibility Bundles (Take 3) (#2093) (#2104) · c23f2e57
      mergify[bot] authored 
      Previous incomplete fixes in #2023 and #2031.

The legality of a FIRRTL connection is determined by type and flow.
Chisel does not have access to true flow information. Previous fix
attempts tried to use ActualDirection as a stand-in for flow, but it is
incorrect in many cases. This new approach checks the flows of the
lvalue and rvalues in the connect and flips the connection if either
the lvalue cannot be a sink or the rvalue cannot be a source.

(cherry picked from commit 7fb2c1eb

)

Co-authored-by: default avatarJack Koenig <koenig@sifive.com>
      c23f2e57
  3. Aug 30, 2021
  5. Jul 10, 2021
    • mergify[bot]'s avatar
      Fix chisel3 <> for Bundles that contain compatibility Bundles (Take 2) (backport #2031) (#2032) · cf5e811e
      mergify[bot] authored 
      * Fix chisel3 <> for Bundles that contain compatibility Bundles (Take 2) (#2031)

PR #2023 fixed a composition issue for chisel3 biconnects delegating to
FIRRTL partial connect when compatibility mode Bundles are elements of
chisel3 Bundles. It missed an important case though that caused
previously working code to break.

The bug is fixed by doing the automatic flipping for compatibility mode
Bundles that have "Input" as a direction in addition to those that are
"Flipped".

(cherry picked from commit 5183ef88

)

# Conflicts:
#	src/test/scala/chiselTests/CompatibilityInteroperabilitySpec.scala

* Resolve backport conflicts

Co-authored-by: default avatarJack Koenig <koenig@sifive.com>
      cf5e811e
  7. Jul 09, 2021
  9. May 26, 2021
  11. May 20, 2021
  13. Mar 30, 2021
  15. Mar 19, 2021
    • mergify[bot]'s avatar
      Don't toggle top.cpp clock and reset on same cycle (#1820) (#1821) · 3879584e
      mergify[bot] authored 
      

Change top.cpp to deassert reset one time unit before the clock asserts.
This avoids a Verilator simultation issue in top.cpp where the eval()
function is only called once per simultation loop.  If the clock and
reset are both changed and eval() is only called once, then any
combinational update due to a change in reset is not visible to the
sequential logic.  This avoids issues where the downstream compilation
utilities move synchronous reset logic outside of an always block that
describes a synchronous reset flip flop.

Reset now deasserts on time unit 10 and the clock ticks on time unit
11.

h/t @albert-magyar

Signed-off-by: default avatarSchuyler Eldridge <schuyler.eldridge@sifive.com>
(cherry picked from commit ac094a5e

)

Co-authored-by: default avatarSchuyler Eldridge <schuyler.eldridge@sifive.com>
      3879584e
  17. Feb 06, 2021
  19. Jan 27, 2021
  21. Jan 25, 2021
  23. Jan 12, 2021
    • mergify[bot]'s avatar
      Make `toTarget` fail if called on a Literal (or would otherwise not serialize... · 8fa3e07d
      mergify[bot] authored 
      Make `toTarget` fail if called on a Literal (or would otherwise not serialize properly) (bp #1714) (#1719)

* Make `toTarget` fail if called on a Literal (or would otherwise not serialize properly) (#1714)

* Add (failing) Test for Data toTarget calls

Add scaladoc and clean up test

* Builder: don't let .toTarget pass if it won't be able to deserialize properly later

* Update src/test/scala/chiselTests/ReferenceTargetSpec.scala

* Rename and simplify tests for literal toTarget

(cherry picked from commit b578aa5e

)

# Conflicts:
#	chiselFrontend/src/main/scala/chisel3/internal/Builder.scala

* fixup! Make `toTarget` fail if called on a Literal (or would otherwise not serialize properly) (#1714)

Co-authored-by: default avatarMegan Wachs <megan@sifive.com>
Co-authored-by: default avatarSchuyler Eldridge <schuyler.eldridge@sifive.com>
      8fa3e07d
  25. Dec 18, 2020
  27. Dec 17, 2020
    • mergify[bot]'s avatar
      Switch to using Github Actions CI (bp #1690) (#1700) · 47676961
      mergify[bot] authored 
      * Switch to using Github Actions CI (#1690)

MiMa binary compatibility checks are now run on master, but the
mimaPreviousArtifacts are empty which makes the check a no-op. This
helps keep both the build.sbt and CI more consistent between master and
stable branches.

.mergify.yml is also updated with mergify.sc from chisel-repo-tools
using the following configuration:

conditions:
  - status-success=all tests passed
branches:
  - 3.2.x
  - 3.3.x
  - 3.4.x
(cherry picked from commit 25a417f8

)

# Conflicts:
#	.mergify.yml
#	build.sbt
#	project/plugins.sbt

* Resolve merge conflicts and remove docs tests

Docs tests were added in 3.4

Co-authored-by: default avatarJack Koenig <koenig@sifive.com>
      47676961
  29. Nov 14, 2020
  31. Nov 11, 2020
  33. Oct 10, 2020
  35. Aug 07, 2020
  37. Aug 01, 2020
  39. Jun 23, 2020
  41. May 14, 2020
  43. Apr 28, 2020
  45. Apr 11, 2020
  47. Mar 25, 2020
  49. Mar 21, 2020
  51. Mar 20, 2020
  53. Mar 13, 2020
  55. Feb 20, 2020
  57. Feb 19, 2020