- Aug 09, 2017
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Andrew Waterman authored
The following sequence would drop the first store when eccBytes=4: sb x0, 0(t0) nop sb x0, 4(t0) nop sb x0, 1(t0) Because the first and second store are to different ECC granules, the hazard check correctly allowed the second one to proceed, but the third was merged with the second, even though it conflicted with the first. So, don't allow the third to be merged with the second, since the second stored to a different ECC granule.
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- Aug 08, 2017
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Andrew Waterman authored
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Andrew Waterman authored
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Andrew Waterman authored
This reverts commit 7d94074b, which works fine with optimistic behavioral RAMs but not real ones.
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Wesley W. Terpstra authored
Fix ram model source reuse
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Wesley W. Terpstra authored
This reverts commit 39b7e930. Now that the RAMModel can properly tolerate overlapping responses in the face of source reuse, we can re-enable the regression test.
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Yunsup Lee authored
maskrom: retain data for d channel is not ready
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Wesley W. Terpstra authored
If a multibeat response comes back, the source might be reused. If response reordering has made the multibeat response invalid, we need to remember this even if the valid bit is cleared on reuse.
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Yunsup Lee authored
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- Aug 07, 2017
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Yunsup Lee authored
bump riscv-tools
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Andrew Waterman authored
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Andrew Waterman authored
Critical paths
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Andrew Waterman authored
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Andrew Waterman authored
The D$ corrects via writeback, so which word the error was in doesn't matter, as the entire line is corrected.
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Wesley W. Terpstra authored
This makes sure that all the base classes call instantiate()
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Yunsup Lee authored
diplomacy: provide default clock/reset for LazyRawModuleImp
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Yunsup Lee authored
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- Aug 06, 2017
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Yunsup Lee authored
Critical paths
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Andrew Waterman authored
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Andrew Waterman authored
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Andrew Waterman authored
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- Aug 05, 2017
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Andrew Waterman authored
We were using it to compute the next PC on flush vs. replay (which require PC+4 and PC, respectively). This fix gets rid of the adder altogether by reusing the M-stage PC in the flush case, which by construction holds PC+4.
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Andrew Waterman authored
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Andrew Waterman authored
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Andrew Waterman authored
It was counting conflict misses but not cold misses.
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Andrew Waterman authored
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Andrew Waterman authored
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Andrew Waterman authored
Handle parity errors with a pipeline flush rather than a faster frontend replay, reducing a critical path.
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Andrew Waterman authored
The deleted code was a holdover from Hwacha's vector fences.
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Andrew Waterman authored
It takes a while for the pipeline to compute the stall signal, so avoid using it until the last logic levels in the clock cycle.
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Andrew Waterman authored
Don't build verilog twice for emulator and emulator-debug
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- Aug 04, 2017
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Andrew Waterman authored
Fix I$ miss perfctr
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Andrew Waterman authored
Since we aren't using chisel2, the output is the same either way.
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Megan Wachs authored
TLXbar: Allow more masters and slaves and issue a warning.
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Megan Wachs authored
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Andrew Waterman authored
Closes #920
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- Aug 03, 2017
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Andrew Waterman authored
The old version was counting prefetches, too.
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Andrew Waterman authored
Icache prefetch
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Andrew Waterman authored
Fix some critical paths
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Megan Wachs authored
TLFuzzer: Allow Ordered clients to be created as well by the fuzzer
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