- Mar 21, 2024
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John Ingalls authored
* util/package: VecToAugmentedVec extract * traverse check GPA bits higher than HGATP * check upper bits of VSATP addr when starting PTW * remove pte_cache_addr, just use pte_addr
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- Feb 15, 2024
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Jiuyang Liu authored
Add error message in LazyModule construction
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Jerry Zhao authored
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- Jan 26, 2024
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Jerry Zhao authored
Fix build.
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- Jan 24, 2024
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Gon Solo authored
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- Jan 18, 2024
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Jerry Zhao authored
Update README.md
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Jerry Zhao authored
Fix outdated technical report link.
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Jerry Zhao authored
Update ECC SRAM to improve throughput on full write
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- Jan 17, 2024
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Kevin Qin authored
Change a_sublane to also check the mask to see if the transaction a partial write. Improves throughput in cases when the full bus is being utilized
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- Jan 16, 2024
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Ricardo Menotti authored
fixing tech report broken link
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- Jan 10, 2024
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Letu Ren authored
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- Jan 05, 2024
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Jerry Zhao authored
Support vector-units w/o L1D$ access (copy #3537)
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- Dec 29, 2023
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Jerry Zhao authored
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Jerry Zhao authored
SContext is remaps to HContext when in VSMode
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- Dec 19, 2023
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Julian Bailey authored
* Fix the mapping when we access scontext or hcontext to ensure we don't switch targets. * Add comment to indicate why we are mapping the S to VS and VS to S.
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- Nov 25, 2023
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Jerry Zhao authored
Remove Scalar Crypto and BitManip (copy #3532)
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Yangyu Chen authored
(cherry picked from commit 218ae0aa)
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Jiuyang Liu authored
(cherry picked from commit 5bef59a8) # Conflicts: # src/main/scala/tile/Core.scala
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Jiuyang Liu authored
(cherry picked from commit 74dd9b19)
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Jiuyang Liu authored
(cherry picked from commit df66c19e)
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- Nov 14, 2023
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Sihao Liu authored
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- Nov 09, 2023
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Jerry Zhao authored
Add DelayQueue (backport #3520)
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- Nov 08, 2023
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abejgonzalez authored
(cherry picked from commit 4dc63059)
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abejgonzalez authored
(cherry picked from commit b2b78fd6)
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- Nov 02, 2023
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mergify[bot] authored
(cherry picked from commit b47fdf9b ) Co-authored-by:
Jerry Zhao <jerryz123@berkeley.edu>
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- Sep 27, 2023
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Jerry Zhao authored
Remove vsim/emulator flows, add simple make verilog flow (backport #3494)
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Jerry Zhao authored
Remove SCIE interface (backport #3499)
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Jerry Zhao authored
* Remove vsim/emulator flows, add simple make verilog flowx * Remove unnecessary dependencies from Makefile' (cherry picked from commit 4a1715eb)
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Jerry Zhao authored
(cherry picked from commit d4775722)
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Jerry Zhao authored
Connect all s1_data fields in SimpleHellaIF (backport #3497)
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Jerry Zhao authored
Fix Makefrag for mill cross-compile (backport #3489)
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Jerry Zhao authored
Make StoreGen support narrow typ field (copy #3479)
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Jerry Zhao authored
Suppress SourceShrinker require if no shrinking is to be done (copy #3485)
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Jerry Zhao authored
(cherry picked from commit 1d69e6db)
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- Sep 21, 2023
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Jerry Zhao authored
(cherry picked from commit ec106af4)
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- Sep 19, 2023
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Jerry Zhao authored
This makes it a bit easier to use the StoreGen circuit. StoreGen shouldn't error if the `typ` argument is narrower than `maxSize` would normally permit. (cherry picked from commit 9a416a16)
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Jerry Zhao authored
(cherry picked from commit a8663bc0)
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- Aug 22, 2023
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Jiuyang Liu authored
Sync master with dev
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Jerry Zhao authored
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Jiuyang Liu authored
Fixes for latest chisel
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