* convert TestHarness to chisel3, work around compatibility mode naming issue.

* explicit tieoff in axi4 bundle.

* use DontCare.

* DCache does not block Acquire/ProbeAck by outstanding Release

* include more bits in the block_probe_for_pending_release_ack address comparison to eliminate most false positives

* tl_out_a block acquire for pending release_ack: include address comparison to eliminate most false positives

* tl_out_a block acquire for pending release_ack: use s2_req.addr for address comparison to improve timing

* Fix a DTIM X-prop issue

Convert PutPartials to PutFulls when the mask is full to avoid RMW.

* Rework ScratchpadSlavePort fix, since it dovetails with DTIM fix

Co-authored-by: Andrew Waterman <andrew@sifive.com>

* Prevent TLWidthWidget from generating X outputs

Widening WidthWidgets contain an uninitialized data register.  The first
transaction through the widget may propagate that register's contents
on the bus, which is logically correct but can propagates a X, violating
our constraint that we never provide X in the payload of a valid xact.

Fix by propagating in.bits.data, rather than the register, until the
register has been written at least once.  This is cheaper than resetting
the register.

* Add comments to WidthWidget X fix

Co-authored-by: Andrew Waterman <andrew@sifive.com>

Since the state transitions in the divider depend on the data values, the
in.ready signal becomes X if the input data is X.  This fact becomes
problematic for speculative instructions, since the state might not yet
have been initialized.

Co-authored-by: Andrew Waterman <andrew@sifive.com>

rs1[4] was being ignored in determining whether the access was a read
or a write.  Other CSR instructions are unaffected.  RV32I/RV64I cores
are unaffected.  Only Caboose and Rocket with RV32E are affected;
Bullet is not.

Co-authored-by: Andrew Waterman <andrew@sifive.com>

ITIM writes are implemented as RMW operations and so cause ITIM reads.
Thus, initializing the ITIM can cause Xs to leak out.  But full-word
ITIM writes don't need to be RMW, so we can suppress the Xs from leaking
out in that special case.

Conveniently, we already require that TIMs be initialized with full-word
writes for ECC purposes, so preventing the Xs from leaking out only in the
full-word write case suffices.

Co-authored-by: Andrew Waterman <andrew@sifive.com>

* Fix x-prop issue in ScratchpadSlavePort

Don't let D$ req.cmd field become X, or else it'll make req.ready become X,
which confuses the Rocket core.

* Fix regression introduced in fix

Wrong D$ command was sent on first slave-port access.

Co-authored-by: Andrew Waterman <andrew@sifive.com>

* Don't attempt to cover non-existent U-mode counters

* Modification in the logic to not cover non-existent U-mode counters

Co-authored-by: Andrew Waterman <andrew@sifive.com>
Co-authored-by: Umer Imran <umerimran@lambda44.internal.sifive.com>

Fixes an x-prop issue

Co-authored-by: Andrew Waterman <andrew@sifive.com>

Fix a scratchpad ECC bug

When a store is immediately followed by a load to the same address,
and the load detects an ECC error (corresponding to the old contents),
the store fails to take effect.

Only affects data scratchpads, not D$.

Co-authored-by: Jack Koenig <koenig@sifive.com>

TraceGen should observe dmem.ordered when attempting a fence

Support timebase-frequency in the cpus node of the Device Tree.

	modified:   src/main/scala/diplomacy/Resources.scala
	modified:   src/main/scala/subsystem/BaseSubsystem.scala

Deprecate several legacy APIs

Bump Chisel and firrtl along 3.4.1.x

fix a ccover bug in I$