Fix CSRRSI/CSRRCI in RV32E cores (#2820)

rs1[4] was being ignored in determining whether the access was a read
or a write.  Other CSR instructions are unaffected.  RV32I/RV64I cores
are unaffected.  Only Caboose and Rocket with RV32E are affected;
Bullet is not.

Co-authored-by: Andrew Waterman <andrew@sifive.com>