aboutsummaryrefslogtreecommitdiff
path: root/model
AgeCommit message (Collapse)AuthorFilesLines
2021-06-29vmem_svNN: Perform PTW accesses always as SupervisorNathaniel Wesley Filardo3-8/+8
Using the new riscv_mem functions to elide the Privilege level computation
2021-06-29riscv_mem: push effectivePermission to peripheryNathaniel Wesley Filardo1-27/+67
- Expose "just below the periphery" functions that allow bypassing effectivePermission and instead take a Permission explicitly (as well as an AccessType, in the case of reads, to distinguish Read from Execute; for writes, just an ext_access_type that will be wrapped in Write).
2021-06-29vmem_svNN: mem_read(Read(Data), ...) the PTEsNathaniel Wesley Filardo3-3/+3
Previously we were erroneously passing the instruction's memory access to lower layers of the memory machinery. For example, a store instruction still should be attempting reads of PTEs, not stores.
2021-06-29effectivePrivilege: don't consult globalsNathaniel Wesley Filardo1-2/+2
This function was inconsistent in its use of arguments vs. globals. However, in all existing cases, the arguments are fed as the values of these globals, so this has no observable impacts in the current model, but hopefully prevents confusion later.
2021-06-25Fix the non-RVFI_DII buildAlex Richardson1-4/+4
This was broken by #76
2021-06-25Merge pull request #76 from arichardson/rvfi-newRobert Norton6-64/+276
Add support for the new RVFI_DII socket format
2021-06-21Merge pull request #85 from ybc-alkaid/pmpRobert Norton1-1/+1
PMP address match misses some corner cases
2021-05-27Fix Error_not_implemented exception on lr.rl or sc.aq.Robert Norton1-12/+12
The RISC-V specification says: "Software should not set the rl bit on an LR instruction unless the aq bit is also set, nor should software set the aq bit on an SC instruction unless the rl bit is also set. LR.rl and SC.aq instructions are not guaranteed to provide any stronger ordering than those with both bits clear, but may result in lower performance." i.e. these instructions are allowed but do not have stronger atomicity guarantees than the versions without the bits set. To implement this we AND the rl bit on lr with the aq bit, and similarly AND the aq bit on sc with the rl bit. Prior to this patch these instructions would generate Error_not_implemented in riscv_mem.sail . An alternative to this patch would be to 'downgrade' the operations there but I think that would risk future extensions calling mem_read / mem_write without being made aware of these special cases (open to discussion).
2021-05-21Extend LR / SC / AMO execute for unused widths.Robert Norton1-9/+23
Even though the relevant encodings are not currently valid it does no harm to implement them in the obvious way. It means it will be trivial to enable them if they do become valid and extensions can choose to implement them simply by adding the relevant decoding.
2021-05-21Fix internal error caused by invalid LR / SC / AMO widths.Robert Norton1-6/+19
The RISC-V spec. only shows LR / SC / AMOs for word and double widths even though the encoding would naturally extend to other widths (it is a little unclear). Previously the Sail model would decode the unused widths but throw an internal error in execute. With this change the unused widths will not be decoded and will cause illegal instruction exceptions instead.
2021-03-19pmp: pmp address match misses some corner casesBicheng Yang1-1/+1
2021-03-16Also set the IXL field in the RVFI traceAlex Richardson1-0/+1
2021-03-16Fix sending version2 trace optional dataAlex Richardson1-6/+16
Previously we were always sending the fields in a fixed order, but we have to omit optional data that is not set. This refactors the logic and adds new getters for the optional data. This code will become a lot simpler once we support the -c2 backend of sail.
2021-03-16Report the current privilege level via RVFIAlex Richardson1-0/+1
2021-03-16Improvements to the version 2 RVFI trace formatAlex Richardson2-65/+71
All packets start with a magic 8 byte header now and the riscv_sim.c code now sends an acknowledgement packet for version requests.
2021-03-16Fix missing rvfi_halt field when converting v2 to v1 RVFI trace formatAlex Richardson1-0/+1
This was causing TestRIG to wait indefinitely
2021-03-16Add a -v rvfi flag to add RVFI debug loggingAlex Richardson1-3/+3
2021-03-16Initial implementation of new RVFI_DII socket formatAlex Richardson6-54/+247
This is not a finalized trace format yet.
2021-02-11Remove unused register files.Prashanth Mundkur2-4/+0
2021-02-11Make N extension configurable.Prashanth Mundkur2-1/+3
2021-02-11Merge pull request #81 from scottj97/sstatus-fixPrashanth Mundkur1-1/+1
Prevent CSRW to sstatus from modifying uie & upie if N-ext not present
2021-02-02Reformat excessively-long linesScott Johnson1-2/+8
2021-01-27MRET and SRET should increment minstret when successfulScott Johnson1-8/+6
2021-01-26Prevent CSRW to sstatus from modifying uie & upie if N-ext not presentScott Johnson1-1/+1
2020-11-30Ignore undefined bits in mstatus on writeAlex Richardson1-1/+6
2020-11-17Bug fix: when writing CSR sip, ignore attempt to change undelegated SSIPScott Johnson1-1/+1
Instead of always writing 0 to mie.SSIP when it's undelegated.
2020-11-09Perform PTE checks on DII fetch (with jrtc27)Peter Rugg1-16/+23
2020-10-15Store PC in mtval on EBREAK to match a spec update.Prashanth Mundkur1-1/+1
Fixes #70.
2020-10-15Handle non-atomic but aligned writes to the 64-bit HTIF i/o port on RV32.Prashanth Mundkur1-28/+65
Unaligned writes or writes narrower than 32-bits are not supported. Fixes #69.
2020-09-22Handle empty predecessor or successor RW sets in FENCE as no-ops, as IO ↵Prashanth Mundkur1-2/+4
concurrency is not yet modelled. Thanks to Christopher Pulte.
2020-09-04Handle hints explicitly in order to not trap on them.Prashanth Mundkur1-0/+158
This currently maps their assembly renditions to non-standard instructions to preserve bidirectional mappings. Fixes #67 and #29.
2020-09-03Add the mstatush CSR for RV32, and hardwire the MBE and SBE fields to 0.Prashanth Mundkur3-0/+26
2020-08-25Implement mcountinhibit IR bit to squash minstret incrementScott Johnson1-1/+2
2020-08-25Allow CSR read/write to mcountinhibitScott Johnson1-0/+1
2020-08-25Add missing disassembler mapping for mcountinhibit CSRScott Johnson1-0/+1
2020-08-20Fix conditions CSR definedness. Fixes #65.Prashanth Mundkur1-11/+11
2020-06-30Merge pull request #64 from nwf:pte-check-split with minor edits.Prashanth Mundkur6-19/+46
Split ext_ptw into pieces and add documentation
2020-06-30Split ext_ptw into pieces and add documentationNathaniel Wesley Filardo6-19/+43
It was somewhat annoying that CHERI would have had to track both successful and erroneous occurrences within the same type. Break the failures out to their own form and, while here, attempt to write down my understanding of the extension's information flow through vmem.
2020-06-30SV32: allow external specification of PTE extension bitsNathaniel Wesley Filardo2-1/+12
Just because they're not present in the SV32 PTE doesn't mean that models necessarily need to interpret them as zeros; any constant will do just fine. This allows extensions (like CHERI) that have both RV32 and RV64 versions to define more standard idiomatic interpretation to the bits within the PTE extension field.
2020-06-27A kinder, gentler splitting of ext_access_type's ReadWriteNathaniel Wesley Filardo6-31/+37
This redoes https://github.com/rems-project/sail-riscv/pull/57 without nearly as much excitement. We sill want it for CHERI, so that we can signal from the instruction to the PTW whether we are prepared to load a capability (or will strip any tags that we load) and whether the store will (or might) set a tag. Thanks to Prashanth Mundkur for several improvements.
2020-06-22Add some comments and docs.Prashanth Mundkur1-0/+4
2020-06-20Allow extensions to override page fault causesJessica Clarke4-5/+8
Otherwise there's no use for PTW_Ext_Error. This is required for sail-cheri-riscv to be able to make use of its own page table exceptions. The alternative to this is to pass the ext_ptw to translationException, but given PTW_Ext_Error exists it seems this was the intended way, and aligns with how access faults vs page faults are distinguished.
2020-06-09Properly handle invalid virtual addresses in address translation.Prashanth Mundkur2-6/+28
Fixes #58.
2020-06-05Avoid relying on ext_access_type values in PMP, to be compatible with ↵Prashanth Mundkur1-8/+8
extensions.
2020-05-28Remove effects on assembly introduced in 1bb74ef9, fix effects on ↵Prashanth Mundkur4-18/+18
encdec_compressed.
2020-05-27Fix bug: mtval (and [su]tval) should get vaddr, not paddrScott Johnson1-2/+2
2020-05-27Rename var to distinguish vaddr from paddrScott Johnson1-16/+16
2020-05-27Rename param to distinguish vaddr from paddrScott Johnson1-2/+2
2020-05-26Fix FMIN/FMAX when QNaN+SNaN (#53)Scott Johnson2-40/+33
* New functions to simplify float NaN detection * Remove unnecessary intermediate values Now that we have simpler function f_is_NaN * FMIN/FMAX should return canonical NaN if both operands are NaN Fixes #52. * Simplify logic for FMIN/FMAX Spec says "If only one operand is a NaN, the result is the non-NaN operand." So no need to distinguish SNaN from QNaN here.
2020-05-22Add compressed F,D instructions.Prashanth Mundkur3-2/+164
Fixes #51.
generated by cgit v1.1 at 2024-09-18 15:24:55 +0000