Initial implementation of new RVFI_DII socket format

This is not a finalized trace format yet.

6 files changed, 247 insertions, 54 deletions

diff --git a/model/riscv_fetch_rvfi.sail b/model/riscv_fetch_rvfi.sail
index 955dd4b..2579b77 100644
--- a/model/riscv_fetch_rvfi.sail
+++ b/model/riscv_fetch_rvfi.sail
@@ -1,6 +1,6 @@
 function fetch() -> FetchResult = {
-  rvfi_exec->rvfi_order()    = minstret;
-  rvfi_exec->rvfi_pc_rdata() = EXTZ(get_arch_pc());
+  rvfi_inst_data->rvfi_order()    = minstret;
+  rvfi_pc_data->rvfi_pc_rdata() = EXTZ(get_arch_pc());
 
   /* First allow extensions to check pc */
   match ext_fetch_check_pc(PC, PC) {
@@ -13,12 +13,7 @@ function fetch() -> FetchResult = {
         TR_Failure(e, _) => F_Error(e, PC),
         TR_Address(_, _) => {
           let i = rvfi_instruction.rvfi_insn();
-          rvfi_exec->rvfi_insn()     = EXTZ(i);
-          /* TODO: should we write these even if they're not really registers? */
-          rvfi_exec->rvfi_rs1_data() = EXTZ(X(i[19 .. 15]));
-          rvfi_exec->rvfi_rs2_data() = EXTZ(X(i[24 .. 20]));
-          rvfi_exec->rvfi_rs1_addr() = sail_zero_extend(i[19 .. 15],8);
-          rvfi_exec->rvfi_rs2_addr() = sail_zero_extend(i[24 .. 20],8);
+          rvfi_inst_data->rvfi_insn()   = EXTZ(i);
           if   (i[1 .. 0] != 0b11)
           then F_RVC(i[15 .. 0])
           else {
diff --git a/model/riscv_mem.sail b/model/riscv_mem.sail
index 3f90cf6..cd43eb6 100644
--- a/model/riscv_mem.sail
+++ b/model/riscv_mem.sail
@@ -75,13 +75,16 @@ function pmp_mem_read forall 'n, 0 < 'n <= max_mem_access . (t : AccessType(ext_
 $ifdef RVFI_DII
 val rvfi_read : forall 'n, 'n > 0. (xlenbits, atom('n), MemoryOpResult(bits(8 * 'n))) -> unit effect {wreg}
 function rvfi_read (addr, width, result) = {
-  rvfi_exec->rvfi_mem_addr() = EXTZ(addr);
+  rvfi_mem_data->rvfi_mem_addr() = EXTZ(addr);
+  rvfi_mem_data_present = true;
   match result {
+    /* TODO: report tag bit for capability writes and extend mask by one bit. */
     MemValue(v) => if   width <= 8
-                   then { rvfi_exec->rvfi_mem_rdata() = sail_zero_extend(v,64);
-                          rvfi_exec->rvfi_mem_rmask() = rvfi_encode_width_mask(width) }
-                   else { rvfi_exec->rvfi_mem_rdata() = v[63..0];
-                          rvfi_exec->rvfi_mem_rmask() = 0xFF},
+                   then { rvfi_mem_data->rvfi_mem_rdata() = sail_zero_extend(v,64);
+                          rvfi_mem_data->rvfi_mem_rmask() = rvfi_encode_width_mask(width) }
+                   else { rvfi_mem_data->rvfi_mem_rdata() = v[63..0]; /* report low bits only */
+                          assert(width == 16, "Should only be used for capabilities");
+                          rvfi_mem_data->rvfi_mem_rmask() = rvfi_encode_width_mask(16)},
     MemException(_) => ()
   };
 }
@@ -135,13 +138,16 @@ function mem_write_ea (addr, width, aq, rl, con) = {
 $ifdef RVFI_DII
 val rvfi_write : forall 'n, 0 < 'n <= max_mem_access . (xlenbits, atom('n), bits(8 * 'n)) -> unit effect {wreg}
 function rvfi_write (addr, width, value) = {
-  rvfi_exec->rvfi_mem_addr() = EXTZ(addr);
+  rvfi_mem_data->rvfi_mem_addr() = EXTZ(addr);
+  rvfi_mem_data_present = true;
   if width <= 8 then {
-    rvfi_exec->rvfi_mem_wdata() = sail_zero_extend(value,64);
-    rvfi_exec->rvfi_mem_wmask() = rvfi_encode_width_mask(width);
+    rvfi_mem_data->rvfi_mem_wdata() = sail_zero_extend(value,64);
+    rvfi_mem_data->rvfi_mem_wmask() = rvfi_encode_width_mask(width);
   } else {
-    rvfi_exec->rvfi_mem_wdata() = value[63..0];
-    rvfi_exec->rvfi_mem_wmask() = 0xFF;
+    /* TODO: report tag bit for capability writes and extend mask by one bit. */
+    rvfi_mem_data->rvfi_mem_wdata() = value[63..0];
+    assert(width == 16, "Should only be used for capabilities");
+    rvfi_mem_data->rvfi_mem_wmask() = rvfi_encode_width_mask(width);
   }
 }
 $else
diff --git a/model/riscv_regs.sail b/model/riscv_regs.sail
index 56ebf20..7cdb8d1 100644
--- a/model/riscv_regs.sail
+++ b/model/riscv_regs.sail
@@ -84,8 +84,9 @@ function rX r = {
 $ifdef RVFI_DII
 val rvfi_wX : forall 'n, 0 <= 'n < 32. (regno('n), xlenbits) -> unit effect {wreg}
 function rvfi_wX (r,v) = {
-  rvfi_exec->rvfi_rd_wdata() = EXTZ(v);
-  rvfi_exec->rvfi_rd_addr() = to_bits(8,r);
+  rvfi_int_data->rvfi_rd_wdata() = EXTZ(v);
+  rvfi_int_data->rvfi_rd_addr() = to_bits(8,r);
+  rvfi_int_data_present = true;
 }
 $else
 val rvfi_wX : forall 'n, 0 <= 'n < 32. (regno('n), xlenbits) -> unit
diff --git a/model/riscv_step_rvfi.sail b/model/riscv_step_rvfi.sail
index dd24365..5132568 100644
--- a/model/riscv_step_rvfi.sail
+++ b/model/riscv_step_rvfi.sail
@@ -6,7 +6,7 @@ function ext_pre_step_hook()  -> unit = ()
 
 function ext_post_step_hook() -> unit = {
   /* record the next pc */
-  rvfi_exec->rvfi_pc_wdata() = EXTZ(get_arch_pc())
+  rvfi_pc_data->rvfi_pc_wdata() = EXTZ(get_arch_pc())
 }
 
 val ext_init : unit -> unit effect {wreg}
@@ -14,12 +14,7 @@ function ext_init() = {
   init_base_regs();
   init_fdext_regs();
   /* these are here so that the C backend doesn't prune them out. */
-  rvfi_set_instr_packet(0x0000000000000000);
-  print_bits("", rvfi_get_cmd());
   // let _ = rvfi_step(0);
-  rvfi_zero_exec_packet();
-  rvfi_halt_exec_packet();
-  let _ = rvfi_get_exec_packet();
   ext_rvfi_init();
   ()
 }
diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail
index c1f062b..5f09d1e 100644
--- a/model/riscv_sys_control.sail
+++ b/model/riscv_sys_control.sail
@@ -285,8 +285,9 @@ function tval(excinfo : option(xlenbits)) -> xlenbits = {
 
 $ifdef RVFI_DII
 val rvfi_trap : unit -> unit effect {wreg}
+// TODO: record rvfi_trap_data
 function rvfi_trap () =
-  rvfi_exec->rvfi_trap() = 0x01
+  rvfi_inst_data->rvfi_trap() = 0x01
 $else
 val rvfi_trap : unit -> unit
 function rvfi_trap () = ()
diff --git a/model/rvfi_dii.sail b/model/rvfi_dii.sail
index 00de956..902f1f8 100644
--- a/model/rvfi_dii.sail
+++ b/model/rvfi_dii.sail
@@ -25,6 +25,10 @@ val rvfi_get_cmd : unit -> bits(8) effect {rreg}
 
 function rvfi_get_cmd () = rvfi_instruction.rvfi_cmd()
 
+val rvfi_get_insn : unit -> bits(32) effect {rreg}
+
+function rvfi_get_insn () = rvfi_instruction.rvfi_insn()
+
 val print_instr_packet : bits(64) -> unit
 
 function print_instr_packet(bs) = {
@@ -33,7 +37,7 @@ function print_instr_packet(bs) = {
   print_bits("instruction", p.rvfi_insn())
 }
 
-bitfield RVFI_DII_Execution_Packet : bits(704) = {
+bitfield RVFI_DII_Execution_Packet_V1 : bits(704) = {
    rvfi_intr      : 703 .. 696, // [87] Trap handler:            Set for first instruction in trap handler.
    rvfi_halt      : 695 .. 688, // [86] Halt indicator:          Marks the last instruction retired 
                                 //                                      before halting execution.
@@ -58,46 +62,237 @@ bitfield RVFI_DII_Execution_Packet : bits(704) = {
    rvfi_order     :  63 ..   0, // [00 - 07] Instruction number:      INSTRET value after completion.
 }
 
-register rvfi_exec : RVFI_DII_Execution_Packet
+bitfield RVFI_DII_Execution_Packet_InstMetaData : bits(192) = {
+  /// The rvfi_order field must be set to the instruction index. No indices
+  /// must be used twice and there must be no gaps. Instructions may be
+  /// retired in a reordered fashion, as long as causality is preserved
+  /// (register and memory write operations must be retired before the read
+  /// operations that depend on them).
+  rvfi_order  : 63 .. 0,
+  /// rvfi_insn is the instruction word for the retired instruction. In case
+  /// of an instruction with fewer than ILEN bits, the upper bits of this
+  /// output must be all zero. For compressed instructions the compressed
+  /// instruction word must be output on this port. For fused instructions the
+  /// complete fused instruction sequence must be output.
+  rvfi_insn  : 127 ..  64,
+  /// rvfi_trap must be set for an instruction that cannot be decoded as a
+  /// legal instruction, such as 0x00000000.
+  /// In addition, rvfi_trap must be set for a misaligned memory read or
+  /// write in PMAs that don't allow misaligned access, or other memory
+  /// access violations. rvfi_trap must also be set for a jump instruction
+  /// that jumps to a misaligned instruction.
+  rvfi_trap  : 135 ..  128,
+  /// The signal rvfi_halt must be set when the instruction is the last
+  /// instruction that the core retires before halting execution. It should not
+  /// be set for an instruction that triggers a trap condition if the CPU
+  /// reacts to the trap by executing a trap handler. This signal enables
+  /// verification of liveness properties.
+  rvfi_halt  : 143 ..  136,
+  /// rvfi_intr must be set for the first instruction that is part of a trap
+  /// handler, i.e. an instruction that has a rvfi_pc_rdata that does not
+  /// match the rvfi_pc_wdata of the previous instruction.
+  rvfi_intr  : 151 ..  144,
+  /// rvfi_mode must be set to the current privilege level, using the following
+  /// encoding: 0=U-Mode, 1=S-Mode, 2=Reserved, 3=M-Mode
+  rvfi_mode  : 159 ..  152,
+  /// rvfi_ixl must be set to the value of MXL/SXL/UXL in the current privilege level,
+  /// using the following encoding: 1=32, 2=64
+  rvfi_ixl  : 167 ..  160,
+
+  /// When the core retires an instruction, it asserts the rvfi_valid signal
+  /// and uses the signals described below to output the details of the
+  /// retired instruction. The signals below are only valid during such a
+  /// cycle and can be driven to arbitrary values in a cycle in which
+  /// rvfi_valid is not asserted.
+  rvfi_valid  : 175 ..  168,
+  // Note: since we only send these packets in the valid state, we could
+  // omit the valid signal, but we need 3 bytes of padding after ixl anyway
+  // so we might as well include it
+  padding  : 191 ..  176,
+}
+
+bitfield RVFI_DII_Execution_Packet_PC : bits(128) = {
+  /// This is the program counter (pc) before (rvfi_pc_rdata) and after
+  /// (rvfi_pc_wdata) execution of this instruction. I.e. this is the address
+  /// of the retired instruction and the address of the next instruction.
+  rvfi_pc_rdata  : 63 .. 0,
+  rvfi_pc_wdata  : 127 ..  64,
+}
+
+bitfield RVFI_DII_Execution_Packet_Ext_Integer : bits(256) = {
+  /// rvfi_rd_wdata is the value of the x register addressed by rd after
+  /// execution of this instruction. This output must be zero when rd is zero.
+  rvfi_rd_wdata  : 63 .. 0,
+  /// rvfi_rs1_rdata/rvfi_rs2_rdata is the value of the x register addressed
+  /// by rs1/rs2 before execution of this instruction. This output must be
+  /// zero when rs1/rs2 is zero.
+  rvfi_rs1_rdata  : 127 ..  64,
+  rvfi_rs2_rdata  : 191 .. 128,
+  /// rvfi_rd_addr is the decoded rd register address for the retired
+  /// instruction. For an instruction that writes no rd register, this output
+  /// must always be zero.
+  rvfi_rd_addr      : 199 .. 192,
+  /// rvfi_rs1_addr and rvfi_rs2_addr are the decoded rs1 and rs1 register
+  /// addresses for the retired instruction. For an instruction that reads no
+  /// rs1/rs2 register, this output can have an arbitrary value. However, if
+  /// this output is nonzero then rvfi_rs1_rdata must carry the value stored
+  /// in that register in the pre-state.
+  rvfi_rs1_addr  : 207 .. 200,
+  rvfi_rs2_addr  : 215 .. 208,
+  padding  : 255 .. 216,
+}
+
+bitfield RVFI_DII_Execution_Packet_Ext_MemAccess : bits(256) = {
+  //// For memory operations (rvfi_mem_rmask and/or rvfi_mem_wmask are
+  ///non-zero), rvfi_mem_addr holds the accessed memory location.
+  rvfi_mem_addr  : 63 .. 0,
+  /// rvfi_mem_rdata is the pre-state data read from rvfi_mem_addr.
+  /// rvfi_mem_rmask specifies which bytes are valid.
+  rvfi_mem_rdata  : 127 ..  64,
+  /// rvfi_mem_wdata is the post-state data written to rvfi_mem_addr.
+  /// rvfi_mem_wmask specifies which bytes are valid.
+  rvfi_mem_wdata  : 191 .. 128,
+  // Note: we extend rmask+wmask to 32 bits to allow reporting the mask for
+  // CHERI/RV128 accesses here, even though the actual data needs to be
+  // returned in a separate struct.
+  /// rvfi_mem_rmask is a bitmask that specifies which bytes in rvfi_mem_rdata
+  /// contain valid read data from rvfi_mem_addr.
+  rvfi_mem_rmask      : 223 .. 192,
+  /// rvfi_mem_wmask is a bitmask that specifies which bytes in rvfi_mem_wdata
+  /// contain valid data that is written to rvfi_mem_addr.
+  rvfi_mem_wmask      : 255 .. 224,
+}
 
+bitfield RVFI_DII_Execution_PacketV2 : bits(448) = {
+  trace_version : 31 .. 0, // must be set to 2
+  trace_size : 63 .. 32, // total size of the trace packet + extensions
+  basic_data : 255 .. 64, // RVFI_DII_Execution_Packet_InstMetaData
+  pc_data : 383 .. 256, // RVFI_DII_Execution_Packet_PC
+  // available_fields : 447 .. 383,
+  integer_data_available: 384, // Followed by RVFI_DII_Execution_Packet_Ext_Integer if set
+  memory_access_data_available: 385, // Followed by RVFI_DII_Execution_Packet_Ext_MemAccess if set
+  floating_point_data_available: 386, // TODO: Followed by RVFI_DII_Execution_Packet_Ext_FP if set
+  csr_read_write_data_available: 387, // TODO: Followed by RVFI_DII_Execution_Packet_Ext_CSR if set
+  cheri_data_available: 388, // TODO: Followed by RVFI_DII_Execution_Packet_Ext_CHERI if set
+  cheri_scr_read_write_data_available: 389, // TODO: Followed by RVFI_DII_Execution_Packet_Ext_CHERI_SCR if set
+  trap_data_available: 389, // TODO: Followed by RVFI_DII_Execution_Packet_Ext_Trap if set
+  unused_data_available_fields : 447 .. 390, // To be used for additional RVFI_DII_Execution_Packet_Ext_* structs
+}
+
+register rvfi_inst_data : RVFI_DII_Execution_Packet_InstMetaData
+register rvfi_pc_data : RVFI_DII_Execution_Packet_PC
+register rvfi_int_data : RVFI_DII_Execution_Packet_Ext_Integer
+register rvfi_int_data_present : bool
+register rvfi_mem_data : RVFI_DII_Execution_Packet_Ext_MemAccess
+register rvfi_mem_data_present : bool
+
+// Reset the trace
 val rvfi_zero_exec_packet : unit -> unit effect {wreg}
 
-function rvfi_zero_exec_packet () =
-  rvfi_exec = Mk_RVFI_DII_Execution_Packet(sail_zero_extend(0b0,704))
+function rvfi_zero_exec_packet () = {
+  rvfi_inst_data = Mk_RVFI_DII_Execution_Packet_InstMetaData(EXTZ(0b0));
+  rvfi_pc_data = Mk_RVFI_DII_Execution_Packet_PC(EXTZ(0b0));
+  rvfi_int_data = Mk_RVFI_DII_Execution_Packet_Ext_Integer(EXTZ(0b0));
+  rvfi_int_data_present = false;
+  rvfi_mem_data = Mk_RVFI_DII_Execution_Packet_Ext_MemAccess(EXTZ(0b0));
+  rvfi_mem_data_present = false;
+}
 
 val rvfi_halt_exec_packet : unit -> unit effect {wreg}
 
 function rvfi_halt_exec_packet () =
-  rvfi_exec->rvfi_halt() = 0x01
+  rvfi_inst_data->rvfi_halt() = 0x01
 
-val rvfi_get_exec_packet : unit -> bits(704) effect {rreg}
+val rvfi_get_v2_support_packet : unit -> bits(704)
 
-function rvfi_get_exec_packet() = rvfi_exec.bits()
+function rvfi_get_v2_support_packet () = {
+  let rvfi_exec = Mk_RVFI_DII_Execution_Packet_V1(EXTZ(0b0));
+  // Returning 0x3 in halt instead of 0x1 means that we support the version 2
+  // wire format.
+  let rvfi_exec = update_rvfi_halt(rvfi_exec, 0x03);
+  return rvfi_exec.bits();
+}
+
+val rvfi_get_exec_packet_v1 : unit -> bits(704) effect {rreg}
+
+function rvfi_get_exec_packet_v1 () = {
+  let v1_packet = Mk_RVFI_DII_Execution_Packet_V1(EXTZ(0b0));
+  // Convert the v2 packet to a v1 packet
+  let v1_packet = update_rvfi_intr(v1_packet, rvfi_inst_data.rvfi_intr());
+  let v1_packet = update_rvfi_trap(v1_packet, rvfi_inst_data.rvfi_trap());
+  let v1_packet = update_rvfi_insn(v1_packet, rvfi_inst_data.rvfi_insn());
+  let v1_packet = update_rvfi_order(v1_packet, rvfi_inst_data.rvfi_order());
+
+  let v1_packet = update_rvfi_pc_wdata(v1_packet, rvfi_pc_data.rvfi_pc_wdata());
+  let v1_packet = update_rvfi_pc_rdata(v1_packet, rvfi_pc_data.rvfi_pc_rdata());
+
+  let v1_packet = update_rvfi_rd_addr(v1_packet, rvfi_int_data.rvfi_rd_addr());
+  let v1_packet = update_rvfi_rs2_addr(v1_packet, rvfi_int_data.rvfi_rs2_addr());
+  let v1_packet = update_rvfi_rs1_addr(v1_packet, rvfi_int_data.rvfi_rs1_addr());
+  let v1_packet = update_rvfi_rd_wdata(v1_packet, rvfi_int_data.rvfi_rd_wdata());
+  let v1_packet = update_rvfi_rs2_data(v1_packet, rvfi_int_data.rvfi_rs2_rdata());
+  let v1_packet = update_rvfi_rs1_data(v1_packet, rvfi_int_data.rvfi_rs1_rdata());
+
+  let v1_packet = update_rvfi_mem_wmask(v1_packet, truncate(rvfi_mem_data.rvfi_mem_wmask(), 8));
+  let v1_packet = update_rvfi_mem_rmask(v1_packet, truncate(rvfi_mem_data.rvfi_mem_rmask(), 8));
+  let v1_packet = update_rvfi_mem_wdata(v1_packet, rvfi_mem_data.rvfi_mem_wdata());
+  let v1_packet = update_rvfi_mem_rdata(v1_packet, rvfi_mem_data.rvfi_mem_rdata());
+  let v1_packet = update_rvfi_mem_addr(v1_packet, rvfi_mem_data.rvfi_mem_addr());
+
+  return v1_packet.bits();
+}
+
+val rvfi_get_v2_trace_size : unit -> bits(32) effect {rreg}
+
+function rvfi_get_v2_trace_size () = {
+  let trace_size = 448;
+  let trace_size = if (rvfi_int_data_present) then trace_size + 256 else trace_size;
+  let trace_size = if (rvfi_mem_data_present) then trace_size + 256 else trace_size;
+  return to_bits(32, trace_size);
+}
+
+val rvfi_get_exec_packet_v2 : unit -> bits(448 + 256 + 256) effect {rreg}
+
+function rvfi_get_exec_packet_v2 () = {
+  // TODO: add the other data
+  // TODO: find a way to return a variable-legnth bitvector
+  let packet = Mk_RVFI_DII_Execution_PacketV2(EXTZ(0b0));
+  let packet = update_trace_version(packet, EXTZ(0x2));
+  let packet = update_basic_data(packet, rvfi_inst_data.bits());
+  let packet = update_pc_data(packet, rvfi_pc_data.bits());
+  let packet = update_integer_data_available(packet, bool_to_bits(rvfi_int_data_present));
+  let packet = update_memory_access_data_available(packet, bool_to_bits(rvfi_mem_data_present));
+  // To simplify the implementation (so that we can return a fixed-size vector)
+  // we always return a max-size packet from this function, and the C emulator
+  // ensures that only trace_size bits are sent over the socket.
+  let packet = update_trace_size(packet, rvfi_get_v2_trace_size());
+  return packet.bits() @ rvfi_int_data.bits() @ rvfi_mem_data.bits();
+}
 
-val rvfi_encode_width_mask : forall 'n, 0 < 'n <= 8. atom('n) -> bits(8)
+val rvfi_encode_width_mask : forall 'n, 0 < 'n <= 32. atom('n) -> bits(32)
 
 function rvfi_encode_width_mask(width) =
-  (0xFF >> (8 - width))
+  (0xFFFFFFFF >> (32 - width))
 
 val print_rvfi_exec : unit -> unit effect {rreg}
 
 function print_rvfi_exec () = {
-  print_bits("rvfi_intr     : ", rvfi_exec.rvfi_intr());
-  print_bits("rvfi_halt     : ", rvfi_exec.rvfi_halt());
-  print_bits("rvfi_trap     : ", rvfi_exec.rvfi_trap());
-  print_bits("rvfi_rd_addr  : ", rvfi_exec.rvfi_rd_addr());
-  print_bits("rvfi_rs2_addr : ", rvfi_exec.rvfi_rs2_addr());
-  print_bits("rvfi_rs1_addr : ", rvfi_exec.rvfi_rs1_addr());
-  print_bits("rvfi_mem_wmask: ", rvfi_exec.rvfi_mem_wmask());
-  print_bits("rvfi_mem_rmask: ", rvfi_exec.rvfi_mem_rmask());
-  print_bits("rvfi_mem_wdata: ", rvfi_exec.rvfi_mem_wdata());
-  print_bits("rvfi_mem_rdata: ", rvfi_exec.rvfi_mem_rdata());
-  print_bits("rvfi_mem_addr : ", rvfi_exec.rvfi_mem_addr());
-  print_bits("rvfi_rd_wdata : ", rvfi_exec.rvfi_rd_wdata());
-  print_bits("rvfi_rs2_data : ", rvfi_exec.rvfi_rs2_data());
-  print_bits("rvfi_rs1_data : ", rvfi_exec.rvfi_rs1_data());
-  print_bits("rvfi_insn     : ", rvfi_exec.rvfi_insn());
-  print_bits("rvfi_pc_wdata : ", rvfi_exec.rvfi_pc_wdata());
-  print_bits("rvfi_pc_rdata : ", rvfi_exec.rvfi_pc_rdata());
-  print_bits("rvfi_order    : ", rvfi_exec.rvfi_order());
+  print_bits("rvfi_intr     : ", rvfi_inst_data.rvfi_intr());
+  print_bits("rvfi_halt     : ", rvfi_inst_data.rvfi_halt());
+  print_bits("rvfi_trap     : ", rvfi_inst_data.rvfi_trap());
+  print_bits("rvfi_rd_addr  : ", rvfi_int_data.rvfi_rd_addr());
+  print_bits("rvfi_rs2_addr : ", rvfi_int_data.rvfi_rs2_addr());
+  print_bits("rvfi_rs1_addr : ", rvfi_int_data.rvfi_rs1_addr());
+  print_bits("rvfi_mem_wmask: ", rvfi_mem_data.rvfi_mem_wmask());
+  print_bits("rvfi_mem_rmask: ", rvfi_mem_data.rvfi_mem_rmask());
+  print_bits("rvfi_mem_wdata: ", rvfi_mem_data.rvfi_mem_wdata());
+  print_bits("rvfi_mem_rdata: ", rvfi_mem_data.rvfi_mem_rdata());
+  print_bits("rvfi_mem_addr : ", rvfi_mem_data.rvfi_mem_addr());
+  print_bits("rvfi_rd_wdata : ", rvfi_int_data.rvfi_rd_wdata());
+  print_bits("rvfi_rs2_data : ", rvfi_int_data.rvfi_rs2_rdata());
+  print_bits("rvfi_rs1_data : ", rvfi_int_data.rvfi_rs1_rdata());
+  print_bits("rvfi_insn     : ", rvfi_inst_data.rvfi_insn());
+  print_bits("rvfi_pc_wdata : ", rvfi_pc_data.rvfi_pc_wdata());
+  print_bits("rvfi_pc_rdata : ", rvfi_pc_data.rvfi_pc_rdata());
+  print_bits("rvfi_order    : ", rvfi_inst_data.rvfi_order());
 }