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author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2021-01-06 19:56:40 -0800 |
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committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2021-02-11 19:14:19 -0800 |
commit | 99be0960a2d1027b0ace9dbe066bf38bb16b9b97 (patch) | |
tree | 6470b5179823c797629bae2f65f5a9d60cbc83f0 /model | |
parent | 33cacbd88289bf0503b07433ee0c2923e32ef946 (diff) | |
download | sail-riscv-99be0960a2d1027b0ace9dbe066bf38bb16b9b97.zip sail-riscv-99be0960a2d1027b0ace9dbe066bf38bb16b9b97.tar.gz sail-riscv-99be0960a2d1027b0ace9dbe066bf38bb16b9b97.tar.bz2 |
Make N extension configurable.
Diffstat (limited to 'model')
-rw-r--r-- | model/riscv_insts_next.sail | 2 | ||||
-rw-r--r-- | model/riscv_sys_regs.sail | 2 |
2 files changed, 3 insertions, 1 deletions
diff --git a/model/riscv_insts_next.sail b/model/riscv_insts_next.sail index 0d23452..e77fbcb 100644 --- a/model/riscv_insts_next.sail +++ b/model/riscv_insts_next.sail @@ -7,7 +7,7 @@ mapping clause encdec = URET() <-> 0b0000000 @ 0b00010 @ 0b00000 @ 0b000 @ 0b00000 @ 0b1110011 function clause execute URET() = { - if (~ (haveUsrMode())) + if (~ (haveUsrMode()) | ~(sys_enable_next())) then handle_illegal() else if ~ (ext_check_xret_priv (User)) then ext_fail_xret_priv () diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail index 1601aea..714f3c9 100644 --- a/model/riscv_sys_regs.sail +++ b/model/riscv_sys_regs.sail @@ -76,6 +76,8 @@ val sys_enable_writable_misa = {c: "sys_enable_writable_misa", ocaml: "Platform. val sys_enable_rvc = {c: "sys_enable_rvc", ocaml: "Platform.enable_rvc", _: "sys_enable_rvc"} : unit -> bool /* whether misa.{f,d} were enabled at boot */ val sys_enable_fdext = {c: "sys_enable_fdext", ocaml: "Platform.enable_fdext", _: "sys_enable_fdext"} : unit -> bool +/* whether the N extension was enabled at boot */ +val sys_enable_next = {c: "sys_enable_next", ocaml: "Platform.enable_next", _: "sys_enable_next"} : unit -> bool /* This function allows an extension to veto a write to Misa if it would violate an alignment restriction on |