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| author | Alex Richardson <Alexander.Richardson@cl.cam.ac.uk> | 2020-11-17 17:41:53 +0000 |
|---|---|---|
| committer | Alex Richardson <Alexander.Richardson@cl.cam.ac.uk> | 2021-03-16 16:18:11 +0000 |
| commit | c7c49c90b776f9bc21d0e80515fd7df302fbc60f (patch) | |
| tree | 49ffcd1e1e21af563a48df01f3e147912fcb64a1 /model | |
| parent | fc89f3e2eebae198cf4ebe6965e9b4080de9630c (diff) | |
| download | sail-riscv-c7c49c90b776f9bc21d0e80515fd7df302fbc60f.zip sail-riscv-c7c49c90b776f9bc21d0e80515fd7df302fbc60f.tar.gz sail-riscv-c7c49c90b776f9bc21d0e80515fd7df302fbc60f.tar.bz2 | |
Add a -v rvfi flag to add RVFI debug logging
Diffstat (limited to 'model')
| -rw-r--r-- | model/rvfi_dii.sail | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/model/rvfi_dii.sail b/model/rvfi_dii.sail index 902f1f8..9d21645 100644 --- a/model/rvfi_dii.sail +++ b/model/rvfi_dii.sail @@ -33,8 +33,8 @@ val print_instr_packet : bits(64) -> unit function print_instr_packet(bs) = { let p = Mk_RVFI_DII_Instruction_Packet(bs); - print_bits("command", p.rvfi_cmd()); - print_bits("instruction", p.rvfi_insn()) + print_bits("command ", p.rvfi_cmd()); + print_bits("instruction ", p.rvfi_insn()) } bitfield RVFI_DII_Execution_Packet_V1 : bits(704) = { @@ -255,7 +255,7 @@ val rvfi_get_exec_packet_v2 : unit -> bits(448 + 256 + 256) effect {rreg} function rvfi_get_exec_packet_v2 () = { // TODO: add the other data - // TODO: find a way to return a variable-legnth bitvector + // TODO: find a way to return a variable-length bitvector let packet = Mk_RVFI_DII_Execution_PacketV2(EXTZ(0b0)); let packet = update_trace_version(packet, EXTZ(0x2)); let packet = update_basic_data(packet, rvfi_inst_data.bits()); |