aboutsummaryrefslogtreecommitdiff
path: root/model/riscv_sys_regs.sail
AgeCommit message (Expand)AuthorFilesLines
2024-05-07fixup! Add Svinval extension.Martin Berger1-0/+4
2024-04-24Add read-only CSR MCONFIGPTRAlasdair1-0/+1
2024-04-15Implement Zcb extensionTim Hutt1-0/+5
2024-04-14Fix compiler warnings in vextVed Shanbhogue1-7/+9
2024-04-03Fix flen=32 compilationTim Hutt1-1/+1
2024-03-25Fix MEnvCall valueTim Hutt1-1/+1
2024-03-24Fix error in senvcfg definitionVed Shanbhogue1-7/+25
2024-02-08Shorten copyright notice at the top of each fileTim Hutt1-65/+3
2024-02-05Improve PMP supportTim Hutt1-0/+7
2024-01-31Update bitfield update syntaxAlasdair1-89/+69
2024-01-31Update bitfield syntaxAlasdair1-103/+103
2023-12-06Remove effect annotations from vector extensionAlasdair1-6/+6
2023-10-17RISC-V Vector Extension SupportXinlai Wan1-3/+95
2023-10-11Rename enable-fiom to enable-writable-fiomTim Hutt1-2/+2
2023-10-11Implement menvcfgTim Hutt1-0/+45
2023-09-26Per section 3.1.1 of the Privileged Spec (Machine ISA Register misa): F/D bot...ahadali50001-3/+3
2023-09-12Remove effectsTim Hutt1-1/+1
2023-08-28If C cannot be disabled, all changes to misa must be suppressedahadali50001-15/+12
2023-08-01Rename EXTZ and EXTSAlasdair1-9/+9
2023-05-29apply_headers: regenerate copyright headersupdate-copyright-headersPhilipp Tomsich1-1/+2
2023-05-29coding style: fix style issues from merge of PR #257Philipp Tomsich1-3/+2
2023-05-29Add Zfa extension support (excl. quad-precision)Philipp Tomsich1-0/+3
2023-05-29Fix minstret off-by-one when mcountinhibit is setTim Hutt1-8/+8
2023-05-29Add support for the Zicond extensionPhilipp Tomsich1-1/+5
2023-04-10Check for mstatus.FS when performing half-precision loads/storesAlex Richardson1-3/+2
2023-03-14Use not() instead of ~() for boolean negation (#210)Alexander Richardson1-4/+4
2023-03-06Add wildcard cases to matches to suppress Sail warnings. (#197)Robert Norton1-1/+1
2023-02-14Revert "added 3 new command line switches (plus functionality): -X/--enable-...Jessica Clarke1-6/+0
2023-02-13added 3 new command line switches (plus functionality): -X/--enable-experime...Bill McSpadden1-0/+6
2022-07-13Add support for Zhinx extension (#153)Bilal Sakhawat1-1/+2
2022-01-21Add support for Scalar Cryptography Zbkb, Zbkc and Zbkx Extensions (#135)Bilal Sakhawat1-1/+6
2022-01-19Add support for Zfh extension (#129)Bilal Sakhawat1-0/+3
2022-01-19Add support for Zmmul (#122)Bilal Sakhawat1-0/+2
2021-12-05Support BitManip Zba, Zbb, Zbc and Zbs extensions (#116)Bilal Sakhawat1-0/+6
2021-11-22Implement support for Zfinx (#130)Jessica Clarke1-3/+11
2021-11-17Revert "Initial introduction of zfinx (#75)"Jessica Clarke1-6/+3
2021-11-17Initial introduction of zfinx (#75)Ibrahim Abu Kharmeh1-3/+6
2021-10-18scalar-crypto: Initial commit of 1.0.0-rc2 spec work. (#99)Ben Marshall1-0/+63
2021-07-29Use headache to apply copyright header at request of Peter Sewell.Robert Norton1-0/+68
2021-06-29effectivePrivilege: don't consult globalsNathaniel Wesley Filardo1-2/+2
2021-02-11Make N extension configurable.Prashanth Mundkur1-0/+2
2021-01-26Prevent CSRW to sstatus from modifying uie & upie if N-ext not presentScott Johnson1-1/+1
2020-11-30Ignore undefined bits in mstatus on writeAlex Richardson1-1/+6
2020-11-17Bug fix: when writing CSR sip, ignore attempt to change undelegated SSIPScott Johnson1-1/+1
2020-09-03Add the mstatush CSR for RV32, and hardwire the MBE and SBE fields to 0.Prashanth Mundkur1-0/+17
2020-08-25Implement mcountinhibit IR bit to squash minstret incrementScott Johnson1-1/+2
2020-05-22Prevent access to N-mode registers and mstatus/mip/mie bits when N-mode is di...Prashanth Mundkur1-4/+8
2020-04-27Clear mstatus.mprv on mret and sret, and hardwire it to 0 when user-mode is n...Prashanth Mundkur1-1/+2
2020-04-27Add the mcountinhibit register.Prashanth Mundkur1-0/+13
2020-04-27Handle writes to misa.{F,D}.Prashanth Mundkur1-3/+8
generated by cgit v1.1 at 2024-08-04 13:16:57 +0000