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| author | Tim Hutt <timothy.hutt@codasip.com> | 2024-02-02 11:56:55 +0000 |
|---|---|---|
| committer | Bill McSpadden <bill@riscv.org> | 2024-02-05 11:22:09 -0600 |
| commit | 4de2bff12d967d91dd064e4a49e25ca4785f25e3 (patch) | |
| tree | b106b03932811b9f35c4ac025a89c6f47862dc8f /model/riscv_sys_regs.sail | |
| parent | d5e89a71e3a84495c1b88a7749c25fd6b9da684b (diff) | |
| download | sail-riscv-4de2bff12d967d91dd064e4a49e25ca4785f25e3.zip sail-riscv-4de2bff12d967d91dd064e4a49e25ca4785f25e3.tar.gz sail-riscv-4de2bff12d967d91dd064e4a49e25ca4785f25e3.tar.bz2 | |
Improve PMP support
This implements a lot of missing functionality for PMPs.
* Support 64 PMPs as well as 0 and 16.
* Support setting PMP grain
* Return correct address bits on read (some read as 0 or 1 depending on the grain and match type)
* Unlock PMPs on reset
* Implement pmpcfg WARL legalisation
Co-authored-by: Ben Fletcher <benjamin.fletcher@codasip.com>
Diffstat (limited to 'model/riscv_sys_regs.sail')
| -rw-r--r-- | model/riscv_sys_regs.sail | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail index fac0c97..c98584b 100644 --- a/model/riscv_sys_regs.sail +++ b/model/riscv_sys_regs.sail @@ -153,6 +153,13 @@ val sys_enable_next = {c: "sys_enable_next", ocaml: "Platform.enable_next", _: " /* Whether FIOM bit of menvcfg/senvcfg is enabled. It must be enabled if supervisor mode is implemented and non-bare addressing modes are supported. */ val sys_enable_writable_fiom = {c: "sys_enable_writable_fiom", ocaml: "Platform.enable_writable_fiom", _: "sys_enable_writable_fiom"} : unit -> bool + +/* How many PMP entries are implemented. This must be 0, 16 or 64 (this is checked at runtime). */ +val sys_pmp_count = {c: "sys_pmp_count", ocaml: "Platform.pmp_count", _: "sys_pmp_count"} : unit -> range(0, 64) +/* G parameter that specifies the PMP grain size. The grain size is 2^(G+2), e.g. + G=0 -> 4 bytes, G=10 -> 4096 bytes. */ +val sys_pmp_grain = {c: "sys_pmp_grain", ocaml: "Platform.pmp_grain", _: "sys_pmp_grain"} : unit -> range(0, 63) + /* whether misa.v was enabled at boot */ val sys_enable_vext = {c: "sys_enable_vext", ocaml: "Platform.enable_vext", _: "sys_enable_vext"} : unit -> bool |