diff options
| author | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2021-01-06 19:56:40 -0800 |
|---|---|---|
| committer | Prashanth Mundkur <prashanth.mundkur@gmail.com> | 2021-02-11 19:14:19 -0800 |
| commit | 99be0960a2d1027b0ace9dbe066bf38bb16b9b97 (patch) | |
| tree | 6470b5179823c797629bae2f65f5a9d60cbc83f0 /model/riscv_sys_regs.sail | |
| parent | 33cacbd88289bf0503b07433ee0c2923e32ef946 (diff) | |
| download | sail-riscv-99be0960a2d1027b0ace9dbe066bf38bb16b9b97.zip sail-riscv-99be0960a2d1027b0ace9dbe066bf38bb16b9b97.tar.gz sail-riscv-99be0960a2d1027b0ace9dbe066bf38bb16b9b97.tar.bz2 | |
Make N extension configurable.
Diffstat (limited to 'model/riscv_sys_regs.sail')
| -rw-r--r-- | model/riscv_sys_regs.sail | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/model/riscv_sys_regs.sail b/model/riscv_sys_regs.sail index 1601aea..714f3c9 100644 --- a/model/riscv_sys_regs.sail +++ b/model/riscv_sys_regs.sail @@ -76,6 +76,8 @@ val sys_enable_writable_misa = {c: "sys_enable_writable_misa", ocaml: "Platform. val sys_enable_rvc = {c: "sys_enable_rvc", ocaml: "Platform.enable_rvc", _: "sys_enable_rvc"} : unit -> bool /* whether misa.{f,d} were enabled at boot */ val sys_enable_fdext = {c: "sys_enable_fdext", ocaml: "Platform.enable_fdext", _: "sys_enable_fdext"} : unit -> bool +/* whether the N extension was enabled at boot */ +val sys_enable_next = {c: "sys_enable_next", ocaml: "Platform.enable_next", _: "sys_enable_next"} : unit -> bool /* This function allows an extension to veto a write to Misa if it would violate an alignment restriction on |