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AgeCommit message (Expand)AuthorFilesLines
2019-01-25More cleanup.Tim Newsome5-47/+8
2019-01-25Remove debug statements.Tim Newsome5-50/+6
2019-01-25Merge branch 'riscv' into hwthreadTim Newsome4-137/+245
2019-01-25Invalidate register cache on reset.Tim Newsome1-1/+3
2019-01-25Properly clean up SMP watchpoints.Tim Newsome1-4/+26
2019-01-24WIP on hardware breakpoints.Tim Newsome8-61/+207
2019-01-22Move version check until after dmactive=1.Tim Newsome1-10/+10
2019-01-18Halt all SMP harts on halt request.Tim Newsome1-8/+20
2019-01-18Don't reset current thread id on single step.Tim Newsome1-13/+20
2019-01-17Fix reading of non-general registers for hwthreadTim Newsome8-12/+102
2019-01-11rtos support to write registers on current threadTim Newsome4-61/+93
2019-01-10Clean up register caching a little.Tim Newsome2-19/+29
2019-01-09Add 'riscv set_ir' command to set IR value for JTAG registers.Darius Rad3-16/+38
2019-01-08Add comment for reset_delays_wait.Tim Newsome4-34/+18
2019-01-07Make riscv_get_gdb_reg_list read the registers.Tim Newsome1-0/+13
2019-01-07Clean up debug printf.Tim Newsome1-2/+2
2019-01-07Handler target_get_gdb_reg_list() better.Tim Newsome1-0/+1
2019-01-07Implement hwthread_get_thread_reg_list.Tim Newsome1-4/+22
2019-01-03WIP make riscv work with -rtos hwthread.Tim Newsome1-2/+23
2019-01-03Neuter hwthread_get_thread_reg_list so it buildsTim Newsome1-66/+6
2019-01-02rtos/hwthread: add hardware-thread pseudo rtosMatthias Welwarsky3-0/+397
2019-01-02Fix typo.Tim Newsome1-1/+1
2018-12-13Fix block read corner cases.Tim Newsome1-43/+33
2018-12-04Add `riscv reset_delays` for testing.Tim Newsome4-2/+83
2018-12-03Deal with DMI busy in block reads/writes.Tim Newsome1-79/+110
2018-11-29Add idle count to debug output. (#337)Tim Newsome2-17/+33
2018-11-19From upstream (#331)Tim Newsome65-1594/+6510
2018-11-12Fix memory leaks. (#328)Tim Newsome1-4/+10
2018-11-12examine() should leave halted harts halted (#327)Tim Newsome1-6/+5
2018-11-07Doxygen style, too. (#325)Tim Newsome2-3/+3
2018-11-06Clean up fespi flashing code (#313)v20181030Tim Newsome1-260/+109
2018-11-05Remove unused extern declaration. (#324)Greg Savin1-3/+0
2018-11-05Support for two-wire cJTAG OSCAN1 signaling thru FTDI devices with appropriat...Greg Savin2-10/+354
2018-11-05Conform to OpenOCD style. (#323)Tim Newsome1-1/+1
2018-11-05Install patchutils for the build. (#321)Tim Newsome1-3/+2
2018-11-05Complete single step before returning. (#319)Tim Newsome1-1/+1
2018-11-05FIX(src/target/riscv/riscv.c): riscv_add_breakpoint: RVC: invalid 32bit trans...Pavel S. Smirnov1-10/+19
2018-11-02Fix 0.11 memory leak. (#318)Tim Newsome1-3/+3
2018-10-30Old fixes from June (#311)Carsten Gosvig4-36/+63
2018-10-24Revert "Don't report exact watchpoint to gdb. (#300)" (#304)Tim Newsome1-5/+1
2018-10-19Merge pull request #308 from riscv/eclipse_memory_readCarsten Gosvig2-45/+82
2018-10-19Moved comment and added initial buffer clearingv20180928eclipse_memory_readcgsfv1-3/+5
2018-10-18dmi_scan() allocate bytes depending on abits value (#307)Tim Newsome1-3/+7
2018-10-18Fix segfault in riscv_deinit_target(). (#306)Tim Newsome1-6/+11
2018-09-17Corrected wrong C syntaxcgsfv1-1/+1
2018-09-17Use LOG_DEBUG for debug messages: Discard unexpected charcgsfv1-1/+1
2018-09-17Read memory words individually if burst read failscgsfv1-44/+79
2018-09-17Update mpsse.cmpsse_flushMegan Wachs1-0/+1
2018-09-12Add wall clock timeout to mpsse_flush()Tim Newsome1-0/+6
2018-09-06Don't report exact watchpoint to gdb. (#300)Tim Newsome1-1/+5
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