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author | Tim Newsome <tim@sifive.com> | 2019-01-08 13:40:56 -0800 |
---|---|---|
committer | Tim Newsome <tim@sifive.com> | 2019-01-08 14:01:25 -0800 |
commit | e6b6aa615b0ec4da3251fd9fe1058f4294a5f324 (patch) | |
tree | 946d4e6499732802bfb7ebeb260573722bb8e40c /src | |
parent | ccc093ab821f45832771f32b6abdfccc604a7ee2 (diff) | |
download | riscv-openocd-e6b6aa615b0ec4da3251fd9fe1058f4294a5f324.zip riscv-openocd-e6b6aa615b0ec4da3251fd9fe1058f4294a5f324.tar.gz riscv-openocd-e6b6aa615b0ec4da3251fd9fe1058f4294a5f324.tar.bz2 |
Add comment for reset_delays_wait.
Also refactor so there's just one of them in riscv, instead of one for
0.11 and one for 0.13.
Change-Id: I0dbbf112b4c57f76bed971a22dadf844fa27cd4e
Diffstat (limited to 'src')
-rw-r--r-- | src/target/riscv/riscv-011.c | 17 | ||||
-rw-r--r-- | src/target/riscv/riscv-013.c | 24 | ||||
-rw-r--r-- | src/target/riscv/riscv.c | 3 | ||||
-rw-r--r-- | src/target/riscv/riscv.h | 8 |
4 files changed, 18 insertions, 34 deletions
diff --git a/src/target/riscv/riscv-011.c b/src/target/riscv/riscv-011.c index 1de72b1..eded862 100644 --- a/src/target/riscv/riscv-011.c +++ b/src/target/riscv/riscv-011.c @@ -206,8 +206,6 @@ typedef struct { bool need_strict_step; bool never_halted; - - int reset_delays_wait; } riscv011_info_t; typedef struct { @@ -360,10 +358,11 @@ static void add_dbus_scan(const struct target *target, struct scan_field *field, uint16_t address, uint64_t data) { riscv011_info_t *info = get_info(target); + RISCV_INFO(r); - if (info->reset_delays_wait >= 0) { - info->reset_delays_wait--; - if (info->reset_delays_wait < 0) { + if (r->reset_delays_wait >= 0) { + r->reset_delays_wait--; + if (r->reset_delays_wait < 0) { info->dbus_busy_delay = 0; info->interrupt_high_delay = 0; } @@ -1385,13 +1384,6 @@ static int halt(struct target *target) return ERROR_OK; } -static int reset_delays(struct target *target, int wait) -{ - riscv011_info_t *info = get_info(target); - info->reset_delays_wait = wait; - return ERROR_OK; -} - static int init_target(struct command_context *cmd_ctx, struct target *target) { @@ -1399,7 +1391,6 @@ static int init_target(struct command_context *cmd_ctx, riscv_info_t *generic_info = (riscv_info_t *) target->arch_info; generic_info->get_register = get_register; generic_info->set_register = set_register; - generic_info->reset_delays = &reset_delays; generic_info->version_specific = calloc(1, sizeof(riscv011_info_t)); if (!generic_info->version_specific) diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 36ec839..87f3846 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -215,8 +215,6 @@ typedef struct { /* DM that provides access to this target. */ dm013_info_t *dm; - - int reset_delays_wait; } riscv013_info_t; LIST_HEAD(dm_list); @@ -460,6 +458,7 @@ static dmi_status_t dmi_scan(struct target *target, uint32_t *address_in, bool exec) { riscv013_info_t *info = get_info(target); + RISCV_INFO(r); unsigned num_bits = info->abits + DTM_DMI_OP_LENGTH + DTM_DMI_DATA_LENGTH; size_t num_bytes = (num_bits + 7) / 8; uint8_t in[num_bytes]; @@ -470,9 +469,9 @@ static dmi_status_t dmi_scan(struct target *target, uint32_t *address_in, .in_value = in }; - if (info->reset_delays_wait >= 0) { - info->reset_delays_wait--; - if (info->reset_delays_wait < 0) { + if (r->reset_delays_wait >= 0) { + r->reset_delays_wait--; + if (r->reset_delays_wait < 0) { info->dmi_busy_delay = 0; info->ac_busy_delay = 0; } @@ -1615,13 +1614,6 @@ int riscv013_authdata_write(struct target *target, uint32_t value) return ERROR_OK; } -static int reset_delays(struct target *target, int wait) -{ - riscv013_info_t *info = get_info(target); - info->reset_delays_wait = wait; - return ERROR_OK; -} - static int init_target(struct command_context *cmd_ctx, struct target *target) { @@ -1652,7 +1644,6 @@ static int init_target(struct command_context *cmd_ctx, generic_info->dmi_write = &dmi_write; generic_info->test_sba_config_reg = &riscv013_test_sba_config_reg; generic_info->test_compliance = &riscv013_test_compliance; - generic_info->reset_delays = &reset_delays; generic_info->version_specific = calloc(1, sizeof(riscv013_info_t)); if (!generic_info->version_specific) return ERROR_FAIL; @@ -2117,9 +2108,10 @@ static int read_memory_bus_v1(struct target *target, target_addr_t address, static int batch_run(const struct target *target, struct riscv_batch *batch) { RISCV013_INFO(info); - if (info->reset_delays_wait >= 0) { - info->reset_delays_wait -= batch->used_scans; - if (info->reset_delays_wait <= 0) { + RISCV_INFO(r); + if (r->reset_delays_wait >= 0) { + r->reset_delays_wait -= batch->used_scans; + if (r->reset_delays_wait <= 0) { batch->idle_count = 0; info->dmi_busy_delay = 0; info->ac_busy_delay = 0; diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index fc7f777..ee576b9 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -1622,7 +1622,8 @@ COMMAND_HANDLER(riscv_reset_delays) struct target *target = get_current_target(CMD_CTX); RISCV_INFO(r); - return r->reset_delays(target, wait); + r->reset_delays_wait = wait; + return ERROR_OK; } static const struct command_registration riscv_exec_command_handlers[] = { diff --git a/src/target/riscv/riscv.h b/src/target/riscv/riscv.h index 82c1916..4b6ab8c 100644 --- a/src/target/riscv/riscv.h +++ b/src/target/riscv/riscv.h @@ -96,6 +96,10 @@ typedef struct { bool triggers_enumerated; + /* Decremented every scan, and when it reaches 0 we clear the learned + * delays, causing them to be relearned. Used for testing. */ + int reset_delays_wait; + /* Helper functions that target the various RISC-V debug spec * implementations. */ int (*get_register)(struct target *target, @@ -130,10 +134,6 @@ typedef struct { uint32_t num_words, target_addr_t illegal_address, bool run_sbbusyerror_test); int (*test_compliance)(struct target *target); - - /* After wait scans, reset the number of Run-Test/Idle cycles we've learned - * are required. */ - int (*reset_delays)(struct target *target, int wait); } riscv_info_t; /* Wall-clock timeout for a command/access. Settable via RISC-V Target commands.*/ |