riscv-openocd.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2019-01-25	More cleanup.	Tim Newsome	5	-47/+8
2019-01-25	Remove debug statements.	Tim Newsome	5	-50/+6
2019-01-25	Merge branch 'riscv' into hwthread	Tim Newsome	5	-137/+256
2019-01-25	Invalidate register cache on reset.	Tim Newsome	1	-1/+3
2019-01-25	Properly clean up SMP watchpoints.	Tim Newsome	1	-4/+26
2019-01-24	WIP on hardware breakpoints.	Tim Newsome	8	-61/+207
2019-01-24	Merge pull request #346 from riscv/dmactive	Tim Newsome	1	-10/+10
2019-01-22	Move version check until after dmactive=1.	Tim Newsome	1	-10/+10
2019-01-18	Halt all SMP harts on halt request.	Tim Newsome	1	-8/+20
2019-01-18	Don't reset current thread id on single step.	Tim Newsome	1	-13/+20
2019-01-17	Fix reading of non-general registers for hwthread	Tim Newsome	8	-12/+102
2019-01-11	rtos support to write registers on current thread	Tim Newsome	4	-61/+93
2019-01-11	Merge pull request #345 from darius-bluespec/set_ir	Tim Newsome	4	-16/+49
2019-01-10	Clean up register caching a little.	Tim Newsome	2	-19/+29
2019-01-09	Add 'riscv set_ir' command to set IR value for JTAG registers.	Darius Rad	4	-16/+49
2019-01-09	Merge pull request #344 from riscv/idle	Tim Newsome	4	-111/+197
2019-01-08	Add comment for reset_delays_wait.	Tim Newsome	4	-34/+18
2019-01-07	Make riscv_get_gdb_reg_list read the registers.	Tim Newsome	1	-0/+13
2019-01-07	Clean up debug printf.	Tim Newsome	1	-2/+2
2019-01-07	Handler target_get_gdb_reg_list() better.	Tim Newsome	1	-0/+1
2019-01-07	Implement hwthread_get_thread_reg_list.	Tim Newsome	1	-4/+22
2019-01-03	WIP make riscv work with -rtos hwthread.	Tim Newsome	1	-2/+23
2019-01-03	Neuter hwthread_get_thread_reg_list so it builds	Tim Newsome	1	-66/+6
2019-01-02	rtos/hwthread: add hardware-thread pseudo rtos	Matthias Welwarsky	4	-51/+464
2019-01-02	Fix typo.	Tim Newsome	1	-1/+1
2018-12-31	Merge pull request #335 from aka-sps/merge-master-to-riscv	Tim Newsome	0	-0/+0
2018-12-13	Fix block read corner cases.	Tim Newsome	1	-43/+33
2018-12-04	Add `riscv reset_delays` for testing.	Tim Newsome	4	-2/+83
2018-12-03	Deal with DMI busy in block reads/writes.	Tim Newsome	1	-79/+110
2018-12-03	Document how to get code coverage. (#339)v2018.12.0	Tim Newsome	1	-0/+26
2018-11-29	Add idle count to debug output. (#337)	Tim Newsome	2	-17/+33
2018-11-26	Merge master into riscv-sc	Pavel S. Smirnov	0	-0/+0
2018-11-21	Document FESPI driver. (#334)	Tim Newsome	2	-5/+16
2018-11-19	From upstream (#331)	Tim Newsome	89	-1613/+7219
2018-11-13	Permit null target on TCL connection	Christopher Head	3	-4/+10
2018-11-12	Fix memory leaks. (#328)	Tim Newsome	1	-4/+10
2018-11-12	examine() should leave halted harts halted (#327)	Tim Newsome	1	-6/+5
2018-11-12	Add utility to combine runs of lines in log files. (#317)	Tim Newsome	1	-0/+119
2018-11-10	README: fix stlink instructions	Paul Fertser	1	-1/+1
2018-11-10	docs: fix typo in manual	Spencer Oliver	1	-1/+1
2018-11-10	target/stm32h7x: Fix documentation of reset_config	Christopher Head	1	-1/+11
2018-11-10	jtag/bitq: array boundary overflow	xuguangxiao	1	-1/+1
2018-11-08	armv7a: ARMv7-A MMU tools	Matthias Welwarsky	7	-171/+497
2018-11-07	Doxygen style, too. (#325)	Tim Newsome	2	-3/+3
2018-11-06	Clean up fespi flashing code (#313)v20181030	Tim Newsome	4	-260/+251
2018-11-06	target/cortex_a: remove duplicate code to read target registers	Antonio Borneo	3	-160/+9
2018-11-06	target/arm_dpm: uniform names of exported functions	Antonio Borneo	3	-16/+16
2018-11-06	target/cortex_a: remove buggy memory AP accesses	Antonio Borneo	2	-142/+10
2018-11-06	target/cortex_a: remove unused code controlled by "fast_reg_read"	Antonio Borneo	2	-84/+6
2018-11-05	Remove unused extern declaration. (#324)	Greg Savin	1	-3/+0