Invalidate register cache on reset.

All tests pass with `-rtos hwthread` against spike32!

Change-Id: I9051259d2702c76b7c35aeffeac020a773e0597a

1 files changed, 3 insertions, 1 deletions

diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index aa871e9..d05b9c7 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -867,13 +867,15 @@ static int old_or_new_riscv_halt(struct target *target)
 
 static int riscv_assert_reset(struct target *target)
 {
+	LOG_DEBUG("[%d]", target->coreid);
 	struct target_type *tt = get_target_type(target);
+	riscv_invalidate_register_cache(target);
 	return tt->assert_reset(target);
 }
 
 static int riscv_deassert_reset(struct target *target)
 {
-	LOG_DEBUG("RISCV DEASSERT RESET");
+	LOG_DEBUG("[%d]", target->coreid);
 	struct target_type *tt = get_target_type(target);
 	return tt->deassert_reset(target);
 }