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https://github.com/incoresemi/riscv-opcodes into incoresemi-migration-to-new-format
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* add spinalhdl support
Signed-off-by: ncer <huangzzk@bupt.edu.cn>
* restruct chisel and spinalhdl parser
Signed-off-by: ncer <huangzzk@bupt.edu.cn>
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- the python file is well commented
- the README provides a brief overview of how the python script works and the various artifacts it can generate
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The parse-opcodes script already contains `#!/usr/bin/env python3`
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Similar to 2497a8cc Clean up handling of bitmanip extensions
cc @ben-marshall
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There's no such thing as "B", which continues to be a source of
confusion. Time to fix that.
cc @ben-marshall since I added Zbkb/Zbkx.
Resolves #101
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Instead of making (and depending on) multiple header files in external
repositories, this commit makes single intermediate file and copies it
to external directories on install.
This will...
* Reduce CPU time (only slightly, though).
* Enable making header file *without* cloning and destroying
external repositories (`make encoding.out.h`).
* Ensure that latest encoding.h is generated and copied on install,
even after fresh checkout on an external source tree.
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This commit adds instructions defined in RISC-V Base Cache Management
Operation ISA Extensions, version 1.0.0-rc2 (now ratified).
https://github.com/riscv/riscv-CMOs
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* Add Svinval instructions
* Add PTE defines for Priv 1.12 and Svpbmt
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- Adds opcodes for RV32 and RV64 scalar crypto.
- opcodes-rvk contains encodings which are for RV32 and RV64 base ISAs
- opcodes-rv32/64k contains encodings which are for RV32 or RV64
- parse_opcodes has been modified:
- Wnable instructions to be listed as either RV32 or RV64 only, allowing
these opcodes to overlap.
- The C backend has been modifed to emit the "DECLARE_RV32_ONLY" or
"DECLARE_RV64_ONLY" macros as needed.
- The other backends have not been modified, and may need to be in the
future.
On branch scalar-crypto
Changes to be committed:
modified: Makefile
new file: opcodes-rv32k
new file: opcodes-rv64k
new file: opcodes-rvk
modified: parse_opcodes
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The header explains where the file came from.
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This part copy the implementation which has been merged in spike
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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* (Partially) fix #30
With this change (and a renamed parse-opcodes) it's possible to as a
Python module without having to patch the repo. Example:
from parse_opcodes import parse_inputs
if __name__ == "__main__":
(namelist, pseudos, mask, match, arguments) = parse_inputs(["opcodes", "opcodes-rvc"])
* Fix #30: Rename parse-opcode to parse_opcode to enable module use
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add most of vector instruction encoding described in v-spec 0.7.
except for 'Zvamo' extension
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
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Now that binutils is upstream, we maintain that file manually.
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* Support generating Go code
Generate Go code for the RISC-V Go port
<https://github.com/riscv/riscv-go>.
* Clarify use of yank in Go backend
* Go: Also generate funct3, csr, and funct7 encodings
* Go: Emit all instructions
Changes to the RISC-V Go implementation obviate the need for
GO_UNUSED_INSTRUCTIONS.
* Go: Print CSRs as signed values
* Go: Update parse-opcodes to use obj.As
See https://github.com/golang/go/commit/0d9258a830c585.
* Go: Return errors out of band
* Go: Return 'ok' status instead of 'err' status
Also clean up imports.
* Go: Make gofmt-clean
* Go: Return rs2 value for each instructions
Some binary floating-point instructions (ab)use the rs2 value to hold
additional instruction data, so we need that data in the Go assembler.
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It's upstreamed, so avoid the false impression it can easily change.
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This reverts commit fe5742618c1732be6000cccfbed3432596dea9e4.
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