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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-07-14 23:19:39 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-07-31 10:07:27 -0700 |
| commit | 7231f5a8582019ca5eb0037ba05ceed8c44f35a8 (patch) | |
| tree | 973b77c507e337b43cfb71e056265de02c10b742 /Makefile | |
| parent | 75f44b5b949922813b7ab971d5ececf863592b0a (diff) | |
| download | riscv-opcodes-7231f5a8582019ca5eb0037ba05ceed8c44f35a8.zip riscv-opcodes-7231f5a8582019ca5eb0037ba05ceed8c44f35a8.tar.gz riscv-opcodes-7231f5a8582019ca5eb0037ba05ceed8c44f35a8.tar.bz2 | |
hyperviosr: add csr mask and interrupt macro name
This part copy the implementation which has been merged in spike
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -5,7 +5,7 @@ PK_H := ../riscv-pk/machine/encoding.h ENV_H := ../riscv-tests/env/encoding.h OPENOCD_H := ../riscv-openocd/src/target/riscv/encoding.h -ALL_REAL_ILEN32_OPCODES := opcodes-rv32i opcodes-rv64i opcodes-rv32m opcodes-rv64m opcodes-rv32a opcodes-rv64a opcodes-rv32f opcodes-rv64f opcodes-rv32d opcodes-rv64d opcodes-rv32q opcodes-rv64q opcodes-system +ALL_REAL_ILEN32_OPCODES := opcodes-rv32i opcodes-rv64i opcodes-rv32m opcodes-rv64m opcodes-rv32a opcodes-rv64a opcodes-rv32h opcodes-rv64h opcodes-rv32f opcodes-rv64f opcodes-rv32d opcodes-rv64d opcodes-rv32q opcodes-rv64q opcodes-system ALL_REAL_OPCODES := $(ALL_REAL_ILEN32_OPCODES) opcodes-rvc opcodes-rv32c opcodes-rv64c opcodes-custom opcodes-rvv ALL_OPCODES := opcodes-pseudo $(ALL_REAL_OPCODES) opcodes-rvv-pseudo |