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| author | Andrew Waterman <andrew@sifive.com> | 2020-03-03 18:44:45 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-03-03 18:44:45 -0800 |
| commit | 0ce3ec1f7d82d5449ba5d00302270076f6cc34f6 (patch) | |
| tree | 1189f43367842a03c24e6d4f47312863f3431b8f /Makefile | |
| parent | c7e17632237219090791ba67dd700c2fca432e20 (diff) | |
| download | riscv-opcodes-0ce3ec1f7d82d5449ba5d00302270076f6cc34f6.zip riscv-opcodes-0ce3ec1f7d82d5449ba5d00302270076f6cc34f6.tar.gz riscv-opcodes-0ce3ec1f7d82d5449ba5d00302270076f6cc34f6.tar.bz2 | |
Factor out RVC opcodes into per-extension files
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 6 |
1 files changed, 3 insertions, 3 deletions
@@ -6,11 +6,11 @@ ENV_H := ../riscv-tests/env/encoding.h OPENOCD_H := ../riscv-openocd/src/target/riscv/encoding.h ALL_REAL_ILEN32_OPCODES := opcodes-rv32i opcodes-rv64i opcodes-rv32m opcodes-rv64m opcodes-rv32a opcodes-rv64a opcodes-rv32f opcodes-rv64f opcodes-rv32d opcodes-rv64d opcodes-rv32q opcodes-rv64q opcodes-rv128q opcodes-system -ALL_REAL_OPCODES := $(ALL_REAL_ILEN32_OPCODES) opcodes-rvc opcodes-custom opcodes-rvv +ALL_REAL_OPCODES := $(ALL_REAL_ILEN32_OPCODES) opcodes-rvc opcodes-rv32c opcodes-rv64c opcodes-rv128c opcodes-custom opcodes-rvv -ALL_OPCODES := opcodes-pseudo $(ALL_REAL_OPCODES) opcodes-rvc-pseudo opcodes-rvv-pseudo +ALL_OPCODES := opcodes-pseudo $(ALL_REAL_OPCODES) opcodes-rvv-pseudo -install: $(ISASIM_H) inst.chisel instr-table.tex priv-instr-table.tex +install: $(ISASIM_H) $(PK_H) $(ENV_H) $(OPENOCD_H) inst.chisel instr-table.tex priv-instr-table.tex $(ISASIM_H) $(PK_H) $(ENV_H) $(OPENOCD_H): $(ALL_OPCODES) parse_opcodes encoding.h cp encoding.h $@ |