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| author | Florian Zaruba <zarubaf@iis.ee.ethz.ch> | 2019-02-11 19:41:39 +0100 |
|---|---|---|
| committer | Andrew Waterman <aswaterman@gmail.com> | 2019-02-11 10:41:39 -0800 |
| commit | a2f7cf2080b3809de1141b9652c3dce341053e2a (patch) | |
| tree | 835b06a09d20b9bf0023c8c6723b3ac43e2abc4e /Makefile | |
| parent | ec25bc8728fcdc3e960213ff85773efd61673aa8 (diff) | |
| download | riscv-opcodes-a2f7cf2080b3809de1141b9652c3dce341053e2a.zip riscv-opcodes-a2f7cf2080b3809de1141b9652c3dce341053e2a.tar.gz riscv-opcodes-a2f7cf2080b3809de1141b9652c3dce341053e2a.tar.bz2 | |
Add SystemVerilog generation (#24)
Diffstat (limited to 'Makefile')
| -rw-r--r-- | Makefile | 3 |
1 files changed, 3 insertions, 0 deletions
@@ -20,6 +20,9 @@ inst.chisel: $(ALL_OPCODES) parse-opcodes inst.go: opcodes opcodes-pseudo parse-opcodes cat opcodes opcodes-pseudo | ./parse-opcodes -go > $@ +inst.sverilog: opcodes opcodes-pseudo parse-opcodes + cat opcodes opcodes-rvc opcodes-rvc-pseudo opcodes-custom opcodes-pseudo | ./parse-opcodes -sverilog > $@ + instr-table.tex: $(ALL_OPCODES) parse-opcodes cat opcodes opcodes-pseudo | ./parse-opcodes -tex > $@ |