riscv-isa-manual.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2022-07-26	Memory access traps may write zero to stval (#776)	John Hauser	1	-1/+2
2022-07-26	Accesses to pages with mismatched attrs are I/O _and_ memory wrt FENCE (#774)	Andrew Waterman	1	-6/+8
2022-07-26	Rename hstatus.HU (#770)	John Hauser	1	-1/+1
2022-07-26	Allow more bits of hideleg to be writable (#772)	John Hauser	1	-3/+4
2022-07-26	Clarify condition when virtual instruction trap will occur (#773)	John Hauser	1	-1/+1
2022-07-26	CSR mideleg masks hideleg, hip, and hie (#771)	John Hauser	1	-0/+3
2022-07-26	Rewrite most instances of "hardwire" as "read-only" (#768)	John Hauser	4	-74/+74
2022-07-26	Remove trailing whitespace from a.tex (#767)	Axel Heider	1	-1/+1
2022-07-26	Document version 20211105-signoff	Andrew Waterman	1	-2/+2
2022-07-26	Further relax PMP/address-translation caching interactions	Andrew Waterman	1	-8/+12
2022-07-26	Remove reference to consecutive-SFENCE idiom	Andrew Waterman	1	-5/+0
2022-07-26	minor grammatical and stylistic changes	Andrew Waterman	2	-9/+9
2022-07-26	Add the Svinval standard extension	Daniel Lustig	5	-10/+252
2022-07-26	Add the Svpbmt standard extension	Daniel Lustig	2	-20/+128
2022-07-26	Add the Svnapot standard extension	Daniel Lustig	2	-17/+161
2022-07-26	Add Sv57 and Sv57x4	Daniel Lustig	3	-27/+205
2022-07-26	Remove M-mode details from S-mode chapter	Andrew Waterman	1	-2/+2
2022-07-26	Various minor virtual memory clarifications	Daniel Lustig	5	-49/+255
2022-07-26	Back to draft status	Andrew Waterman	1	-1/+1
2022-07-26	Define the Zicntr and Zihpm extensions	Andrew Waterman	1	-10/+14
2022-07-26	Improve text in Zicntr section	Andrew Waterman	1	-4/+8
2022-07-26	Document version 20211028-signoff	Andrew Waterman	1	-2/+2
2022-07-26	Incorporate Steve's feedback	Andrew Waterman	1	-1/+1
2021-12-28	Add yaml file for build automation (#801)	Stephano Cetola	1	-0/+58
2021-12-28	Add dependencies for github workflow	Stephano Cetola	4	-0/+43
2021-12-20	mm-formal: table fixes	Stephano Cetola	1	-2/+4
2021-12-20	c-st-ext: add wavedrom diagrams back in	Stephano Cetola	5	-8/+70
2021-12-20	Cleanup build errors and remove generated PDF	Stephano Cetola	3	-5/+9
2021-12-20	Update Makefile to use asciidoctor build	Stephano Cetola	3	-68/+25
2021-11-23	wavedrom edits and additions	elisa	7	-80/+146
2021-11-15	fixes to memory ordering and csr diagrams	elisa	3	-12/+12
2021-11-15	Merge pull request #775 from hbrausen/convert2adoc	Elisa Sawyer	1	-7/+4
2021-11-15	Change "ordering" to "ordrng" to clean up alignment of label	Henry Brausen	1	-1/+1
2021-11-14	Tidy up whitespace	Henry Brausen	1	-1/+1
2021-11-14	Rename bitfield func3 to funct3	Henry Brausen	1	-1/+1
2021-11-14	Fix labels for bits 25 and 26, clean up wavedrom file	Henry Brausen	1	-6/+3
2021-11-05	fixes to appendices, tables and graphics	elisa	8	-158/+148
2021-11-03	appendix a diagram scaling	elisa	2	-13/+12
2021-11-02	diagram and table fixes, plus add Appendix A	elisa	22	-275/+502
2021-10-28	formatting refinements	elisa	13	-117/+175
2021-10-27	change diagram output to png for color to display	elisa	33	-122/+60
2021-10-27	Merge branch 'master' of github.com:riscv/riscv-isa-manual into convert2adoc	elisa	1	-0/+2
2021-10-25	No valid LR/SC reservation upon reset	Andrew Waterman	1	-0/+2
2021-10-22	table and diagram fixes, added some missing c diagrams	elisa	27	-85/+156
2021-10-20	table and diagram fixes	elisa	6	-15/+46
2021-10-19	table fixes	elisa	2	-13/+12
2021-10-18	updated pdf	elisa	1	-0/+0
2021-10-18	Merge pull request #755 from ved-rivos/ved-patch-4	Elisa Sawyer	1	-387/+276
2021-10-17	Fixed the instruction listing tables format.	Vedvyas Shanbhogue	1	-387/+276
2021-10-14	table fixes	elisa	2	-206/+186