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| author | Vedvyas Shanbhogue <ved@rivosinc.com> | 2021-10-17 17:34:49 -0500 |
|---|---|---|
| committer | Vedvyas Shanbhogue <ved@rivosinc.com> | 2021-10-17 17:34:49 -0500 |
| commit | 6be8360f8aaf1f87662ee94adbf16d1282d30f31 (patch) | |
| tree | f24a1e46cfc08c5bb777227386636b67fd067b83 | |
| parent | 82a4a9af3477a22f83615ca5d8d6f92e0ac55fdc (diff) | |
| download | riscv-isa-manual-6be8360f8aaf1f87662ee94adbf16d1282d30f31.zip riscv-isa-manual-6be8360f8aaf1f87662ee94adbf16d1282d30f31.tar.gz riscv-isa-manual-6be8360f8aaf1f87662ee94adbf16d1282d30f31.tar.bz2 | |
Fixed the instruction listing tables format.
| -rw-r--r-- | src/rv-32-64g.adoc | 663 |
1 files changed, 276 insertions, 387 deletions
diff --git a/src/rv-32-64g.adoc b/src/rv-32-64g.adoc index 3f1fd35..a77ae78 100644 --- a/src/rv-32-64g.adoc +++ b/src/rv-32-64g.adoc @@ -9,21 +9,17 @@ for the IMAFDZicsr_Zifencei combination of instruction-set extensions. This chapter presents opcode maps and instruction-set listings for RV32G and RV64G. +// note: ≥ is unicode for >= [[opcodemap]] .RISC-V base opcode map, inst[1:0]=11 -[%header,] +[cols= ">.^4m, ^.^4m, ^.^4m, ^.^4m, ^.^4m, ^.^4m, ^.^4m, ^.^6m, ^.^4m"] |=== -|inst[4:2] .2+|000 .2+|001 .2+|010 .2+|011 .2+|100 .2+|101 .2+|110 .2+|111 (latexmath:[$>32b$]) - +|inst[4:2] .2+|000 .2+|001 .2+|010 .2+|011 .2+|100 .2+|101 .2+|110 .2+|111 (>32b) |inst[6:5] - -|00 |LOAD |LOAD-FP |_custom-0_ |MISC-MEM |OP-IMM |AUIPC |OP-IMM-32 |latexmath:[$48b$] - -|01 |STORE|STORE-FP |_custom-1_ |AMO |OP |LUI |OP-32 |latexmath:[$64b$] - -|10 |MADD |MSUB |NMSUB |NMADD |OP-FP |_reserved_ |_custom-2/rv128_|latexmath:[$48b$] - -|11 |BRANCH |JALR |_reserved_ |JAL |SYSTEM |_reserved_ |_custom-3/rv128_|latexmath:[$\geq80b$] +|00 |LOAD |LOAD-FP |_custom-0_ |MISC-MEM |OP-IMM |AUIPC |OP-IMM-32 |48b +|01 |STORE |STORE-FP |_custom-1_ |AMO |OP |LUI |OP-32 |64b +|10 |MADD |MSUB |NMSUB |NMADD |OP-FP |_reserved_ |_custom-2/rv128_|48b +|11 |BRANCH |JALR |_reserved_ |JAL |SYSTEM |_reserved_ |_custom-3/rv128_|≥80b |=== <<opcodemap>> shows a map of the major opcodes for @@ -53,389 +49,282 @@ these more specialized additions. <<extensions>> has a more extensive discussion of ways to add extensions to the RISC-V ISA. -[%header,format+DSV,separator=!,] -!=== -!31 27 26 25 !24 20 !19 15 ! 14 12! 11 7!6 0 ! - -2+!funct7|rs2 !rs1 !funct3 !rd !opcode !R-type - -2+!imm[11:0] !rs1 !funct3 !rd !opcode !I-type - -!imm[11:5] !rs2 !rs1 !funct3 !imm[4:0] !opcode !S-type - -!imm[12|10:5] !rs2 !rs1 !funct3 !imm[4:1|11] !opcode !B-type - -4+!imm[31:12]!rd !opcode !U-type - -4+!imm[20|10:1|11|19:12]!rd !opcode !J-type - -7+!*RV32I Base Instruction Set* - -4+!imm[31:12] !rd !0110111 !LUI - -4+!imm[31:12] !rd !0010111 !AUIPC - -4+!imm[20|10:1|11|19:12]!rd !1101111 !JAL - -2+!imm[11:0]!rs1 !000 !rd !1100111 !JALR - -!imm[12|10:5]!rs2 !rs1 !000 !imm[4:1|11] !1100011 !BEQ - -!imm[12|10:5]!rs2 !rs1 !001 !imm[4:1|11] !1100011 !BNE - -!imm[12|10:5]!rs2 !rs1 !100 !imm[4:1|11] !1100011 !BLT - -!imm[12|10:5]!rs2 !rs1 !101 !imm[4:1|11] !1100011 !BGE - -!imm[12|10:5]!rs2 !rs1 !110 !imm[4:1|11] !1100011 !BLTU - -!imm[12|10:5]!rs2 !rs1 !111 !imm[4:1|11] !1100011 !BGEU - -2+!imm[11:0] !rs1 !000 !rd !0000011 !LB - -2+!imm[11:0] !rs1 !001 !rd !0000011 !LH - -2+!imm[11:0] !rs1 !010 !rd !0000011 !LW - -2+!imm[11:0] !rs1 !100 !rd !0000011 !LBU - -2+!imm[11:0] !rs1 !101 !rd !0000011 !LHU - -!imm[11:5] !rs2 !rs1 !000 !imm[4:0] !0100011 !SB - -!imm[11:5] !rs2 !rs1 !001 !imm[4:0] !0100011 !SH - -!imm[11:5] !rs2 !rs1 !010 !imm[4:0] !0100011 !SW - -2+!imm[11:0] !rs1 !000 !rd !0010011 !ADDI - -2+!imm[11:0] !rs1 !010 !rd !0010011 !SLTI - -2+!imm[11:0] !rs1 !011 !rd !0010011 !SLTIU - -2+!imm[11:0] !rs1 !100 !rd !0010011 !XORI - -2+!imm[11:0] !rs1 !110 !rd !0010011 !ORI - -2+!imm[11:0] !rs1 !111 !rd !0010011 !ANDI - -!0000000 !shamt !rs1 !001 !rd !0010011 !SLLI - -!0000000 !shamt !rs1 !101 !rd !0010011 !SRLI - -!0100000 !shamt !rs1 !101 !rd !0010011 !SRAI - -!0000000 !rs2 !rs1 !000 !rd !0110011 !ADD - -!0100000 !rs2 !rs1 !000 !rd !0110011 !SUB - -!0000000 !rs2 !rs1 !001 !rd !0110011 !SLL - -!0000000 !rs2 !rs1 !010 !rd !0110011 !SLT - -!0000000 !rs2 !rs1 !011 !rd !0110011 !SLTU - -!0000000 !rs2 !rs1 !100 !rd !0110011 !XOR - -!0000000!rs2 !rs1 !101 !rd !0110011 !SRL - -!0100000!rs2 !rs1 !101 !rd !0110011 !SRA - -!0000000 !rs2 !rs1 !110 !rd !0110011 !OR - -!0000000 !rs2 !rs1 !111 !rd !0110011 !AND - -!fm !pred;succ !rs1 !000 !rd !0001111 !FENCE - -!1000 !0011;0011 !00000 !000 !00000 !0001111 !FENCE.TSO - -!0000 !0001;0000 !00000 !000 !00000 !0001111 !PAUSE - -2+!000000000000 !00000 !000 !00000 !1110011 !ECALL - -2+!000000000001 !00000 !000 !00000 !1110011 !EBREAK - -!=== - -[%header,] -|=== - -|31 27 26 25|24 20|19 15|14 12|11 7|6 0 | - -|funct7 |rs2 |rs1 |funct3 |rd |opcode |R-type - -2+|imm[11:0] |rs1 |funct3 |rd |opcode |I-type - -|imm[11:5] |rs2 |rs1 |funct3 |imm[4:0] |opcode |S-type - -7+|*RV64I Base Instruction Set (in addition to RV32I)* - -2+|imm[11:0] |rs1 |110 |rd |0000011 |LWU - -2+|imm[11:0] |rs1 |011 |rd |0000011 |LD - -|imm[11:5] |rs2 |rs1 |011 |imm[4:0] |0100011 |SD - -|000000 |shamt |rs1 |001 |rd |0010011 |SLLI - -|000000 |shamt|rs1 |101 |rd |0010011 |SRLI - -|010000 |shamt |rs1 |101 |rd |0010011 |SRAI - -2+|imm[11:0] |rs1 |000 |rd |0011011 |ADDIW - -|0000000 |shamt |rs1 |001 |rd |0011011 |SLLIW - -|0000000 |shamt |rs1 |101 |rd |0011011 |SRLIW - -|0100000 |shamt |rs1 |101 |rd |0011011 |SRAIW - -|0000000 |rs2 |rs1 |000 |rd |0111011 |ADDW - -|0100000 |rs2 |rs1 |000 |rd |0111011 |SUBW - -|0000000 |rs2 |rs1 |001 |rd |0111011 |SLLW - -|0000000 |rs2 |rs1 |101 |rd |0111011 |SRLW - -|0100000 |rs2 |rs1 |101 |rd |0111011 |SRAW - -7+|*RV32/RV64 _Zifencei_ Standard Extension* - -2+|imm[11:0] |rs1 |001 |rd |0001111 |FENCE.I - -7+|*RV32/RV64 _Zicsr_ Standard Extension* - -2+|csr |rs1 |001 |rd |1110011 |CSRRW - -2+|csr |rs1 |010 |rd |1110011 |CSRRS - -2+|csr |rs1 |011 |rd |1110011 |CSRRC - -2+|csr |uimm |101 |rd |1110011 |CSRRWI - -2+|csr |uimm |110 |rd |1110011 |CSRRSI - -2+|csr |uimm |111 |rd |1110011 |CSRRCI - -7+|*RV32M Standard Extension* - -|0000001 |rs2 |rs1 |000 |rd |0110011 |MUL - -|0000001 |rs2 |rs1 |001 |rd |0110011 |MULH - -|0000001 |rs2 |rs1 |010 |rd |0110011 |MULHSU - -|0000001 |rs2 |rs1 |011 |rd |0110011 |MULHU - -|0000001 |rs2 |rs1 |100 |rd |0110011 |DIV - -|0000001 |rs2 |rs1 |101 |rd |0110011 |DIVU - -|0000001 |rs2 |rs1 |110 |rd |0110011 |REM - -|0000001 |rs2 |rs1 |111 |rd |0110011 |REMU - -7+|*RV64M Standard Extension (in addition to RV32M)* - -|0000001 |rs2 |rs1 |000 |rd |0111011 |MULW - -|0000001 |rs2 |rs1 |100 |rd |0111011 |DIVW - -|0000001 |rs2 |rs1 |101 |rd |0111011 |DIVUW - -|0000001 |rs2 |rs1 |110 |rd |0111011 |REMW - -|0000001 |rs2 |rs1 |111 |rd |0111011 |REMUW - -|=== - -[%header,] -|=== -3+|funct7 |rs2 |rs1 |funct3 |rd |opcode |R-type -9+|*RV32A Standard Extension* -|00010 |aq |rl |00000 |rs1 |010 |rd |0101111 |LR.W -|00011 |aq |rl |rs2 |rs1 |010 |rd |0101111 |SC.W -|00001 |aq |rl |rs2 |rs1 |010 |rd |0101111 |AMOSWAP.W -|00000 |aq |rl |rs2 |rs1 |010 |rd |0101111 |AMOADD.W -|00100 |aq |rl |rs2 |rs1 |010 |rd |0101111 |AMOXOR.W -|01100 |aq |rl |rs2 |rs1 |010 |rd |0101111 |AMOAND.W -|01000 |aq |rl |rs2 |rs1 |010 |rd |0101111 |AMOOR.W -|10000 |aq |rl |rs2 |rs1 |010 |rd |0101111 |AMOMIN.W -|10100 |aq |rl |rs2 |rs1 |010 |rd |0101111 |AMOMAX.W -|11000 |aq |rl |rs2 |rs1 |010 |rd |0101111 |AMOMINU.W -|11100 |aq |rl |rs2 |rs1 |010 |rd |0101111 |AMOMAXU.W -9+|*RV64A Standard Extension (in addition to RV32A)* -|00010 |aq |rl |00000 |rs1 |011 |rd |0101111 |LR.D -|00011 |aq |rl |rs2 |rs1 |011 |rd |0101111 |SC.D -|00001 |aq |rl |rs2 |rs1 |011 |rd |0101111 |AMOSWAP.D -|00000 |aq |rl |rs2 |rs1 |011 |rd |0101111 |AMOADD.D -|00100 |aq |rl |rs2 |rs1 |011 |rd |0101111 |AMOXOR.D -|01100 |aq |rl |rs2 |rs1 |011 |rd |0101111 |AMOAND.D -|01000 |aq |rl |rs2 |rs1 |011 |rd |0101111 |AMOOR.D -|10000 |aq |rl |rs2 |rs1 |011 |rd |0101111 |AMOMIN.D -|10100 |aq |rl |rs2 |rs1 |011 |rd |0101111 |AMOMAX.D -|11000 |aq |rl |rs2 |rs1 |011 |rd |0101111 |AMOMINU.D -|11100 |aq |rl |rs2 |rs1 |011 |rd |0101111 |AMOMAXU.D -|=== - -[%header,] +[cols="^2m,^2m,^2m,^2m,<2m,>3m, <4m, >4m, <4m, >4m, <4m, >4m, <4m, >4m, <6m"] |=== -2+|31 27 26 25|24 20|19 15|14 12|11 7|6 0| -2+|funct7 |rs2 |rs1 |funct3 |rd |opcode |R-type -|rs3 |funct2 |rs2 |rs1 |funct3 |rd |opcode |R4-type -3+|imm[11:0] |rs1 |funct3 |rd |opcode |I-type -2+|imm[11:5] |rs2 |rs1 |funct3 |imm[4:0] |opcode |S-type -8+|*RV32F Standard Extension* -3+|imm[11:0] |rs1 |010 |rd |0000111 |FLW -2+|imm[11:5] |rs2 |rs1 |010 |imm[4:0] |0100111 |FSW -|rs3 |00 |rs2 |rs1 |rm |rd |1000011 |FMADD.S -|rs3 |00 |rs2 |rs1 |rm |rd |1000111 |FMSUB.S -|rs3 |00 |rs2 |rs1 |rm |rd |1001011 |FNMSUB.S -|rs3 |00 |rs2 |rs1 |rm |rd |1001111 |FNMADD.S -2+|0000000|rs2 |rs1 |rm |rd |1010011 |FADD.S -2+|0000100|rs2 |rs1 |rm |rd |1010011 |FSUB.S -2+|0001000|rs2 |rs1 |rm |rd |1010011 |FMUL.S -2+|0001100|rs2 |rs1 |rm |rd |1010011 |FDIV.S -2+|0101100|00000|rs1 |rm |rd |1010011 |FSQRT.S -2+|0010000|rs2 |rs1 |000 |rd |1010011 |FSGNJ.S -2+|0010000|rs2 |rs1 |001 |rd |1010011 |FSGNJN.S -2+|0010000|rs2 |rs1 |010 |rd |1010011 |FSGNJX.S -2+|0010100|rs2 |rs1 |000 |rd |1010011 |FMIN.S -2+|0010100|rs2 |rs1 |001 |rd |1010011 |FMAX.S -2+|1100000|00000 |rs1 |rm |rd |1010011 |FCVT.W.S -2+|1100000|00001 |rs1 |rm |rd |1010011 |FCVT.WU.S -2+|1110000|00000 |rs1 |000 |rd |1010011 |FMV.X.W -2+|1010000|rs2 |rs1 |010 |rd |1010011 |FEQ.S -2+|1010000|rs2 |rs1 |001 |rd |1010011 |FLT.S -2+|1010000|rs2 |rs1 |000 |rd |1010011 |FLE.S -2+|1110000|00000 |rs1 |001 |rd |1010011 |FCLASS.S -2+|1101000|00000 |rs1 |rm |rd |1010011 |FCVT.S.W -2+|1101000 |00001 |rs1 |rm |rd |1010011 |FCVT.S.WU -2+|1111000 |00000 |rs1 |000 |rd |1010011 |FMV.W.X -8+|*RV64F Standard Extension (in addition to RV32F)* -2+|1100000|00010 |rs1 |rm |rd |1010011 |FCVT.L.S -2+|1100000|00011 |rs1 |rm |rd |1010011 |FCVT.LU.S -2+|1101000 |00010 |rs1 |rm |rd |1010011 |FCVT.S.L -2+|1101000 |00011 |rs1 |rm |rd |1010011 |FCVT.S.LU -|=== - -[%header,] -|=== -2+|31 27 26 25|24 20|19 15|14 12|11 7|6 0| -2+|funct7 |rs2 |rs1 |funct3 |rd |opcode |R-type -|rs3 |funct2 |rs2 |rs1 |funct3 |rd |opcode |R4-type -3+|imm[11:0] |rs1 |funct3 |rd |opcode |I-type -2+|imm[11:5] |rs2 |rs1 |funct3 |imm[4:0] |opcode |S-type -8+|*RV32D Standard Extension* -3+|imm[11:0] |rs1 |011 |rd |0000111 |FLD -2+|imm[11:5] |rs2 |rs1 |011 |imm[4:0] |0100111 |FSD -|rs3 |01 |rs2 |rs1 |rm |rd |1000011 |FMADD.D -|rs3 |01 |rs2 |rs1 |rm |rd |1000111 |FMSUB.D -|rs3 |01 |rs2 |rs1 |rm |rd |1001011 |FNMSUB.D -|rs3 |01 |rs2 |rs1 |rm |rd |1001111 |FNMADD.D -2+|0000001 |rs2 |rs1 |rm |rd |1010011 |FADD.D -2+|0000101 |rs2 |rs1 |rm |rd |1010011 |FSUB.D -2+|0001001 |rs2 |rs1 |rm |rd |1010011 |FMUL.D -2+|0001101 |rs2 |rs1 |rm |rd |1010011 |FDIV.D -2+|0101101 |00000 |rs1 |rm |rd |1010011 |FSQRT.D -2+|0010001 |rs2 |rs1 |000 |rd |1010011 |FSGNJ.D -2+|0010001 |rs2 |rs1 |001 |rd |1010011 |FSGNJN.D -2+|0010001 |rs2 |rs1 |010 |rd |1010011 |FSGNJX.D -2+|0010101 |rs2 |rs1 |000 |rd |1010011 |FMIN.D -2+|0010101 |rs2 |rs1 |001 |rd |1010011 |FMAX.D -2+|0100000 |00001 |rs1 |rm |rd |1010011 |FCVT.S.D -2+|0100001 |00000 |rs1 |rm |rd |1010011 |FCVT.D.S -2+|1010001 |rs2 |rs1 |010 |rd |1010011 |FEQ.D -2+|1010001 |rs2 |rs1 |001 |rd |1010011 |FLT.D -2+|1010001 |rs2 |rs1 |000 |rd |1010011 |FLE.D -2+|1110001 |00000 |rs1 |001 |rd |1010011 |FCLASS.D -2+|1100001 |00000 |rs1 |rm |rd |1010011 |FCVT.W.D -2+|1100001 |00001 |rs1 |rm |rd |1010011 |FCVT.WU.D -2+|1101001 |00000 |rs1 |rm |rd |1010011 |FCVT.D.W -2+|1101001 |00001 |rs1 |rm |rd |1010011 |FCVT.D.WU -8+|*RV64D Standard Extension (in addition to RV32D)* -2+|1100001 |00010 |rs1 |rm |rd |1010011 |FCVT.L.D -2+|1100001 |00011 |rs1 |rm |rd |1010011 |FCVT.LU.D -2+|1110001 |00000 |rs1 |000 |rd |1010011 |FMV.X.D -2+|1101001 |00010 |rs1 |rm |rd |1010011 |FCVT.D.L -2+|1101001 |00011 |rs1 |rm |rd |1010011 |FCVT.D.LU -2+|1111001 |00000 |rs1 |000 |rd |1010011 |FMV.D.X -|=== - -[%header,] -|=== -2+|31 27 26 25|24 20|19 15|14 12|11 7|6 0| -2+|funct7 |rs2 |rs1 |funct3 |rd |opcode |R-type -|rs3 |funct2 |rs2 |rs1 |funct3 |rd |opcode |R4-type -3+|imm[11:0] |rs1 |funct3 |rd |opcode |I-type -2+|imm[11:5] |rs2 |rs1 |funct3 |imm[4:0] |opcode |S-type -8+|*RV32Q Standard Extension* -3+|imm[11:0] |rs1 |100 |rd |0000111 |FLQ -2+|imm[11:5] |rs2 |rs1 |100 |imm[4:0] |0100111 |FSQ -|rs3 |11 |rs2 |rs1 |rm |rd |1000011 |FMADD.Q -|rs3 |11 |rs2 |rs1 |rm |rd |1000111 |FMSUB.Q -|rs3 |11 |rs2 |rs1 |rm |rd |1001011 |FNMSUB.Q -|rs3 |11 |rs2 |rs1 |rm |rd |1001111 |FNMADD.Q -2+|0000011 |rs2 |rs1 |rm |rd |1010011 |FADD.Q -2+|0000111 |rs2 |rs1 |rm |rd |1010011 |FSUB.Q -2+|0001011 |rs2 |rs1 |rm |rd |1010011 |FMUL.Q -2+|0001111 |rs2 |rs1 |rm |rd |1010011 |FDIV.Q -2+|0101111 |00000 |rs1 |rm |rd |1010011 |FSQRT.Q -2+|0010011 |rs2 |rs1 |000 |rd |1010011 |FSGNJ.Q -2+|0010011 |rs2 |rs1 |001 |rd |1010011 |FSGNJN.Q -2+|0010011 |rs2 |rs1 |010 |rd |1010011 |FSGNJX.Q -2+|0010111 |rs2 |rs1 |000 |rd |1010011 |FMIN.Q -2+|0010111 |rs2 |rs1 |001 |rd |1010011 |FMAX.Q -2+|0100000 |00011 |rs1 |rm |rd |1010011 |FCVT.S.Q -2+|0100011 |00000 |rs1 |rm |rd |1010011 |FCVT.Q.S -2+|0100001 |00011 |rs1 |rm |rd |1010011 |FCVT.D.Q -2+|0100011 |00001 |rs1 |rm |rd |1010011 |FCVT.Q.D -2+|1010011 |rs2 |rs1 |010 |rd |1010011 |FEQ.Q -2+|1010011 |rs2 |rs1 |001 |rd |1010011 |FLT.Q -2+|1010011 |rs2 |rs1 |000 |rd |1010011 |FLE.Q -2+|1110011 |00000 |rs1 |001 |rd |1010011 |FCLASS.Q -2+|1100011 |00000 |rs1 |rm |rd |1010011 |FCVT.W.Q -2+|1100011 |00001 |rs1 |rm |rd |1010011 |FCVT.WU.Q -2+|1101011 |00000 |rs1 |rm |rd |1010011 |FCVT.Q.W -2+|1101011 |00001 |rs1 |rm |rd |1010011 |FCVT.Q.WU -8+|*RV64Q Standard Extension (in addition to RV32Q)* -|1100011 |00010 | |rs1 |rm |rd |1010011 |FCVT.L.Q -|1100011 |00011 | |rs1 |rm |rd |1010011 |FCVT.LU.Q -|1101011 |00010 | |rs1 |rm |rd |1010011 |FCVT.Q.L -|1101011 |00011 | |rs1 |rm |rd |1010011 |FCVT.Q.LU + |31 |27 |26 |25 |24 | 20|19 | 15| 14 | 12|11 | 7|6 | 0| + 4+^|funt7 2+^|rs2 2+^|rs1 2+^|funct3 2+^|rd 2+^|opcode <|R-type + 6+^|imm[11:0] 2+^|rs1 2+^|funct3 2+^|rd 2+^|opcode <|I-type + 4+^|imm[11:5] 2+^|rs2 2+^|rs1 2+^|funct3 2+^|imm[4:0] 2+^|opcode <|S-type + 4+^|imm[12\|10:5] 2+^|rs2 2+^|rs1 2+^|funct3 2+^|imm[4:1\|11] 2+^|opcode <|B-type +10+^|imm[31:12] 2+^|rd 2+^|opcode <|U-type +10+^|imm[20\|10:1\|11\|19:12] 2+^|rd 2+^|opcode <|J-type +15+^| +15+^|*RV32I Base Instruction Set* +10+^|imm[31:12] 2+^|rd 2+^|0110111 <|LUI +10+^|imm[31:12] 2+^|rd 2+^|0010111 <|AUIPC +10+^|imm[20\|10:1\|11\|19:12] 2+^|rd 2+^|1101111 <|JAL + 6+^|imm[11:0] 2+^|rs1 2+^|000 2+^|rd 2+^|1100111 <|JALR + 4+^|imm[12\|10:5] 2+^|rs2 2+^|rs1 2+^|000 2+^|imm[4:1\|11] 2+^|1100011 <|BEQ + 4+^|imm[12\|10:5] 2+^|rs2 2+^|rs1 2+^|001 2+^|imm[4:1\|11] 2+^|1100011 <|BNE + 4+^|imm[12\|10:5] 2+^|rs2 2+^|rs1 2+^|100 2+^|imm[4:1\|11] 2+^|1100011 <|BLT + 4+^|imm[12\|10:5] 2+^|rs2 2+^|rs1 2+^|101 2+^|imm[4:1\|11] 2+^|1100011 <|BGE + 4+^|imm[12\|10:5] 2+^|rs2 2+^|rs1 2+^|110 2+^|imm[4:1\|11] 2+^|1100011 <|BLTU + 4+^|imm[12\|10:5] 2+^|rs2 2+^|rs1 2+^|111 2+^|imm[4:1\|11] 2+^|1100011 <|BGEU + 6+^|imm[11:0] 2+^|rs1 2+^|000 2+^|rd 2+^|0000011 <|LB + 6+^|imm[11:0] 2+^|rs1 2+^|001 2+^|rd 2+^|0000011 <|LH + 6+^|imm[11:0] 2+^|rs1 2+^|010 2+^|rd 2+^|0000011 <|LW + 6+^|imm[11:0] 2+^|rs1 2+^|100 2+^|rd 2+^|0000011 <|LBU + 6+^|imm[11:0] 2+^|rs1 2+^|101 2+^|rd 2+^|0000011 <|LHU + 4+^|imm[11:5] 2+^|rs2 2+^|rs1 2+^|000 2+^|imm[4:0] 2+^|0100011 <|SB + 4+^|imm[11:5] 2+^|rs2 2+^|rs1 2+^|001 2+^|imm[4:0] 2+^|0100011 <|SH + 4+^|imm[11:5] 2+^|rs2 2+^|rs1 2+^|010 2+^|imm[4:0] 2+^|0100011 <|SW + 6+^|imm[11:0] 2+^|rs1 2+^|000 2+^|rd 2+^|0010011 <|ADDI + 6+^|imm[11:0] 2+^|rs1 2+^|010 2+^|rd 2+^|0010011 <|SLTI + 6+^|imm[11:0] 2+^|rs1 2+^|011 2+^|rd 2+^|0010011 <|SLTIU + 6+^|imm[11:0] 2+^|rs1 2+^|100 2+^|rd 2+^|0010011 <|XORI + 6+^|imm[11:0] 2+^|rs1 2+^|110 2+^|rd 2+^|0010011 <|ORI + 6+^|imm[11:0] 2+^|rs1 2+^|111 2+^|rd 2+^|0010011 <|ANDI + 4+^|0000000 2+^|shamt 2+^|rs1 2+^|001 2+^|rd 2+^|0010011 <|SLLI + 4+^|0000000 2+^|shamt 2+^|rs1 2+^|101 2+^|rd 2+^|0010011 <|SRLI + 4+^|0100000 2+^|shamt 2+^|rs1 2+^|101 2+^|rd 2+^|0010011 <|SRAI + 4+^|0000000 2+^|rs2 2+^|rs1 2+^|000 2+^|rd 2+^|0110011 <|ADD + 4+^|0100000 2+^|rs2 2+^|rs1 2+^|000 2+^|rd 2+^|0110011 <|SUB + 4+^|0000000 2+^|rs2 2+^|rs1 2+^|001 2+^|rd 2+^|0110011 <|SLL + 4+^|0000000 2+^|rs2 2+^|rs1 2+^|010 2+^|rd 2+^|0110011 <|SLT + 4+^|0000000 2+^|rs2 2+^|rs1 2+^|011 2+^|rd 2+^|0110011 <|SLTU + 4+^|0000000 2+^|rs2 2+^|rs1 2+^|100 2+^|rd 2+^|0110011 <|XOR + 4+^|0000000 2+^|rs2 2+^|rs1 2+^|101 2+^|rd 2+^|0110011 <|SRL + 4+^|0100000 2+^|rs2 2+^|rs1 2+^|101 2+^|rd 2+^|0110011 <|SRA + 4+^|0000000 2+^|rs2 2+^|rs1 2+^|110 2+^|rd 2+^|0110011 <|OR + 4+^|0000000 2+^|rs2 2+^|rs1 2+^|111 2+^|rd 2+^|0110011 <|AND + 3+^|fm 2+^|pred 1+^|succ 2+^|rs1 2+^|000 2+^|rd 2+^|0001111 <|FENCE + 3+^|1000 2+^|0011 1+^|0011 2+^|00000 2+^|000 2+^|00000 2+^|0001111 <|FENCE.TSO + 3+^|0000 2+^|0001 1+^|0000 2+^|00000 2+^|000 2+^|00000 2+^|0001111 <|PAUSE + 6+^|000000000000 2+^|00000 2+^|000 2+^|00000 2+^|1110011 <|ECALL + 6+^|000000000001 2+^|00000 2+^|000 2+^|00000 2+^|1110011 <|EBREAK +15+^| + |31 |27 |26 |25 |24 | 20|19 | 15| 14 | 12|11 | 7|6 | 0| + 4+^|funt7 2+^|rs2 2+^|rs1 2+^|funct3 2+^|rd 2+^|opcode <|R-type + 6+^|imm[11:0] 2+^|rs1 2+^|funct3 2+^|rd 2+^|opcode <|I-type + 4+^|imm[11:5] 2+^|rs2 2+^|rs1 2+^|funct3 2+^|imm[4:0] 2+^|opcode <|S-type +15+^| +15+^|*RV64I Base Instruction Set (in addition to RV32I)* + 6+^|imm[11:0] 2+^|rs1 2+^|110 2+^|rd 2+^|0000011 <|LWU + 6+^|imm[11:0] 2+^|rs1 2+^|011 2+^|rd 2+^|0000011 <|LD + 4+^|imm[11:5] 2+^|rs2 2+^|rs1 2+^|011 2+^|imm[4:0] 2+^|0100011 <|SD + 3+^|000000 3+^|shamt 2+^|rs1 2+^|001 2+^|rd 2+^|0010011 <|SLLI + 3+^|000000 3+^|shamt 2+^|rs1 2+^|101 2+^|rd 2+^|0010011 <|SRLI + 3+^|010000 3+^|shamt 2+^|rs1 2+^|101 2+^|rd 2+^|0010011 <|SRAI + 6+^|imm[11:0] 2+^|rs1 2+^|000 2+^|rd 2+^|0011011 <|ADDIW + 4+^|0000000 2+^|shamt 2+^|rs1 2+^|001 2+^|rd 2+^|0011011 <|SLLIW + 4+^|0000000 2+^|shamt 2+^|rs1 2+^|101 2+^|rd 2+^|0011011 <|SRLIW + 4+^|0100000 2+^|shamt 2+^|rs1 2+^|101 2+^|rd 2+^|0011011 <|SRAIW + 4+^|0000000 2+^|rs2 2+^|rs1 2+^|000 2+^|rd 2+^|0111011 <|ADDW + 4+^|0100000 2+^|rs2 2+^|rs1 2+^|000 2+^|rd 2+^|0111011 <|SUBW + 4+^|0000000 2+^|rs2 2+^|rs1 2+^|001 2+^|rd 2+^|0111011 <|SLLW + 4+^|0000000 2+^|rs2 2+^|rs1 2+^|101 2+^|rd 2+^|0111011 <|SRLW + 4+^|0100000 2+^|rs2 2+^|rs1 2+^|101 2+^|rd 2+^|0111011 <|SRAW +15+^| +15+^|*RV32/RV64 _Zifencei_ Standard Extension* + 6+^|imm[11:0] 2+^|rs1 2+^|001 2+^|rd 2+^|0001111 <|FENCE.I +15+^| +15+^|*RV32/RV64 _Zicsr_ Standard Extension* + 6+^|csr 2+^|rs1 2+^|001 2+^|rd 2+^|1110011 <|CSRRW + 6+^|csr 2+^|rs1 2+^|010 2+^|rd 2+^|1110011 <|CSRRS + 6+^|csr 2+^|rs1 2+^|011 2+^|rd 2+^|1110011 <|CSRRC + 6+^|csr 2+^|uimm 2+^|101 2+^|rd 2+^|1110011 <|CSRRWI + 6+^|csr 2+^|uimm 2+^|110 2+^|rd 2+^|1110011 <|CSRRSI + 6+^|csr 2+^|uimm 2+^|111 2+^|rd 2+^|1110011 <|CSRRCI +15+^| +15+^|*RV32M Standard Extension* + 4+^|0000001 2+^|rs2 2+^|rs1 2+^|000 2+^|rd 2+^|0110011 <|MUL + 4+^|0000001 2+^|rs2 2+^|rs1 2+^|001 2+^|rd 2+^|0110011 <|MULH + 4+^|0000001 2+^|rs2 2+^|rs1 2+^|010 2+^|rd 2+^|0110011 <|MULHSU + 4+^|0000001 2+^|rs2 2+^|rs1 2+^|011 2+^|rd 2+^|0110011 <|MULHU + 4+^|0000001 2+^|rs2 2+^|rs1 2+^|100 2+^|rd 2+^|0110011 <|DIV + 4+^|0000001 2+^|rs2 2+^|rs1 2+^|101 2+^|rd 2+^|0110011 <|DIVU + 4+^|0000001 2+^|rs2 2+^|rs1 2+^|110 2+^|rd 2+^|0110011 <|REM + 4+^|0000001 2+^|rs2 2+^|rs1 2+^|111 2+^|rd 2+^|0110011 <|REMU +15+^| +15+^|*RV64M Standard Extension (in addition to RV32M)* + 4+^|0000001 2+^|rs2 2+^|rs1 2+^|000 2+^|rd 2+^|0111011 <|MULW + 4+^|0000001 2+^|rs2 2+^|rs1 2+^|100 2+^|rd 2+^|0111011 <|DIVW + 4+^|0000001 2+^|rs2 2+^|rs1 2+^|101 2+^|rd 2+^|0111011 <|DIVUW + 4+^|0000001 2+^|rs2 2+^|rs1 2+^|110 2+^|rd 2+^|0111011 <|REMW + 4+^|0000001 2+^|rs2 2+^|rs1 2+^|111 2+^|rd 2+^|0111011 <|REMUW +15+^| + |31 |27 |26 |25 |24 | 20|19 | 15| 14 | 12|11 | 7|6 | 0| + 4+^|funt7 2+^|rs2 2+^|rs1 2+^|funct3 2+^|rd 2+^|opcode <|R-type +15+^| +15+^|*RV32A Standard Extension* + 2+^|00010 ^|aq ^|rl 2+^|00000 2+^|rs1 2+^|010 2+^|rd 2+^|0101111 <|LR.W + 2+^|00011 ^|aq ^|rl 2+^|rs2 2+^|rs1 2+^|010 2+^|rd 2+^|0101111 <|SC.W + 2+^|00001 ^|aq ^|rl 2+^|rs2 2+^|rs1 2+^|010 2+^|rd 2+^|0101111 <|AMOSWAP.W + 2+^|00000 ^|aq ^|rl 2+^|rs2 2+^|rs1 2+^|010 2+^|rd 2+^|0101111 <|AMOADD.W + 2+^|00100 ^|aq ^|rl 2+^|rs2 2+^|rs1 2+^|010 2+^|rd 2+^|0101111 <|AMOXOR.W + 2+^|01100 ^|aq ^|rl 2+^|rs2 2+^|rs1 2+^|010 2+^|rd 2+^|0101111 <|AMOAND.W + 2+^|01000 ^|aq ^|rl 2+^|rs2 2+^|rs1 2+^|010 2+^|rd 2+^|0101111 <|AMOOR.W + 2+^|10000 ^|aq ^|rl 2+^|rs2 2+^|rs1 2+^|010 2+^|rd 2+^|0101111 <|AMOMIN.W + 2+^|10100 ^|aq ^|rl 2+^|rs2 2+^|rs1 2+^|010 2+^|rd 2+^|0101111 <|AMOMAX.W + 2+^|11000 ^|aq ^|rl 2+^|rs2 2+^|rs1 2+^|010 2+^|rd 2+^|0101111 <|AMOMINU.W + 2+^|11100 ^|aq ^|rl 2+^|rs2 2+^|rs1 2+^|010 2+^|rd 2+^|0101111 <|AMOMAXU.W +15+^| +15+^|*RV64A Standard Extension (in addition to RV32A)* + 2+^|00010 ^|aq ^|rl 2+^|00000 2+^|rs1 2+^|011 2+^|rd 2+^|0101111 <|LR.D + 2+^|00011 ^|aq ^|rl 2+^|rs2 2+^|rs1 2+^|011 2+^|rd 2+^|0101111 <|SC.D + 2+^|00001 ^|aq ^|rl 2+^|rs2 2+^|rs1 2+^|011 2+^|rd 2+^|0101111 <|AMOSWAP.D + 2+^|00000 ^|aq ^|rl 2+^|rs2 2+^|rs1 2+^|011 2+^|rd 2+^|0101111 <|AMOADD.D + 2+^|00100 ^|aq ^|rl 2+^|rs2 2+^|rs1 2+^|011 2+^|rd 2+^|0101111 <|AMOXOR.D + 2+^|01100 ^|aq ^|rl 2+^|rs2 2+^|rs1 2+^|011 2+^|rd 2+^|0101111 <|AMOAND.D + 2+^|01000 ^|aq ^|rl 2+^|rs2 2+^|rs1 2+^|011 2+^|rd 2+^|0101111 <|AMOOR.D + 2+^|10000 ^|aq ^|rl 2+^|rs2 2+^|rs1 2+^|011 2+^|rd 2+^|0101111 <|AMOMIN.D + 2+^|10100 ^|aq ^|rl 2+^|rs2 2+^|rs1 2+^|011 2+^|rd 2+^|0101111 <|AMOMAX.D + 2+^|11000 ^|aq ^|rl 2+^|rs2 2+^|rs1 2+^|011 2+^|rd 2+^|0101111 <|AMOMINU.D + 2+^|11100 ^|aq ^|rl 2+^|rs2 2+^|rs1 2+^|011 2+^|rd 2+^|0101111 <|AMOMAXU.D +15+^| + |31 |27 |26 |25 |24 | 20|19 | 15| 14 | 12|11 | 7|6 | 0| + 4+^|funt7 2+^|rs2 2+^|rs1 2+^|funct3 2+^|rd 2+^|opcode <|R-type + 2+^|rs3 2+^|funct2 2+^|rs2 2+^|rs1 2+^|funct3 2+^|rd 2+^|opcode <|R4-type + 6+^|imm[11:0] 2+^|rs1 2+^|funct3 2+^|rd 2+^|opcode <|I-type + 4+^|imm[11:5] 2+^|rs2 2+^|rs1 2+^|funct3 2+^|imm[4:0] 2+^|opcode <|S-type +15+^| +15+^|*RV32F Standard Extension* + 6+^|imm[11:0] 2+^|rs1 2+^|010 2+^|rd 2+^|0000111 <|FLW + 4+^|imm[11:5] 2+^|rs2 2+^|rs1 2+^|010 2+^|imm[4:0] 2+^|0100111 <|FSW + 2+^|rs3 2+^|00 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1000011 <|FMADD.S + 2+^|rs3 2+^|00 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1000111 <|FMSUB.S + 2+^|rs3 2+^|00 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1001011 <|FNMSUB.S + 2+^|rs3 2+^|00 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1001111 <|FNMADD.S + 4+^|0000000 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FADD.S + 4+^|0000100 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FSUB.S + 4+^|0001000 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FMUL.S + 4+^|0001100 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FDIV.S + 4+^|0101100 2+^|00000 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FSQRT.S + 4+^|0010000 2+^|rs2 2+^|rs1 2+^|000 2+^|rd 2+^|1010011 <|FSGNJ.S + 4+^|0010000 2+^|rs2 2+^|rs1 2+^|001 2+^|rd 2+^|1010011 <|FSGNJN.S + 4+^|0010000 2+^|rs2 2+^|rs1 2+^|010 2+^|rd 2+^|1010011 <|FSGNJX.S + 4+^|0010100 2+^|rs2 2+^|rs1 2+^|000 2+^|rd 2+^|1010011 <|FMIN.S + 4+^|0010100 2+^|rs2 2+^|rs1 2+^|001 2+^|rd 2+^|1010011 <|FMAX.S + 4+^|1100000 2+^|00000 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.W.S + 4+^|1100000 2+^|00001 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.WU.S + 4+^|1110000 2+^|00000 2+^|rs1 2+^|000 2+^|rd 2+^|1010011 <|FMV.X.W + 4+^|1010000 2+^|rs2 2+^|rs1 2+^|010 2+^|rd 2+^|1010011 <|FEQ.S + 4+^|1010000 2+^|rs2 2+^|rs1 2+^|001 2+^|rd 2+^|1010011 <|FLT.S + 4+^|1010000 2+^|rs2 2+^|rs1 2+^|000 2+^|rd 2+^|1010011 <|FLE.S + 4+^|1110000 2+^|00000 2+^|rs1 2+^|001 2+^|rd 2+^|1010011 <|FCLASS.S + 4+^|1101000 2+^|00000 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.S.W + 4+^|1101000 2+^|00001 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.S.WU + 4+^|1111000 2+^|00000 2+^|rs1 2+^|000 2+^|rd 2+^|1010011 <|FMV.W.X +15+^| +15+^|*RV64F Standard Extension (in addition to RV32F)* + 4+^|1100000 2+^|00010 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.L.S + 4+^|1100000 2+^|00011 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.LU.S + 4+^|1101000 2+^|00010 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.S.L + 4+^|1101000 2+^|00011 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.S.LU +15+^| + |31 |27 |26 |25 |24 | 20|19 | 15| 14 | 12|11 | 7|6 | 0| + 4+^|funt7 2+^|rs2 2+^|rs1 2+^|funct3 2+^|rd 2+^|opcode <|R-type + 2+^|rs3 2+^|funct2 2+^|rs2 2+^|rs1 2+^|funct3 2+^|rd 2+^|opcode <|R4-type + 6+^|imm[11:0] 2+^|rs1 2+^|funct3 2+^|rd 2+^|opcode <|I-type + 4+^|imm[11:5] 2+^|rs2 2+^|rs1 2+^|funct3 2+^|imm[4:0] 2+^|opcode <|S-type +15+^| +15+|*RV32D Standard Extension* + 6+^|imm[11:0] 2+^|rs1 2+^|011 2+^|rd 2+^|0000111 <|FLD + 4+^|imm[11:5] 2+^|rs2 2+^|rs1 2+^|011 2+^|imm[4:0] 2+^|0100111 <|FSD + 2+^|rs3 2+^|01 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1000011 <|FMADD.D + 2+^|rs3 2+^|01 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1000111 <|FMSUB.D + 2+^|rs3 2+^|01 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1001011 <|FNMSUB.D + 2+^|rs3 2+^|01 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1001111 <|FNMADD.D + 4+^|0000001 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FADD.D + 4+^|0000101 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FSUB.D + 4+^|0001001 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FMUL.D + 4+^|0001101 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FDIV.D + 4+^|0101101 2+^|00000 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FSQRT.D + 4+^|0010001 2+^|rs2 2+^|rs1 2+^|000 2+^|rd 2+^|1010011 <|FSGNJ.D + 4+^|0010001 2+^|rs2 2+^|rs1 2+^|001 2+^|rd 2+^|1010011 <|FSGNJN.D + 4+^|0010001 2+^|rs2 2+^|rs1 2+^|010 2+^|rd 2+^|1010011 <|FSGNJX.D + 4+^|0010101 2+^|rs2 2+^|rs1 2+^|000 2+^|rd 2+^|1010011 <|FMIN.D + 4+^|0010101 2+^|rs2 2+^|rs1 2+^|001 2+^|rd 2+^|1010011 <|FMAX.D + 4+^|0100000 2+^|00001 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.S.D + 4+^|0100001 2+^|00000 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.D.S + 4+^|1010001 2+^|rs2 2+^|rs1 2+^|010 2+^|rd 2+^|1010011 <|FEQ.D + 4+^|1010001 2+^|rs2 2+^|rs1 2+^|001 2+^|rd 2+^|1010011 <|FLT.D + 4+^|1010001 2+^|rs2 2+^|rs1 2+^|000 2+^|rd 2+^|1010011 <|FLE.D + 4+^|1110001 2+^|00000 2+^|rs1 2+^|001 2+^|rd 2+^|1010011 <|FCLASS.D + 4+^|1100001 2+^|00000 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.W.D + 4+^|1100001 2+^|00001 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.WU.D + 4+^|1101001 2+^|00000 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.D.W + 4+^|1101001 2+^|00001 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.D.WU +15+^| +15+^|*RV64D Standard Extension (in addition to RV32D)* + 4+^|1100001 2+^|00010 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.L.D + 4+^|1100001 2+^|00011 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.LU.D + 4+^|1110001 2+^|00000 2+^|rs1 2+^|000 2+^|rd 2+^|1010011 <|FMV.X.D + 4+^|1101001 2+^|00010 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.D.L + 4+^|1101001 2+^|00011 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.D.LU + 4+^|1111001 2+^|00000 2+^|rs1 2+^|000 2+^|rd 2+^|1010011 <|FMV.D.X +15+^| + |31 |27 |26 |25 |24 | 20|19 | 15| 14 | 12|11 | 7|6 | 0| + 4+^|funt7 2+^|rs2 2+^|rs1 2+^|funct3 2+^|rd 2+^|opcode <|R-type + 2+^|rs3 2+^|funct2 2+^|rs2 2+^|rs1 2+^|funct3 2+^|rd 2+^|opcode <|R4-type + 6+^|imm[11:0] 2+^|rs1 2+^|funct3 2+^|rd 2+^|opcode <|I-type + 4+^|imm[11:5] 2+^|rs2 2+^|rs1 2+^|funct3 2+^|imm[4:0] 2+^|opcode <|S-type + 6+^|imm[11:0] 2+^|rs1 2+^|100 2+^|rd 2+^|0000111 <|FLQ +15+^| +15+^|*RV32Q Standard Extension* + 4+^|imm[11:5] 2+^|rs2 2+^|rs1 2+^|100 2+^|imm[4:0] 2+^|0100111 <|FSQ + 2+^|rs3 2+^|11 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1000011 <|FMADD.Q + 2+^|rs3 2+^|11 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1000111 <|FMSUB.Q + 2+^|rs3 2+^|11 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1001011 <|FNMSUB.Q + 2+^|rs3 2+^|11 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1001111 <|FNMADD.Q + 4+^|0000011 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FADD.Q + 4+^|0000111 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FSUB.Q + 4+^|0001011 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FMUL.Q + 4+^|0001111 2+^|rs2 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FDIV.Q + 4+^|0101111 2+^|00000 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FSQRT.Q + 4+^|0010011 2+^|rs2 2+^|rs1 2+^|000 2+^|rd 2+^|1010011 <|FSGNJ.Q + 4+^|0010011 2+^|rs2 2+^|rs1 2+^|001 2+^|rd 2+^|1010011 <|FSGNJN.Q + 4+^|0010011 2+^|rs2 2+^|rs1 2+^|010 2+^|rd 2+^|1010011 <|FSGNJX.Q + 4+^|0010111 2+^|rs2 2+^|rs1 2+^|000 2+^|rd 2+^|1010011 <|FMIN.Q + 4+^|0010111 2+^|rs2 2+^|rs1 2+^|001 2+^|rd 2+^|1010011 <|FMAX.Q + 4+^|0100000 2+^|00011 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.S.Q + 4+^|0100011 2+^|00000 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.Q.S + 4+^|0100001 2+^|00011 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.D.Q + 4+^|0100011 2+^|00001 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.Q.D + 4+^|1010011 2+^|rs2 2+^|rs1 2+^|010 2+^|rd 2+^|1010011 <|FEQ.Q + 4+^|1010011 2+^|rs2 2+^|rs1 2+^|001 2+^|rd 2+^|1010011 <|FLT.Q + 4+^|1010011 2+^|rs2 2+^|rs1 2+^|000 2+^|rd 2+^|1010011 <|FLE.Q + 4+^|1110011 2+^|00000 2+^|rs1 2+^|001 2+^|rd 2+^|1010011 <|FCLASS.Q + 4+^|1100011 2+^|00000 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.W.Q + 4+^|1100011 2+^|00001 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.WU.Q + 4+^|1101011 2+^|00000 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.Q.W + 4+^|1101011 2+^|00001 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.Q.WU +15+^| +15+^|*RV64Q Standard Extension (in addition to RV32Q)* + 4+^|1100011 2+^|00010 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.L.Q + 4+^|1100011 2+^|00011 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.LU.Q + 4+^|1101011 2+^|00010 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.Q.L + 4+^|1101011 2+^|00011 2+^|rs1 2+^|rm 2+^|rd 2+^|1010011 <|FCVT.Q.LU |=== <<rvgcsrnames>> lists the CSRs that have currently been allocated CSR addresses. The timers, counters, and floating-point CSRs are the only CSRs defined in this specification. - [[rvgcsrnames]] .RISC-V control and status register (CSR) address map. -[%header,cols="1,1,1,4"] +[cols="1,1,1,4", frame=all, grid=cols] |=== -|Number |Privilege |Name |Description - -4+|Floating-Point Control and Status Registers - -|`0x001` |Read/write |`fflags` |Floating-Point Accrued Exceptions. - -|`0x002` |Read/write |`frm` |Floating-Point Dynamic Rounding Mode. - -|`0x003` |Read/write |`fcsr` |Floating-Point Control and Status Register (`frm` + `fflags`). - -4+|Counters and Timers - -|`0xC00` |Read-only |`cycle` |Cycle counter for RDCYCLE instruction. - -|`0xC01` |Read-only |`time` |Timer for RDTIME instruction. - -|`0xC02` |Read-only |`instret` |Instructions-retired counter for RDINSTRET instruction. - -|`0xC80` |Read-only |`cycleh` |Upper 32 bits of `cycle`, RV32I only. - -|`0xC81` |Read-only |`timeh` |Upper 32 bits of `time`, RV32I only. - -|`0xC82` |Read-only |`instreth` |Upper 32 bits of `instret`, RV32I only. +^|Number ^|Privilege ^|Name ^|Description +4+^|[underline]#Floating-Point Control and Status Registers# +^|`0x001` ^|Read/write |`fflags` |Floating-Point Accrued Exceptions. +^|`0x002` ^|Read/write |`frm` |Floating-Point Dynamic Rounding Mode. +^|`0x003` ^|Read/write |`fcsr` |Floating-Point Control and Status Register (`frm` + `fflags`). +4+^|[underline]#Counters and Timers# +^|`0xC00` ^|Read-only |`cycle` |Cycle counter for RDCYCLE instruction. +^|`0xC01` ^|Read-only |`time` |Timer for RDTIME instruction. +^|`0xC02` ^|Read-only |`instret` |Instructions-retired counter for RDINSTRET instruction. +^|`0xC80` ^|Read-only |`cycleh` |Upper 32 bits of `cycle`, RV32I only. +^|`0xC81` ^|Read-only |`timeh` |Upper 32 bits of `time`, RV32I only. +^|`0xC82` ^|Read-only |`instreth` |Upper 32 bits of `instret`, RV32I only. |=== - + |