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| author | elisa <elisa@riscv.org> | 2021-10-27 11:42:12 -0700 |
|---|---|---|
| committer | elisa <elisa@riscv.org> | 2021-10-27 11:42:12 -0700 |
| commit | 368ed53959996cbdff89e4d7effcd6fb26985fee (patch) | |
| tree | b4eb2e4be6bf8e49e870e6369456a7758473a7e9 | |
| parent | f6bfb73aa06f41fd26bd7cd4f8e46d699d2f833d (diff) | |
| parent | dbdea6b06f031a500a4c8ff3fcd52d0dfab2574e (diff) | |
| download | riscv-isa-manual-368ed53959996cbdff89e4d7effcd6fb26985fee.zip riscv-isa-manual-368ed53959996cbdff89e4d7effcd6fb26985fee.tar.gz riscv-isa-manual-368ed53959996cbdff89e4d7effcd6fb26985fee.tar.bz2 | |
Merge branch 'master' of github.com:riscv/riscv-isa-manual into convert2adoc
| -rw-r--r-- | src/machine.tex | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/machine.tex b/src/machine.tex index 93b16e4..a5e7037 100644 --- a/src/machine.tex +++ b/src/machine.tex @@ -2810,6 +2810,8 @@ If little-endian memory accesses are supported, the {\tt mstatus}/{\tt mstatush} field MBE is reset to 0. The {\tt misa} register is reset to enable the maximal set of supported extensions and widest MXLEN, as described in Section~\ref{sec:misa}. +For implementations with the ``A'' standard extension, there is no valid load +reservation. The {\tt pc} is set to an implementation-defined reset vector. The {\tt mcause} register is set to a value indicating the cause of the reset. |