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| author | Andrew Waterman <andrew@sifive.com> | 2021-11-02 14:55:18 -0700 |
|---|---|---|
| committer | Bill Traynor <btraynor@gmail.com> | 2022-07-26 11:19:25 -0400 |
| commit | b5a5d741e5e22dad34a80bed48cde51a6dcc5831 (patch) | |
| tree | 19a6bf127298eee7e840dfa8994e71fb22086e75 | |
| parent | 6334178233510504da3b0bb62bd4343db46f857d (diff) | |
| download | riscv-isa-manual-b5a5d741e5e22dad34a80bed48cde51a6dcc5831.zip riscv-isa-manual-b5a5d741e5e22dad34a80bed48cde51a6dcc5831.tar.gz riscv-isa-manual-b5a5d741e5e22dad34a80bed48cde51a6dcc5831.tar.bz2 | |
Remove reference to consecutive-SFENCE idiom
| -rw-r--r-- | src/supervisor.tex | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/src/supervisor.tex b/src/supervisor.tex index e12efbe..e9202f9 100644 --- a/src/supervisor.tex +++ b/src/supervisor.tex @@ -2328,11 +2328,6 @@ algorithm in Section~\ref{sv32algorithm}, except that: same as when SFENCE.VMA is used incorrectly: one of the translations will be chosen, but the choice is unpredictable. - When updating a region of NAPOT PTEs all at once, it is recommended that - software continue to follow the idiom in Figure~\ref{consecutive_sfences} - in which no more than one add and one branch instruction is inserted between - consecutive SFENCE.VMA instructions. - If an implementation chooses to use a NAPOT PTE (or cached version thereof), it might not consult the PTE directly specified by the algorithm in Section~\ref{sv32algorithm} at all. Therefore, the D and A bits may not be |