243 files changed, 2605 insertions, 2869 deletions
diff --git a/src/a-st-ext.adoc b/src/a-st-ext.adoc
index ff6e3f3..abc9ec3 100644
--- a/src/a-st-ext.adoc
+++ b/src/a-st-ext.adoc
@@ -54,7 +54,7 @@ same address domain.
 [[sec:lrsc]]
 === "Zalrsc" Extension for Load-Reserved/Store-Conditional Instructions
 
-include::images/wavedrom/load-reserve-st-conditional.adoc[]
+include::images/wavedrom/load-reserve-st-conditional.edn[]
 
 Complex atomic memory operations on a single memory word or doubleword
 are performed with the load-reserved (LR) and store-conditional (SC)
@@ -355,7 +355,7 @@ substantially easier to provide in some microarchitectural styles.
 [[sec:amo]]
 === "Zaamo" Extension for Atomic Memory Operations
 
-include::images/wavedrom/atomic-mem.adoc[]
+include::images/wavedrom/atomic-mem.edn[]
 
 The atomic memory operation (AMO) instructions perform read-modify-write
 operations for multiprocessor synchronization and are encoded with an
diff --git a/src/b-st-ext.adoc b/src/b-st-ext.adoc
index 0dfb273..79ed5aa 100644
--- a/src/b-st-ext.adoc
+++ b/src/b-st-ext.adoc
@@ -191,7 +191,7 @@ along with their specific mapping:
 
 |&#10003;
 |&#10003;
-|orc.b _rd_, _rs1_, _rs2_
+|orc.b _rd_, _rs_
 |<<#insns-orc_b>>
 |
 |&#10003;
@@ -836,7 +836,7 @@ a single bit in a register. The bit is specified by its index.
 
 |===
 
-[#zbkb,reftext="Bit-manipulation for Cryptography"]
+[[zbkb,Bit-manipulation for Cryptography]]
 ==== Zbkb: Bit-manipulation for Cryptography
 
 This extension contains instructions essential for implementing
@@ -912,8 +912,8 @@ common operations in cryptographic workloads.
 
 | &#10003; 
 | &#10003; 
-|  rev.b       
-| <<insns-revb>>
+|  brev8       
+| <<insns-brev8>>
 
 | &#10003; 
 | &#10003; 
@@ -932,7 +932,7 @@ common operations in cryptographic workloads.
 
 |===
 
-[#zbkc,reftext="Carry-less multiplication for Cryptography"]
+[[zbkc,Carry-less multiplication for Cryptography]]
 ==== Zbkc: Carry-less multiplication for Cryptography
 
 Carry-less multiplication is the multiplication in the polynomial ring over
@@ -960,7 +960,7 @@ efficiently implement the GHASH operation, which is part of this workload.
 
 |===
 
-[#zbkx,reftext="Crossbar permutations"]
+[[zbkx,Crossbar permutations]]
 ==== Zbkx: Crossbar permutations
 
 These instructions implement a "lookup table" for 4 and 8 bit elements
@@ -984,13 +984,13 @@ latency does not depend on the (secret) data being operated on.
 
 |&#10003;
 |&#10003;
-|xperm.n _rd_, _rs1_, _rs2_
-|<<#insns-xpermn>>
+|xperm4 _rd_, _rs1_, _rs2_
+|<<#insns-xperm4>>
 
 |&#10003;
 |&#10003;
-|xperm.b _rd_, _rs1_, _rs2_
-|<<#insns-xpermb>>
+|xperm8 _rd_, _rs1_, _rs2_
+|<<#insns-xperm8>>
 
 |===
 
@@ -2386,6 +2386,13 @@ Included in::
 |Ratified
 |===
 
+NOTE: For RV32, the `pack` instruction with _rs2_=`x0` is the `zext.h`
+instruction.
+Hence, for RV32, any extension that contains the `pack` instruction also
+contains the `zext.h` instruction (but not necessarily the `c.zext.h`
+instruction, which is only guaranteed to exist if both the Zcb and Zbb
+extensions are implemented).
+
 <<<
 [#insns-packh,reftext="Pack low bytes of registers"]
 ==== packh
@@ -2484,6 +2491,13 @@ Included in::
 |Ratified
 |===
 
+NOTE: For RV64, the `packw` instruction with _rs2_=`x0` is the `zext.h`
+instruction.
+Hence, for RV64, any extension that contains the `packw` instruction also
+contains the `zext.h` instruction (but not necessarily the `c.zext.h`
+instruction, which is only guaranteed to exist if both the Zcb and Zbb
+extensions are implemented).
+
 <<<
 [#insns-rev8,reftext="Byte-reverse register"]
 ==== rev8
@@ -2568,14 +2582,14 @@ Included in::
 |===
 
 <<<
-[#insns-revb,reftext="Reverse bits in bytes"]
-==== rev.b
+[#insns-brev8,reftext="Reverse bits in bytes"]
+==== brev8
 
 Synopsis::
 Reverse the bits in each byte of a source register.
 
 Mnemonic::
-rev.b _rd_, _rs_
+brev8 _rd_, _rs_
 
 Encoding::
 [wavedrom, , svg]
@@ -3368,7 +3382,8 @@ This instruction is the same as *slli* with *zext.w* performed on _rs1_ before s
 ==== unzip
 
 Synopsis::
-Implements the inverse of the zip instruction.
+Place odd and even bits of the source register into upper and lower halves of
+the destination register, respectively.
 
 Mnemonic::
 unzip _rd_, _rs_
@@ -3381,15 +3396,15 @@ Encoding::
 {bits: 5, name: 'rd'},
 {bits: 3, name: 0x5},
 {bits: 5, name: 'rs1'},
-{bits: 5, name: 0x1f},
+{bits: 5, name: 0xf},
 {bits: 7, name: 0x4},
 ]}
 ....
 
 Description:: 
-This instruction gathers bits from the high and low halves of the source
-word into odd/even bit positions in the destination word.
-It is the inverse of the <<insns-zip,zip>> instruction.
+This instruction scatters all of the odd and even bits of a source word into
+the high and low halves of a destination word.
+It is the inverse of the <<insns-zip-sc,zip>> instruction.
 This instruction is available only on RV32.
 
 Operation::
@@ -3471,14 +3486,14 @@ Included in::
 |===
 
 <<<
-[#insns-xpermb,reftext="Crossbar permutation (bytes)"]
-==== xperm.b
+[#insns-xperm8,reftext="Crossbar permutation (bytes)"]
+==== xperm8
 
 Synopsis::
 Byte-wise lookup of indices into a vector in registers.
 
 Mnemonic::
-xperm.b _rd_, _rs1_, _rs2_
+xperm8 _rd_, _rs1_, _rs2_
 
 Encoding::
 [wavedrom, , svg]
@@ -3495,7 +3510,7 @@ Encoding::
 ....
 
 Description:: 
-The xperm.b instruction operates on bytes.
+The xperm8 instruction operates on bytes.
 The _rs1_ register contains a vector of XLEN/8 8-bit elements.
 The _rs2_ register contains a vector of XLEN/8 8-bit indexes.
 The result is each element in _rs2_ replaced by the indexed element in _rs1_,
@@ -3504,15 +3519,15 @@ or zero if the index into _rs2_ is out of bounds.
 Operation::
 [source,sail]
 --
-val xpermb_lookup : (bits(8), xlenbits) -> bits(8)
-function xpermb_lookup (idx, lut) = {
+val xperm8_lookup : (bits(8), xlenbits) -> bits(8)
+function xperm8_lookup (idx, lut) = {
     (lut >> (idx @ 0b000))[7..0]
 }
 
-function clause execute ( XPERM_B (rs2,rs1,rd)) = {
+function clause execute ( XPERM8 (rs2,rs1,rd)) = {
     result : xlenbits = EXTZ(0b0);
     foreach(i from 0 to xlen by 8) {
-        result[i+7..i] = xpermn_lookup(X(rs2)[i+7..i], X(rs1));
+        result[i+7..i] = xperm8_lookup(X(rs2)[i+7..i], X(rs1));
     };
     X(rd) = result;
     RETIRE_SUCCESS
@@ -3532,14 +3547,14 @@ Included in::
 |===
 
 <<<
-[#insns-xpermn,reftext="Crossbar permutation (nibbles)"]
-==== xperm.n
+[#insns-xperm4,reftext="Crossbar permutation (nibbles)"]
+==== xperm4
 
 Synopsis::
 Nibble-wise lookup of indices into a vector.
 
 Mnemonic::
-xperm.n _rd_, _rs1_, _rs2_
+xperm4 _rd_, _rs1_, _rs2_
 
 Encoding::
 [wavedrom, , svg]
@@ -3556,7 +3571,7 @@ Encoding::
 ....
 
 Description:: 
-The xperm.n instruction operates on nibbles.
+The xperm4 instruction operates on nibbles.
 The _rs1_ register contains a vector of XLEN/4 4-bit elements.
 The _rs2_ register contains a vector of XLEN/4 4-bit indexes.
 The result is each element in _rs2_ replaced by the indexed element in _rs1_,
@@ -3565,15 +3580,15 @@ or zero if the index into _rs2_ is out of bounds.
 Operation::
 [source,sail]
 --
-val xpermn_lookup : (bits(4), xlenbits) -> bits(4)
-function xpermn_lookup (idx, lut) = {
+val xperm4_lookup : (bits(4), xlenbits) -> bits(4)
+function xperm4_lookup (idx, lut) = {
     (lut >> (idx @ 0b00))[3..0]
 }
 
-function clause execute ( XPERM_N (rs2,rs1,rd)) = {
+function clause execute ( XPERM4 (rs2,rs1,rd)) = {
     result : xlenbits = EXTZ(0b0);
     foreach(i from 0 to xlen by 4) {
-        result[i+3..i] = xpermn_lookup(X(rs2)[i+3..i], X(rs1));
+        result[i+3..i] = xperm4_lookup(X(rs2)[i+3..i], X(rs1));
     };
     X(rd) = result;
     RETIRE_SUCCESS
@@ -3660,8 +3675,8 @@ Included in::
 ==== zip
 
 Synopsis::
-Gather odd and even bits of the source word into upper/lower halves of the
-destination.
+Interleave upper and lower halves of the source register into odd and even
+bits of the destination register, respectivley.
 
 Mnemonic::
 zip _rd_, _rs_
@@ -3674,15 +3689,15 @@ Encoding::
 {bits: 5, name: 'rd'},
 {bits: 3, name: 0x1},
 {bits: 5, name: 'rs1'},
-{bits: 5, name: 0x1e},
+{bits: 5, name: 0xf},
 {bits: 7, name: 0x4},
 ]}
 ....
 
 Description:: 
-This instruction scatters all of the odd and even bits of a source word into
-the high and low halves of a destination word.
-It is the inverse of the <<insns-unzip,unzip>> instruction.
+This instruction gathers bits from the high and low halves of the source
+word into odd/even bit positions in the destination word.
+It is the inverse of the <<insns-unzip-sc,unzip>> instruction.
 This instruction is available only on RV32.
 
 Operation::
diff --git a/src/bfloat16.adoc b/src/bfloat16.adoc
index ba3e8bc..531484a 100644
--- a/src/bfloat16.adoc
+++ b/src/bfloat16.adoc
@@ -308,7 +308,7 @@ This extension provides the minimal set of instructions needed to enable scalar
 of the BF16 format. It enables BF16 as an interchange format as it provides conversion
 between BF16 values and FP32 values. 
 
-This extension requires the single-precision floating-point extension
+This extension depends upon the single-precision floating-point extension
 `F`, and the `FLH`, `FSH`, `FMV.X.H`, and `FMV.H.X` instructions as
 defined in the `Zfh` extension.
 
@@ -372,7 +372,7 @@ This extension provides the minimal set of instructions needed to enable vector
 format. It enables BF16 as an interchange format as it provides conversion between BF16 values
 and FP32 values.
 
-This extension requires either the
+This extension depends upon either the
 "V" extension or the `Zve32f` embedded vector extension.
 
 [NOTE]
@@ -428,7 +428,7 @@ the desired rounding mode.
 This extension provides
 a vector widening BF16 mul-add instruction that accumulates into FP32. 
 
-This extension requires the `Zvfbfmin` extension and the `Zfbfmin` extension.
+This extension depends upon the `Zvfbfmin` extension and the `Zfbfmin` extension.
 
 [%autowidth]
 [%header,cols="2,4"]
diff --git a/src/c-st-ext.adoc b/src/c-st-ext.adoc
index 97aca5f..701aae7 100644
--- a/src/c-st-ext.adoc
+++ b/src/c-st-ext.adoc
@@ -49,7 +49,7 @@ and/or D) is also implemented. In addition, RV32C includes a compressed
 jump and link instruction to compress short-range subroutine calls,
 where the same opcode is used to compress ADDIW for RV64C and RV128C.
 
-[TIP]
+[NOTE]
 ====
 Double-precision loads and stores are a significant fraction of static
 and dynamic instructions, hence the motivation to include them in the
@@ -100,7 +100,7 @@ instructions in one C instruction.
 It is important to note that the C extension is not designed to be a
 stand-alone ISA, and is meant to be used alongside a base ISA.
 
-[TIP]
+[NOTE]
 ====
 Variable-length instruction sets have long been used to improve code
 density. For example, the IBM Stretch cite:[stretch], developed in the late 1950s, had
@@ -217,7 +217,7 @@ For many RVC instructions, zero-valued immediates are disallowed and
 encoding space for other instructions requiring fewer operand bits.
 
 //[[cr-register]]
-//include::images/wavedrom/cr-register.adoc[]
+//include::images/wavedrom/cr-register.edn[]
 //.Compressed 16-bit RVC instructions
 //(((compressed, 16-bit)))
 
@@ -297,7 +297,7 @@ registers.
 
 ==== Stack-Pointer-Based Loads and Stores
 
-include::images/wavedrom/c-sp-load-store.adoc[]
+include::images/wavedrom/c-sp-load-store.edn[]
 [[c-sp-load-store]]
 //.Stack-Pointer-Based Loads and Stores--these instructions use the CI format.
 
@@ -334,7 +334,7 @@ register _rd_. It computes its effective address by adding the
 _zero_-extended offset, scaled by 8, to the stack pointer, `x2`. It
 expands to `fld rd, offset(x2)`.
 
-include::images/wavedrom/c-sp-load-store-css.adoc[]
+include::images/wavedrom/c-sp-load-store-css.edn[]
 [[c-sp-load-store-css]]
 //.Stack-Pointer-Based Loads and Stores--these instructions use the CSS format.
 
@@ -409,7 +409,7 @@ attain the greatest code size reduction.
 ==== Register-Based Loads and Stores
 
 [[reg-based-ldnstr]]
-include::images/wavedrom/reg-based-ldnstr.adoc[]
+include::images/wavedrom/reg-based-ldnstr.edn[]
 //.Compressed, register-based load and stores--these instructions use the CL format.
 (((compressed, register-based load and store)))
 These instructions use the CL format.
@@ -446,7 +446,7 @@ _zero_-extended offset, scaled by 8, to the base address in register
 `fld rd′, offset(rs1′)`.
 
 [[c-cs-format-ls]]
-include::images/wavedrom/c-cs-format-ls.adoc[]
+include::images/wavedrom/c-cs-format-ls.edn[]
 //.Compressed, CS format load and store--these instructions use the CS format.
 (((compressed, cs-format load and store)))
 
@@ -490,7 +490,7 @@ instructions. As with base RVI instructions, the offsets of all RVC
 control transfer instructions are in multiples of 2 bytes.
 
 [[c-cj-format-ls]]
-include::images/wavedrom/c-cj-format-ls.adoc[]
+include::images/wavedrom/c-cj-format-ls.edn[]
 //.Compressed, CJ format load and store--these instructions use the CJ format.
 (((compressed, cj-format load and store)))
 
@@ -507,7 +507,7 @@ the jump (`pc+2`) to the link register, `x1`. C.JAL expands to
 `jal x1, offset`.
 
 [[c-cr-format-ls]]
-include::images/wavedrom/c-cr-format-ls.adoc[]
+include::images/wavedrom/c-cr-format-ls.edn[]
 //.Compressed, CR format load and store--these instructions use the CR format.
 (((compressed, cr-format load and store)))
 
@@ -526,7 +526,7 @@ latexmath:[$\textit{rs1}{\neq}\texttt{x0}$]; the code point with
 latexmath:[$\textit{rs1}{=}\texttt{x0}$] corresponds to the C.EBREAK
 instruction.
 
-[TIP]
+[NOTE]
 ====
 Strictly speaking, C.JALR does not expand exactly to a base RVI
 instruction as the value added to the PC to form the link address is 2
@@ -535,7 +535,7 @@ bytes is only a very minor change to the base microarchitecture.
 ====
 
 [[c-cb-format-ls]]
-include::images/wavedrom/c-cb-format-ls.adoc[]
+include::images/wavedrom/c-cb-format-ls.edn[]
 //.Compressed, CB format load and store--these instructions use the CB format.
 (((compressed, cb-format load and store)))
 
@@ -562,7 +562,7 @@ The two constant-generation instructions both use the CI instruction
 format and can target any integer register.
 
 [[c-integer-const-gen]]
-include::images/wavedrom/c-integer-const-gen.adoc[]
+include::images/wavedrom/c-integer-const-gen.edn[]
 //.Integer constant generation format.
 (((compressed, integer constant generation)))
 
@@ -587,7 +587,7 @@ These integer register-immediate operations are encoded in the CI format
 and perform operations on an integer register and a 6-bit immediate.
 
 [[c-integer-register-immediate]]
-include::images/wavedrom/c-int-reg-immed.adoc[]
+include::images/wavedrom/c-int-reg-immed.edn[]
 //.Integer register-immediate format.
 (((compressed, integer register-immediate)))
 
@@ -605,10 +605,11 @@ zero for C.ADDIW, where this corresponds to `sext.w rd`. C.ADDIW is
 only valid when `_rd_≠x0`; the code points with
 `_rd_=x0` are reserved.
 
-C.ADDI16SP shares the opcode with C.LUI, but has a destination field of
+C.ADDI16SP (add immediate to stack pointer)
+shares the opcode with C.LUI, but has a destination field of
 `x2`. C.ADDI16SP adds the non-zero sign-extended 6-bit immediate to the
 value in the stack pointer (`sp=x2`), where the immediate is scaled to
-represent multiples of 16 in the range (-512,496). C.ADDI16SP is used to
+represent multiples of 16 in the range [-512, 496]. C.ADDI16SP is used to
 adjust the stack pointer in procedure prologues and epilogues. It
 expands into `addi x2, x2, nzimm[9:4]`. C.ADDI16SP is only valid when
 _nzimm_≠0; the code point with _nzimm_=0 is reserved.
@@ -620,10 +621,11 @@ always 16-byte aligned.
 ====
 
 [[c-ciw]]
-include::images/wavedrom/c-ciw.adoc[]
+include::images/wavedrom/c-ciw.edn[]
 //.CIW format.
 (((compressed, CIW)))
-C.ADDI4SPN is a CIW-format instruction that adds a _zero_-extended
+C.ADDI4SPN (add immediate to stack pointer, non-destructive)
+is a CIW-format instruction that adds a _zero_-extended
 non-zero immediate, scaled by 4, to the stack pointer, `x2`, and writes
 the result to `rd′`. This instruction is used to generate
 pointers to stack-allocated variables, and expands to
@@ -632,7 +634,7 @@ _nzuimm_≠0; the code points with _nzuimm_=0 are
 reserved.
 
 [[c-ci]]
-include::images/wavedrom/c-ci.adoc[]
+include::images/wavedrom/c-ci.edn[]
 //.CI format.
 (((compressed, CI)))
 
@@ -650,7 +652,7 @@ all base ISAs, the code points with `_rd_=x0` are HINTs, except those
 with _shamt[5]_=1 in RV32C.
 
 [[c-srli-srai]]
-include::images/wavedrom/c-srli-srai.adoc[]
+include::images/wavedrom/c-srli-srai.edn[]
 //.C-SRLI-SRAI format.
 (((compressed, C.SRLI, C.SRAI)))
 
@@ -686,7 +688,7 @@ that RV128C will not be frozen at the same point as RV32C and RV64C, to
 allow evaluation of typical usage of 128-bit address-space codes.
 ====
 [[c-andi]]
-include::images/wavedrom/c-andi.adoc[]
+include::images/wavedrom/c-andi.edn[]
 //.C.ANDI format
 (((compressed, C.ANDI)))
 
@@ -698,7 +700,7 @@ expands to `andi rd′, rd′, imm`.
 ==== Integer Register-Register Operations
 
 [[c-cr]]
-include::images/wavedrom/c-int-reg-to-reg-cr-format.adoc[]
+include::images/wavedrom/c-int-reg-to-reg-cr-format.edn[]
 //C.CR format
 ((((compressed. C.CR))))
 These instructions use the CR format.
@@ -707,7 +709,7 @@ C.MV copies the value in register _rs2_ into register _rd_. C.MV expands
 into `add rd, x0, rs2`. C.MV is only valid when
 `rs2≠x0` the code points with `rs2=x0` correspond to the C.JR instruction. The code points with `rs2≠x0` and `rd=x0` are HINTs.
 
-[TIP]
+[NOTE]
 ====
 _C.MV expands to a different instruction than the canonical MV
 pseudoinstruction, which instead uses ADDI. Implementations that handle
@@ -722,7 +724,7 @@ valid when `rs2≠x0` the code points with `rs2=x0` correspond to the C.JALR
 and C.EBREAK instructions. The code points with `rs2≠x0` and rd=x0 are HINTs.
 
 [[c-ca]]
-include::images/wavedrom/c-int-reg-to-reg-ca-format.adoc[]
+include::images/wavedrom/c-int-reg-to-reg-ca-format.edn[]
 //C.CA format
 ((((compressed. C.CA))))
 
@@ -771,7 +773,7 @@ improvement in static and dynamic compression.
 ==== Defined Illegal Instruction
 
 [[c-def-illegal-inst]]
-include::images/wavedrom/c-def-illegal-inst.adoc[]
+include::images/wavedrom/c-def-illegal-inst.edn[]
 ((((compressed. C.DIINST))))
 
 A 16-bit instruction with all bits zero is permanently reserved as an
@@ -791,7 +793,7 @@ non-existent memory regions.
 ==== NOP Instruction
 
 [[c-nop-instr]]
-include::images/wavedrom/c-nop-instr.adoc[]
+include::images/wavedrom/c-nop-instr.edn[]
 ((((compressed. C.NOPINSTR))))
 
 `C.NOP` is a CI-format instruction that does not change any user-visible
@@ -802,7 +804,7 @@ _imm_=0; the code points with _imm_≠0 encode HINTs.
 ==== Breakpoint Instruction
 
 [[c-breakpoint-instr]]
-include::images/wavedrom/c-breakpoint-instr.adoc[]
+include::images/wavedrom/c-breakpoint-instr.edn[]
 ((((compressed. C.BREAKPOINTINSTR))))
 
 Debuggers can use the `C.EBREAK` instruction, which expands to `ebreak`,
diff --git a/src/colophon.adoc b/src/colophon.adoc
index b7b52af..42820d7 100644
--- a/src/colophon.adoc
+++ b/src/colophon.adoc
@@ -33,7 +33,8 @@ h|Extension h|Version h|Status
 |*Zmmul* |*1.0* |*Ratified*
 |*A* |*2.1* |*Ratified*
 |*Zawrs* |*1.01* |*Ratified*
-|*Zacas* |*1.0* |*Ratifed*
+|*Zacas* |*1.0* |*Ratified*
+|*Zabha* |*1.0* |*Ratified*
 |*RVWMO* |*2.0* |*Ratified*
 |*Ztso* |*1.0* |*Ratified*
 |*CMO* |*1.0* |*Ratified*
@@ -65,6 +66,8 @@ h|Extension h|Version h|Status
 |*Zvksed* |*1.0* |*Ratified*
 |*Zvksh* |*1.0* |*Ratified*
 |*Zvkt* |*1.0* |*Ratified*
+|*Zicfiss* |*1.0* |*Ratified*
+|*Zicfilp* |*1.0* |*Ratified*
 |===
 
 The changes in this version of the document include:
diff --git a/src/counters.adoc b/src/counters.adoc
index f4a34af..7ec7210 100644
--- a/src/counters.adoc
+++ b/src/counters.adoc
@@ -14,7 +14,7 @@ counters (CYCLE, TIME, and INSTRET), which have dedicated functions
 (cycle count, real-time clock, and instructions retired, respectively).
 The Zicntr extension depends on the Zicsr extension.
 
-[TIP]
+[NOTE]
 ====
 We recommend provision of these basic counters in implementations as
 they are essential for basic performance analysis, adaptive and dynamic
@@ -27,7 +27,7 @@ Some execution environments might prohibit access to counters, for
 example, to impede timing side-channel attacks.
 ====
 
-include::images/wavedrom/counters-diag.adoc[]
+include::images/wavedrom/counters-diag.edn[]
 
 
 For base ISAs with XLEN&#8805;64, CSR instructions can access
@@ -35,7 +35,7 @@ the full 64-bit CSRs directly. In particular, the RDCYCLE, RDTIME, and
 RDINSTRET pseudoinstructions read the full 64 bits of the `cycle`,
 `time`, and `instret` counters.
 
-[TIP]
+[NOTE]
 ====
 The counter pseudoinstructions are mapped to the read-only
 `csrrs rd, counter, x0` canonical form, but the other read-only CSR
@@ -47,7 +47,7 @@ For base ISAs with XLEN=32, the Zicntr extension enables the three
 RDTIME, and RDINSTRET pseudoinstructions provide the lower 32 bits, and
 the RDCYCLEH, RDTIMEH, and RDINSTRETH pseudoinstructions provide the
 upper 32 bits of the respective counters.
-[TIP]
+[NOTE]
 ====
 We required the counters be 64 bits wide, even when XLEN=32, as
 otherwise it is very difficult for software to determine if values have
@@ -67,7 +67,7 @@ overflow in practice. The rate at which the cycle counter advances will
 depend on the implementation and operating environment. The execution
 environment should provide a means to determine the current rate
 (cycles/second) at which the cycle counter is incrementing.
-[TIP]
+[NOTE]
 ====
 RDCYCLE is intended to return the number of cycles executed by the
 processor core, not the hart. Precisely defining what is a "core" is
@@ -128,7 +128,7 @@ should be constant within a small error bound. The environment should
 provide a means to determine the accuracy of the clock (i.e., the
 maximum relative error between the nominal and actual real-time clock
 periods).
-[TIP]
+[NOTE]
 ====
 On some simple platforms, cycle count might represent a valid
 implementation of RDTIME, in which case RDTIME and RDCYCLE may return
@@ -141,7 +141,7 @@ bound should be set based on the requirements of the platform.
 
 The real-time clocks of all harts must be synchronized to within one
 tick of the real-time clock.
-[TIP]
+[NOTE]
 ====
 As with other architectural mandates, it suffices to appear "as if"
 harts are synchronized to within one tick of the real-time clock, i.e.,
@@ -154,7 +154,7 @@ hart from some arbitrary start point in the past. RDINSTRETH is only
 present when XLEN=32 and reads bits 63-32 of the same instruction
 counter. The underlying 64-bit counter should never overflow in
 practice.
-[TIP]
+[NOTE]
 ====
 Instructions that cause synchronous exceptions, including ECALL and
 EBREAK, are not considered to retire and hence do not increment the
@@ -180,7 +180,7 @@ hardware performance counters, `hpmcounter3-hpmcounter31`. When
 XLEN=32, the upper 32 bits of these performance counters are accessible
 via additional CSRs `hpmcounter3h- hpmcounter31h`. The Zihpm extension
 depends on the Zicsr extension.
-[TIP]
+[NOTE]
 ====
 In some applications, it is important to be able to read multiple
 counters at the same instant in time. When run under a multitasking
@@ -202,7 +202,7 @@ exception or may return a constant value.
 The execution environment should provide a means to determine the number
 and width of the implemented counters, and an interface to configure the
 events to be counted by each counter.
-[TIP]
+[NOTE]
 ====
 For execution environments implemented on RISC-V privileged platforms,
 the privileged architecture manual describes privileged CSRs controlling
diff --git a/src/d-st-ext.adoc b/src/d-st-ext.adoc
index 7c5eb4c..fcd90c4 100644
--- a/src/d-st-ext.adoc
+++ b/src/d-st-ext.adoc
@@ -58,7 +58,7 @@ so, the _n_ least-significant bits of the input are used as
 the input value, otherwise the input value is treated as an
 _n_-bit canonical NaN.
 
-[TIP]
+[NOTE]
 ====
 Earlier versions of this document did not define the behavior of feeding
 the results of narrower or wider operands into an operation, except to
@@ -103,7 +103,7 @@ value from the floating-point registers to memory.
 The double-precision value may be a NaN-boxed single-precision value.
 ====
 
-include::images/wavedrom/double-ls.adoc[]
+include::images/wavedrom/double-ls.edn[]
 [[double-ls]]
 //.Double-precision load and store
 
@@ -119,7 +119,7 @@ The double-precision floating-point computational instructions are
 defined analogously to their single-precision counterparts, but operate
 on double-precision operands and produce double-precision results.
 
-include::images/wavedrom/double-fl-compute.adoc[]
+include::images/wavedrom/double-fl-compute.edn[]
 [[fl-compute]]
 //.Double-precision float computational
 
@@ -143,7 +143,7 @@ All floating-point to integer and integer to floating-point conversion
 instructions round according to the _rm_ field. Note FCVT.D.W[U] always
 produces an exact result and is unaffected by rounding mode.
 
-include::images/wavedrom/double-fl-convert-mv.adoc[]
+include::images/wavedrom/double-fl-convert-mv.edn[]
 [[fl-convert-mv]]
 //.Double-precision float convert and move
 
@@ -157,7 +157,7 @@ never round.
 (((double-precision, to single-precision)))
 (((single-precision, to double-precision )))
 
-include::images/wavedrom/fcvt-sd-ds.adoc[]
+include::images/wavedrom/fcvt-sd-ds.edn[]
 [[fcvt-sd-ds]]
 //.Double-precision FCVT.S.D and FCVT.D.S
 
@@ -166,7 +166,7 @@ FSGNJN.D, and FSGNJX.D are defined analogously to the single-precision
 sign-injection instruction.
 //FSGNJ.D, FSGNJN.D, and FSGNJX.D
 
-include::images/wavedrom/fsjgnjnx-d.adoc[]
+include::images/wavedrom/fsjgnjnx-d.edn[]
 //.Double-precision sign-injection
 
 For XLEN&#8805;64 only, instructions are provided to move bit
@@ -180,11 +180,11 @@ register _rd_.
 FMV.X.D and FMV.D.X do not modify the bits being transferred; in
 particular, the payloads of non-canonical NaNs are preserved.
 
-include::images/wavedrom/d-xwwx.adoc[]
+include::images/wavedrom/d-xwwx.edn[]
 [[fmvxddx]]
 //.Double-precision float move to _rd_
 
-[TIP]
+[NOTE]
 ====
 Early versions of the RISC-V ISA had additional instructions to allow
 RV32 systems to transfer between the upper and lower portions of a
@@ -214,7 +214,7 @@ analogously to their single-precision counterparts, but operate on
 double-precision operands.
 (((floating-point, compare)))
 
-include::images/wavedrom/double-fl-compare.adoc[]
+include::images/wavedrom/double-fl-compare.edn[]
 [[fl-compare]]
 //.Double-precision float compare
 
@@ -225,8 +225,6 @@ defined analogously to its single-precision counterpart, but operates on
 double-precision operands.
 (((floating-point, classify)))
 
-include::images/wavedrom/double-fl-class.adoc[]
+include::images/wavedrom/double-fl-class.edn[]
 [[fl-class]]
 //.Double-precision float classify
-
-
diff --git a/src/example/sgemm.S b/src/example/sgemm.S
index e29cc8d..0567bf6 100644
--- a/src/example/sgemm.S
+++ b/src/example/sgemm.S
@@ -73,7 +73,7 @@ c_row_loop: # Loop across rows of C blocks
     mv cnp, cp # Initialize C n-loop pointer
 
 c_col_loop: # Loop across one row of C blocks
-    vsetvli nvl, nt, e32, ta, ma  # 32-bit vectors, LMUL=1
+    vsetvli nvl, nt, e32, m1, ta, ma  # 32-bit vectors, LMUL=1
 
     mv akp, ap   # reset pointer into A to beginning
     mv bkp, bnp # step to next column in B matrix
diff --git a/src/example/vvaddint32.s b/src/example/vvaddint32.s
index 22305d9..34d849b 100644
--- a/src/example/vvaddint32.s
+++ b/src/example/vvaddint32.s
@@ -8,7 +8,7 @@
     # a0 = n, a1 = x, a2 = y, a3 = z
     # Non-vector instructions are indented
 vvaddint32:
-    vsetvli t0, a0, e32, ta, ma  # Set vector length based on 32-bit vectors
+    vsetvli t0, a0, e32, m1, ta, ma  # Set vector length based on 32-bit vectors
     vle32.v v0, (a1)         # Get first vector
       sub a0, a0, t0         # Decrement number done
       slli t0, t0, 2         # Multiply number done by 4 bytes
diff --git a/src/extending.adoc b/src/extending.adoc
index 9124a26..6a322dc 100644
--- a/src/extending.adoc
+++ b/src/extending.adoc
@@ -31,7 +31,7 @@ categories: _standard_ versus _non-standard_.
 
 * A standard extension is one that is generally useful and that is
 designed to not conflict with any other standard extension. Currently,
-"MAFDQLCBTPV", described in other chapters of this manual, are either
+"MAFDQCBTPV", described in other chapters of this manual, are either
 complete or planned standard extensions.
 * A non-standard extension may be highly specialized and may conflict
 with other standard or non-standard extensions. We anticipate a wide
diff --git a/src/f-st-ext.adoc b/src/f-st-ext.adoc
index 96d5b44..a5a1816 100644
--- a/src/f-st-ext.adoc
+++ b/src/f-st-ext.adoc
@@ -21,7 +21,7 @@ instructions operate on values in the floating-point register file.
 Floating-point load and store instructions transfer floating-point
 values between registers and memory. Instructions to transfer values to and from the integer register file are also provided.
 
-[TIP]
+[NOTE]
 ====
 We considered a unified register file for both integer and
 floating-point values as this simplifies software register allocation
@@ -87,7 +87,7 @@ operations and holds the accrued exception flags, as shown in <<fcsr>>.
 
 [[fcsr, Floating-Point Control and Status Register]]
 .Floating-point control and status register
-include::images/wavedrom/float-csr.adoc[]
+include::images/wavedrom/float-csr.edn[]
 
 The `fcsr` register can be read and written with the FRCSR and FSCSR
 instructions, which are assembler pseudoinstructions built on the
@@ -189,7 +189,7 @@ quiet bit. For single-precision floating-point, this corresponds to the pattern
 (((NaN, generation)))
 (((NaN, propagation)))
 
-[TIP]
+[NOTE]
 ====
 We considered propagating NaN payloads, as is recommended by the
 standard, but this decision would have increased hardware cost.
@@ -231,7 +231,7 @@ signals.
 
 Floating-point loads and stores use the same base+offset addressing mode as the integer base ISAs, with a base address in register _rs1_ and a 12-bit signed byte offset. The FLW instruction loads a single-precision floating-point value from memory into floating-point register _rd_. FSW stores a single-precision value from floating-point register _rs2_ to memory.
 
-include::images/wavedrom/sp-load-store-2.adoc[]
+include::images/wavedrom/sp-load-store-2.edn[]
 [[sp-ldst]]
 //.SP load and store
 
@@ -283,7 +283,7 @@ minimumNumber and maximumNumber operations, rather than the IEEE
 handling of signaling NaNs.
 ====
 
-include::images/wavedrom/spfloat.adoc[]
+include::images/wavedrom/spfloat.edn[]
 [[spfloat]]
 //.Single-Precision Floating-Point Computational Instructions
 (((floating point, fused multiply-add)))
@@ -315,7 +315,7 @@ RISC-V FNMSUB and FNMADD instruction names are swapped compared to x86
 and ARM.
 ====
 
-include::images/wavedrom/spfloat2.adoc[]
+include::images/wavedrom/spfloat2.edn[]
 [[fnmaddsub]]
 //.F[N]MADD/F[N]MSUB instructions
 
@@ -389,7 +389,7 @@ All floating-point conversion instructions set the Inexact exception
 flag if the rounded result differs from the operand value and the
 Invalid exception flag is not set.
 
-include::images/wavedrom/spfloat-cn-cmp.adoc[]
+include::images/wavedrom/spfloat-cn-cmp.edn[]
 [[fcvt]]
 //.SP float convert and move
 
@@ -405,7 +405,7 @@ FSGNJN.S _rx, ry, ry_ moves the negation of _ry_ to _rx_ (assembler
 pseudoinstruction FNEG.S _rx, ry_); and FSGNJX.S _rx, ry, ry_ moves the absolute value of _ry_ to _rx_ (assembler pseudoinstruction FABS.S _rx,
 ry_).
 
-include::images/wavedrom/spfloat-sign-inj.adoc[]
+include::images/wavedrom/spfloat-sign-inj.edn[]
 [[inj]]
 
 [NOTE]
@@ -428,11 +428,11 @@ preserved.
 The FMV.W.X and FMV.X.W instructions were previously called FMV.S.X and FMV.X.S. The use of W is more consistent with their semantics as an instruction that moves 32 bits without interpreting them. This became clearer after defining NaN-boxing. To avoid disturbing existing code, both the W and S versions will be supported by tools.
 ====
 
-include::images/wavedrom/spfloat-mv.adoc[]
+include::images/wavedrom/spfloat-mv.edn[]
 [[spfloat-mv]]
 //.SP floating point move
 
-[TIP]
+[NOTE]
 ====
 The base floating-point ISA was defined so as to allow implementations
 to employ an internal recoding of the floating-point format in registers to simplify handling of subnormal values and possibly to reduce functional unit latency. To this end, the F extension avoids
@@ -454,7 +454,7 @@ _signaling_ comparisons: that is, they set the invalid operation
 exception flag if either input is NaN. FEQ.S performs a _quiet_
 comparison: it only sets the invalid operation exception flag if either input is a signaling NaN. For all three instructions, the result is 0 if either operand is NaN.
 
-include::images/wavedrom/spfloat-comp.adoc[]
+include::images/wavedrom/spfloat-comp.edn[]
 [[spfloat-comp]]
 //.SP floating point compare
 
@@ -478,7 +478,7 @@ _rd_ are cleared. Note that exactly one bit in _rd_ will be set.
 FCLASS.S does not set the floating-point exception flags.
 (((floating-point, classification)))
 
-include::images/wavedrom/spfloat-classify.adoc[]
+include::images/wavedrom/spfloat-classify.edn[]
 [[spfloat-classify]]
 //.SP floating point classify
 
diff --git a/src/hypervisor.adoc b/src/hypervisor.adoc
index d8a77e0..6887f4d 100644
--- a/src/hypervisor.adoc
+++ b/src/hypervisor.adoc
@@ -158,6 +158,7 @@ In this chapter, we use the term _HSXLEN_ to refer to the effective XLEN
 when executing in HS-mode, and _VSXLEN_ to refer to the effective XLEN
 when executing in VS-mode.
 
+[[sec:hstatus]]
 ==== Hypervisor Status (`hstatus`) Register 
 
 The `hstatus` register is an HSXLEN-bit read/write register formatted as
@@ -179,7 +180,7 @@ The VSXL field controls the effective XLEN for VS-mode (known as
 VSXLEN), which may differ from the XLEN for HS-mode (HSXLEN). When
 HSXLEN=32, the VSXL field does not exist, and VSXLEN=32. When HSXLEN=64,
 VSXL is a *WARL* field that is encoded the same as the MXL field of `misa`,
-shown in <<misabase>> on page <<misabase, 19>>. In particular, an
+shown in <<misabase>>. In particular, an
 implementation may make VSXL be a read-only field whose value always
 ensures that VSXLEN=HSXLEN.
 
@@ -726,6 +727,9 @@ When XLEN=32, `htimedeltah` is a 32-bit read/write register
 that aliases bits 63:32 of `htimedelta`.
 Register `htimedeltah` does not exist when XLEN=64.
 
+If the `time` CSR is implemented, `htimedelta` (and `htimedeltah` for XLEN=32)
+must be implemented.
+
 ==== Hypervisor Trap Value (`htval`) Register 
 
 The `htval` register is an HSXLEN-bit read/write register formatted as
@@ -935,7 +939,7 @@ in <<vsstatusreg-rv32>> when VSXLEN=32 and
 normally read or modify `sstatus` actually access `vsstatus` instead.
 
 [[vsstatusreg-rv32]]
-.Virtual supervisor status (`vstatus`) register when VSXLEN=32.
+.Virtual supervisor status (`vsstatus`) register when VSXLEN=32.
 [wavedrom, ,svg]
 ....
 {reg: [
@@ -1230,7 +1234,7 @@ controls the privilege level of the access. The explicit memory access
 is done as though in VU-mode when SPVP=0, and as though in VS-mode when
 SPVP=1. As usual when V=1, two-stage address translation is applied, and
 the HS-level `sstatus`.SUM is ignored. HS-level `sstatus`.MXR makes
-execute-only pages readable for both stages of address translation
+execute-only pages readable by explicit loads for both stages of address translation
 (VS-stage and G-stage), whereas `vsstatus`.MXR affects only the first
 translation stage (VS-stage).
 
@@ -1598,7 +1602,7 @@ there is no option to disable two-stage address translation when V=1,
 either stage of translation can be effectively disabled by zeroing the
 corresponding `vsatp` or `hgatp` register.
 
-The `vsstatus` field MXR, which makes execute-only pages readable, only
+The `vsstatus` field MXR, which makes execute-only pages readable by explicit loads, only
 overrides VS-stage page protection. Setting MXR at VS-level does not
 override guest-physical page protections. Setting MXR at HS-level,
 however, overrides both VS-stage and G-stage execute-only permissions.
@@ -2478,7 +2482,7 @@ with the encodings of basic loads and stores, as illustrated by
 <<pseudoinsts-basis>>.
 
 [[pseudoinsts-basis]]
-.Standard instructions corresponding to the special psudoinstructions of <<pseudoinsts>>.
+.Standard instructions corresponding to the special pseudoinstructions of <<pseudoinsts>>.
 [%autowidth,float="center",align="center",cols="<,<",options="header"]
 |===
 |Encoding |Instruction
diff --git a/src/images/bytefield/hypv-miereg-standard.edn b/src/images/bytefield/hypv-miereg-standard.edn
index 154983d..e2b60ab 100644
--- a/src/images/bytefield/hypv-miereg-standard.edn
+++ b/src/images/bytefield/hypv-miereg-standard.edn
@@ -8,9 +8,9 @@
 (def boxes-per-row 32)
 
 (draw-box "15" {:borders {}})
-(draw-box nil {:span 2 :borders {}})
-(draw-box "13" {:borders {}})
-(draw-box "12" {:span 3 :borders {}})
+(draw-box "14" {:borders {}})
+(draw-box "13" {:span 3 :borders {}})
+(draw-box "12" {:span 2 :borders {}})
 (draw-box "11" {:span 2 :borders {}})
 (draw-box "10" {:span 3 :borders {}})
 (draw-box "9" {:span 2 :borders {}})
@@ -24,8 +24,9 @@
 (draw-box "1" {:span 2 :borders {}})
 (draw-box "0" {:span 2 :borders {}})
 
-(draw-box "0" {:span 4})
-(draw-box "SGEIE" {:span 3})
+(draw-box "0" {:span 2})
+(draw-box "LCOFIE" {:span 3})
+(draw-box "SGEIE" {:span 2})
 (draw-box "MEIE" {:span 2})
 (draw-box "VSEIE" {:span 3})
 (draw-box "SEIE" {:span 2})
@@ -39,8 +40,9 @@
 (draw-box "SSIE" {:span 2})
 (draw-box "0" {:span 2})
 
-(draw-box "3" {:span 4 :borders {}})
-(draw-box "1" {:span 3:borders {}})
+(draw-box "2" {:span 2 :borders {}})
+(draw-box "1" {:span 3 :borders {}})
+(draw-box "1" {:span 2 :borders {}})
 (draw-box "1" {:span 2 :borders {}})
 (draw-box "1" {:span 3 :borders {}})
 (draw-box "1" {:span 2 :borders {}})
diff --git a/src/images/bytefield/hypv-mipreg-standard.edn b/src/images/bytefield/hypv-mipreg-standard.edn
index c75ec02..f41a1ba 100644
--- a/src/images/bytefield/hypv-mipreg-standard.edn
+++ b/src/images/bytefield/hypv-mipreg-standard.edn
@@ -8,9 +8,9 @@
 (def boxes-per-row 32)
 
 (draw-box "15" {:borders {}})
-(draw-box nil {:span 2 :borders {}})
-(draw-box "13" {:borders {}})
-(draw-box "12" {:span 3 :borders {}})
+(draw-box "14" {:borders {}})
+(draw-box "13" {:span 3 :borders {}})
+(draw-box "12" {:span 2 :borders {}})
 (draw-box "11" {:span 2 :borders {}})
 (draw-box "10" {:span 3 :borders {}})
 (draw-box "9" {:span 2 :borders {}})
@@ -24,8 +24,9 @@
 (draw-box "1" {:span 2 :borders {}})
 (draw-box "0" {:span 2 :borders {}})
 
-(draw-box "0" {:span 4})
-(draw-box "SGEIP" {:span 3})
+(draw-box "0" {:span 2})
+(draw-box "LCOFIP" {:span 3})
+(draw-box "SGEIP" {:span 2})
 (draw-box "MEIP" {:span 2})
 (draw-box "VSEIP" {:span 3})
 (draw-box "SEIP" {:span 2})
@@ -39,8 +40,9 @@
 (draw-box "SSIP" {:span 2})
 (draw-box "0" {:span 2})
 
-(draw-box "3" {:span 4 :borders {}})
-(draw-box "1" {:span 3:borders {}})
+(draw-box "2" {:span 2 :borders {}})
+(draw-box "1" {:span 3 :borders {}})
+(draw-box "1" {:span 2 :borders {}})
 (draw-box "1" {:span 2 :borders {}})
 (draw-box "1" {:span 3 :borders {}})
 (draw-box "1" {:span 2 :borders {}})
diff --git a/src/images/bytefield/rvc-instr-quad1.adoc b/src/images/bytefield/rvc-instr-quad1.adoc
index e0f6073..3aebd40 100644
--- a/src/images/bytefield/rvc-instr-quad1.adoc
+++ b/src/images/bytefield/rvc-instr-quad1.adoc
@@ -14,7 +14,7 @@
 (draw-box "0" {:span 5})
 (draw-box "imm[4:0]" {:span 5})
 (draw-box "01" {:span 2})
-(draw-box (text "C.NOP" :math [:sub "(HINT, imm=0)"]) {:span 3 :text-anchor "start" :borders {}})
+(draw-box (text "C.NOP" :math [:sub "(HINT, imm≠0)"]) {:span 3 :text-anchor "start" :borders {}})
 
 (draw-box "000" {:span 3})
 (draw-box "imm[5]") {:span 1}
diff --git a/src/images/wavedrom/atomic-mem.adoc b/src/images/wavedrom/atomic-mem.adoc
deleted file mode 100644
index ef66028..0000000
--- a/src/images/wavedrom/atomic-mem.adoc
+++ /dev/null
@@ -1,15 +0,0 @@
-//## 9.4 Atomic Memory Operations
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7, name: 'opcode',     type: 8, attr: ['7','AMO','AMO','AMO','AMO','AMO','AMO','AMO']},
-  {bits: 5, name: 'rd',         type: 2, attr: ['5','dest','dest','dest','dest','dest','dest','dest']},
-  {bits: 3, name: 'funct3',     type: 8, attr: ['3','width','width','width','width','width','width','width']},
-  {bits: 5, name: 'rs1',        type: 4, attr: ['5','addr','addr','addr','addr','addr','addr','addr']},
-  {bits: 5, name: 'rs2',        type: 4, attr: ['5','src','src','src','src','src','src','src']},
-  {bits: 1, name: 'rl',         type: 8, attr: ['1']},
-  {bits: 1, name: 'aq',         type: 8, attr: ['1']},
-  {bits: 6, name: 'funct5',     type: 8, attr: ['5','AMOSWAP.W/D', 'AMOADD.W/D', 'AMOAND.W/D', 'AMOOR.W/D', 'AMOXOR.W/D', 'AMOMAX[U].W/D','AMOMIN[U].W/D']},
-], config: {bits: 32}}
-....
diff --git a/src/images/wavedrom/atomic-mem.edn b/src/images/wavedrom/atomic-mem.edn
new file mode 100644
index 0000000..1e95eb4
--- /dev/null
+++ b/src/images/wavedrom/atomic-mem.edn
@@ -0,0 +1,15 @@
+//## 9.4 Atomic Memory Operations
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7, name: 'opcode',     attr: ['7','AMO','AMO','AMO','AMO','AMO','AMO','AMO']},
+  {bits: 5, name: 'rd',         attr: ['5','dest','dest','dest','dest','dest','dest','dest']},
+  {bits: 3, name: 'funct3',     attr: ['3','width','width','width','width','width','width','width']},
+  {bits: 5, name: 'rs1',        attr: ['5','addr','addr','addr','addr','addr','addr','addr']},
+  {bits: 5, name: 'rs2',        attr: ['5','src','src','src','src','src','src','src']},
+  {bits: 1, name: 'rl',         attr: ['1']},
+  {bits: 1, name: 'aq',         attr: ['1']},
+  {bits: 6, name: 'funct5',     attr: ['5','AMOSWAP.W/D', 'AMOADD.W/D', 'AMOAND.W/D', 'AMOOR.W/D', 'AMOXOR.W/D', 'AMOMAX[U].W/D','AMOMIN[U].W/D']},
+], config: {bits: 32}}
+....
diff --git a/src/images/wavedrom/b-immediate.edn b/src/images/wavedrom/b-immediate.edn
new file mode 100644
index 0000000..fcf9aad
--- /dev/null
+++ b/src/images/wavedrom/b-immediate.edn
@@ -0,0 +1,12 @@
+//#### B-immediate
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 1,  name: '0'},
+  {bits: 4,  name: 'inst[11:8]'},
+  {bits: 6,  name: 'inst[30:25]'},
+  {bits: 1,  name: '[7]'},
+  {bits: 20, name: '— inst[31] —'},
+], config:{fontsize: 12, label:{right: 'B-immediate'}}}
+....
+\ No newline at end of file
diff --git a/src/images/wavedrom/c-andi.adoc b/src/images/wavedrom/c-andi.adoc
deleted file mode 100644
index 5eca644..0000000
--- a/src/images/wavedrom/c-andi.adoc
+++ /dev/null
@@ -1,13 +0,0 @@
-//c-andi.adoc
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 2, name: 'op',    type: 5, attr: ['2','C1'],},
-  {bits: 5, name: 'imm[4:0]',    type: 5, attr: ['5','imm[4:0]']},
-  {bits: 3, name: 'rd′/rs1′',    type: 5, attr: ['3','dest'],},
-  {bits: 2, name: 'funct2',     type: 5, attr: ['2','C.ANDI'],},
-  {bits: 1, name: 'imm[5]',    type: 1, attr: ['1','imm[5]'],},
-  {bits: 3, name: 'funct3', type: 5, attr: ['3','C.ANDI'],},
-]}
-....
-\ No newline at end of file
diff --git a/src/images/wavedrom/c-andi.edn b/src/images/wavedrom/c-andi.edn
new file mode 100644
index 0000000..3ea3206
--- /dev/null
+++ b/src/images/wavedrom/c-andi.edn
@@ -0,0 +1,13 @@
+//c-andi.adoc
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 2, name: 'op',    attr: ['2','C1'],},
+  {bits: 5, name: 'imm[4:0]',    attr: ['5','imm[4:0]']},
+  {bits: 3, name: 'rd′/rs1′',    attr: ['3','dest'],},
+  {bits: 2, name: 'funct2',     attr: ['2','C.ANDI'],},
+  {bits: 1, name: 'imm[5]',    attr: ['1','imm[5]'],},
+  {bits: 3, name: 'funct3', attr: ['3','C.ANDI'],},
+]}
+....
+\ No newline at end of file
diff --git a/src/images/wavedrom/c-breakpoint-instr.adoc b/src/images/wavedrom/c-breakpoint-instr.adoc
deleted file mode 100644
index 99ae2d5..0000000
--- a/src/images/wavedrom/c-breakpoint-instr.adoc
+++ /dev/null
@@ -1,11 +0,0 @@
-//
-
-[wavedrom, ,svg]
-
-....
-{reg: [
-  {bits: 2, name: 'op', type: 8, attr: ['2','C2'],},
-  {bits: 10, name: '0', type: 4, attr: ['10','0'],},
-  {bits: 4, name: 'funct4', type: 8, attr: ['4','C.EBREAK'],},
-], config: {bits: 16}}
-....
-\ No newline at end of file
diff --git a/src/images/wavedrom/c-breakpoint-instr.edn b/src/images/wavedrom/c-breakpoint-instr.edn
new file mode 100644
index 0000000..6ae1890
--- /dev/null
+++ b/src/images/wavedrom/c-breakpoint-instr.edn
@@ -0,0 +1,11 @@
+//
+
+[wavedrom, ,svg]
+
+....
+{reg: [
+  {bits: 2, name: 'op', attr: ['2','C2'],},
+  {bits: 10, name: '0', attr: ['10','0'],},
+  {bits: 4, name: 'funct4', attr: ['4','C.EBREAK'],},
+], config: {bits: 16}}
+....
+\ No newline at end of file
diff --git a/src/images/wavedrom/c-cb-format-ls.adoc b/src/images/wavedrom/c-cb-format-ls.adoc
deleted file mode 100644
index daf2248..0000000
--- a/src/images/wavedrom/c-cb-format-ls.adoc
+++ /dev/null
@@ -1,13 +0,0 @@
-//c-cb-format-ls
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 2, name: 'op', type: 8, attr: ['2','C1', 'C1']},
-  {bits: 5, name: 'imm', type: 3, attr: ['5','offset[7:6|2:1|5]', 'offset[7:6|2:1|5]']},
-  {bits: 3, name: 'rs1′',     type: 4, attr: ['3','src', 'src']},
-  {bits: 3, name: 'imm',    type: 3, attr: ['3','offset[8|4:3]', 'offset[8|4:3]'],},
-  {bits: 3, name: 'funct3',    type: 8, attr: ['3','C.BEQZ', 'C.BNEZ'],},
-], config: {bits: 16}}
-....
-
diff --git a/src/images/wavedrom/c-cb-format-ls.edn b/src/images/wavedrom/c-cb-format-ls.edn
new file mode 100644
index 0000000..5c90133
--- /dev/null
+++ b/src/images/wavedrom/c-cb-format-ls.edn
@@ -0,0 +1,13 @@
+//c-cb-format-ls
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 2, name: 'op', attr: ['2','C1', 'C1']},
+  {bits: 5, name: 'imm', attr: ['5','offset[7:6|2:1|5]', 'offset[7:6|2:1|5]']},
+  {bits: 3, name: 'rs1′',     attr: ['3','src', 'src']},
+  {bits: 3, name: 'imm',    attr: ['3','offset[8|4:3]', 'offset[8|4:3]'],},
+  {bits: 3, name: 'funct3',    attr: ['3','C.BEQZ', 'C.BNEZ'],},
+], config: {bits: 16}}
+....
+
diff --git a/src/images/wavedrom/c-ci.adoc b/src/images/wavedrom/c-ci.adoc
deleted file mode 100644
index 7dae51e..0000000
--- a/src/images/wavedrom/c-ci.adoc
+++ /dev/null
@@ -1,13 +0,0 @@
-//
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 2, name: 'op', type: 3, attr: ['2', 'C2']},
-  {bits: 5, name: 'shamt[4:0]',    type: 1, attr: ['5', 'shamt[4:0]']},
-  {bits: 5, name: 'rd/rs1',     type: 5, attr: ['5', 'dest != 0']},
-  {bits: 1, name: 'shamt[5]',    type: 5, attr: ['1', 'shamt[5]']},
-  {bits: 3, name: 'funct3',    type: 5, attr: ['3', 'C.SLLI']},
-]}
-....
-
diff --git a/src/images/wavedrom/c-ci.edn b/src/images/wavedrom/c-ci.edn
new file mode 100644
index 0000000..aacf2be
--- /dev/null
+++ b/src/images/wavedrom/c-ci.edn
@@ -0,0 +1,13 @@
+//
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 2, name: 'op', attr: ['2', 'C2']},
+  {bits: 5, name: 'shamt[4:0]',    attr: ['5', 'shamt[4:0]']},
+  {bits: 5, name: 'rd/rs1',     attr: ['5', 'dest != 0']},
+  {bits: 1, name: 'shamt[5]',    attr: ['1', 'shamt[5]']},
+  {bits: 3, name: 'funct3',    attr: ['3', 'C.SLLI']},
+]}
+....
+
diff --git a/src/images/wavedrom/c-ciw.adoc b/src/images/wavedrom/c-ciw.adoc
deleted file mode 100644
index 111b272..0000000
--- a/src/images/wavedrom/c-ciw.adoc
+++ /dev/null
@@ -1,12 +0,0 @@
-//c-ciw.adoc
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 2, name: 'op', type: 3, attr: ['2','C0'],},
-  {bits: 3, name: 'rd′',     type: 5, attr: ['3','dest'],},
-  {bits: 8, name: 'imm',    type: 5, attr: ['8','nzuimm[5:4|9:6|2|3]']},
-  {bits: 3, name: 'funct3',    type: 5, attr: ['3','C.ADDI4SPN']},
-], config: {bits: 16}}
-....
-
diff --git a/src/images/wavedrom/c-ciw.edn b/src/images/wavedrom/c-ciw.edn
new file mode 100644
index 0000000..b167e1f
--- /dev/null
+++ b/src/images/wavedrom/c-ciw.edn
@@ -0,0 +1,12 @@
+//c-ciw.adoc
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 2, name: 'op', attr: ['2','C0'],},
+  {bits: 3, name: 'rd′',     attr: ['3','dest'],},
+  {bits: 8, name: 'imm',    attr: ['8','nzuimm[5:4|9:6|2|3]']},
+  {bits: 3, name: 'funct3',    attr: ['3','C.ADDI4SPN']},
+], config: {bits: 16}}
+....
+
diff --git a/src/images/wavedrom/c-cj-format-ls.adoc b/src/images/wavedrom/c-cj-format-ls.adoc
deleted file mode 100644
index 1ecbd35..0000000
--- a/src/images/wavedrom/c-cj-format-ls.adoc
+++ /dev/null
@@ -1,23 +0,0 @@
-//c-cj-format-ls
-
-//[wavedrom, ,svg]
-//....
-//{reg: [
-//	{bits: 2,  name: 'op', 		type: 4,  attr: ['2','CI','CI']},
-//	{bits: 10, name: 'imm',		type: 2,  },
-//	{bits: 4,  name: 'funct3' 	type: 4,  attr:['3','CJ','CJAL']},
-//] config: {bits: 16}}
-//....
-
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 2, name: 'op',     type: 8, attr: ['2','C1','C1']},
-  {bits: 11, name: 'imm',   type: 2, attr: ['11','offset[11|4|9:8|10|6|7|3:1|5]','offset[11|4|9:8|10|6|7|3:1|5]']},
-  {bits: 3, name: 'funct3', type: 8, attr: ['3','C.J','C.JAL']},
-], config: {bits: 16}}
-....
-
-
-
diff --git a/src/images/wavedrom/c-cj-format-ls.edn b/src/images/wavedrom/c-cj-format-ls.edn
new file mode 100644
index 0000000..d5fa6d1
--- /dev/null
+++ b/src/images/wavedrom/c-cj-format-ls.edn
@@ -0,0 +1,23 @@
+//c-cj-format-ls
+
+//[wavedrom, ,svg]
+//....
+//{reg: [
+//	{bits: 2,  name: 'op', attr: ['2','CI','CI']},
+//	{bits: 10, name: 'imm'},
+//	{bits: 4,  name: 'funct3' attr:['3','CJ','CJAL']},
+//] config: {bits: 16}}
+//....
+
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 2, name: 'op',     attr: ['2','C1','C1']},
+  {bits: 11, name: 'imm',   attr: ['11','offset[11|4|9:8|10|6|7|3:1|5]','offset[11|4|9:8|10|6|7|3:1|5]']},
+  {bits: 3, name: 'funct3', attr: ['3','C.J','C.JAL']},
+], config: {bits: 16}}
+....
+
+
+
diff --git a/src/images/wavedrom/c-cr-format-ls.adoc b/src/images/wavedrom/c-cr-format-ls.adoc
deleted file mode 100644
index 0329261..0000000
--- a/src/images/wavedrom/c-cr-format-ls.adoc
+++ /dev/null
@@ -1,12 +0,0 @@
-//These instructions use the CR format.
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 2, name: 'op', type: 8, attr: ['2','C2', 'C2']},
-  {bits: 5, name: 'rs2',     type: 4, attr: ['5','0', '0']},
-  {bits: 5, name: 'rs1',     type: 4, attr: ['5','src≠0', 'src≠0']},
-  {bits: 4, name: 'funct4',  type: 8, attr: ['4','C.JR', 'C.JALR']},
-], config: {bits: 16}}
-....
-
diff --git a/src/images/wavedrom/c-cr-format-ls.edn b/src/images/wavedrom/c-cr-format-ls.edn
new file mode 100644
index 0000000..b989e2c
--- /dev/null
+++ b/src/images/wavedrom/c-cr-format-ls.edn
@@ -0,0 +1,12 @@
+//These instructions use the CR format.
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 2, name: 'op', attr: ['2','C2', 'C2']},
+  {bits: 5, name: 'rs2',     attr: ['5','0', '0']},
+  {bits: 5, name: 'rs1',     attr: ['5','src≠0', 'src≠0']},
+  {bits: 4, name: 'funct4',  attr: ['4','C.JR', 'C.JALR']},
+], config: {bits: 16}}
+....
+
diff --git a/src/images/wavedrom/c-cs-format-ls.adoc b/src/images/wavedrom/c-cs-format-ls.adoc
deleted file mode 100644
index 1f759a7..0000000
--- a/src/images/wavedrom/c-cs-format-ls.adoc
+++ /dev/null
@@ -1,16 +0,0 @@
-//## 16.X Load and Store Instructions
-//### c-cs-format-ls
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 2, name: 'op',     type: 8, attr: ['2', 'C0','C0','C0','C0','C0']},
-  {bits: 3, name: 'rs2ʹ',   type: 3, attr: ['3', 'src','src','src','src','src']},
-  {bits: 2, name: 'imm',    type: 2, attr: ['2', 'offset[2|6]','offset[7:6]','offset[7:6]','offset[2|6]','offset[7:6]']},
-  {bits: 3, name: 'rs1ʹ',   type: 3, attr: ['3', 'base','base','base','base','base']},
-  {bits: 3, name: 'imm',    type: 3, attr: ['3', 'offset[5:3]','offset[5:3]','offset[5|4|8]','offset[5:3]','offset[5:3]']},
-  {bits: 3, name: 'funct3', type: 8, attr: ['3', 'C.SW','C.SD','C.SQ','C.FSW','C.FSD']},
-], config: {bits: 16}}
-....
-
-
diff --git a/src/images/wavedrom/c-cs-format-ls.edn b/src/images/wavedrom/c-cs-format-ls.edn
new file mode 100644
index 0000000..31f4ccf
--- /dev/null
+++ b/src/images/wavedrom/c-cs-format-ls.edn
@@ -0,0 +1,16 @@
+//## 16.X Load and Store Instructions
+//### c-cs-format-ls
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 2, name: 'op',     attr: ['2', 'C0','C0','C0','C0','C0']},
+  {bits: 3, name: 'rs2ʹ',   attr: ['3', 'src','src','src','src','src']},
+  {bits: 2, name: 'imm',    attr: ['2', 'offset[2|6]','offset[7:6]','offset[7:6]','offset[2|6]','offset[7:6]']},
+  {bits: 3, name: 'rs1ʹ',   attr: ['3', 'base','base','base','base','base']},
+  {bits: 3, name: 'imm',    attr: ['3', 'offset[5:3]','offset[5:3]','offset[5|4|8]','offset[5:3]','offset[5:3]']},
+  {bits: 3, name: 'funct3', attr: ['3', 'C.SW','C.SD','C.SQ','C.FSW','C.FSD']},
+], config: {bits: 16}}
+....
+
+
diff --git a/src/images/wavedrom/c-def-illegal-inst.adoc b/src/images/wavedrom/c-def-illegal-inst.adoc
deleted file mode 100644
index add949d..0000000
--- a/src/images/wavedrom/c-def-illegal-inst.adoc
+++ /dev/null
@@ -1,13 +0,0 @@
-//
-
-[wavedrom, ,svg]
-
-....
-{reg: [
-  {bits: 2, name: '0', type: 8, attr: ['2','0'],},
-  {bits: 5, name: '0', type: 4, attr: ['5','0'],},
-  {bits: 5, name: '0', type: 8, attr: ['5','0'],},
-  {bits: 1, name: '0', type: 8, attr: ['1','0'],},
-  {bits: 3, name: '0', type: 8, attr: ['3','0'],},
-], config: {bits: 16}}
-....
-\ No newline at end of file
diff --git a/src/images/wavedrom/c-def-illegal-inst.edn b/src/images/wavedrom/c-def-illegal-inst.edn
new file mode 100644
index 0000000..414a19e
--- /dev/null
+++ b/src/images/wavedrom/c-def-illegal-inst.edn
@@ -0,0 +1,13 @@
+//
+
+[wavedrom, ,svg]
+
+....
+{reg: [
+  {bits: 2, name: '0', attr: ['2','0'],},
+  {bits: 5, name: '0', attr: ['5','0'],},
+  {bits: 5, name: '0', attr: ['5','0'],},
+  {bits: 1, name: '0', attr: ['1','0'],},
+  {bits: 3, name: '0', attr: ['3','0'],},
+], config: {bits: 16}}
+....
+\ No newline at end of file
diff --git a/src/images/wavedrom/c-int-reg-immed.adoc b/src/images/wavedrom/c-int-reg-immed.adoc
deleted file mode 100644
index 45168d7..0000000
--- a/src/images/wavedrom/c-int-reg-immed.adoc
+++ /dev/null
@@ -1,12 +0,0 @@
-//c-int-reg-immed.adoc
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 2, name: 'op',        type: 3, attr: ['2','C1', 'C1', 'C1']},
-  {bits: 5, name: 'imm[4:]',  type: 1, attr: ['5','nzimm[4:0]', 'imm[4:0]', 'nzimm[4|6|8:7|5]']},
-  {bits: 5, name: 'rd/rs1',    type: 5, attr: ['5','dest != 0', 'dest != 0', '2']},
-  {bits: 1, name: 'imm[5]',    type: 5, attr: ['1','nzimm[5]', 'imm[5]', 'nzimm[9]']},
-  {bits: 3, name: 'funct3',    type: 5, attr: ['3','C.ADDI', 'C.ADDIW', 'C.ADDI16SP']},
-], config: {bits: 16}}
-....
diff --git a/src/images/wavedrom/c-int-reg-immed.edn b/src/images/wavedrom/c-int-reg-immed.edn
new file mode 100644
index 0000000..f509065
--- /dev/null
+++ b/src/images/wavedrom/c-int-reg-immed.edn
@@ -0,0 +1,12 @@
+//c-int-reg-immed.adoc
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 2, name: 'op',        attr: ['2','C1', 'C1', 'C1']},
+  {bits: 5, name: 'imm[4:]',  attr: ['5','nzimm[4:0]', 'imm[4:0]', 'nzimm[4|6|8:7|5]']},
+  {bits: 5, name: 'rd/rs1',    attr: ['5','dest != 0', 'dest != 0', '2']},
+  {bits: 1, name: 'imm[5]',    attr: ['1','nzimm[5]', 'imm[5]', 'nzimm[9]']},
+  {bits: 3, name: 'funct3',    attr: ['3','C.ADDI', 'C.ADDIW', 'C.ADDI16SP']},
+], config: {bits: 16}}
+....
diff --git a/src/images/wavedrom/c-int-reg-to-reg-ca-format.adoc b/src/images/wavedrom/c-int-reg-to-reg-ca-format.adoc
deleted file mode 100644
index b2cf982..0000000
--- a/src/images/wavedrom/c-int-reg-to-reg-ca-format.adoc
+++ /dev/null
@@ -1,13 +0,0 @@
-//
-
-[wavedrom, ,svg]
-
-....
-{reg: [
-  {bits: 2, name: 'op',     type: 8, attr: ['2', 'C1', 'C1', 'C1', 'C1', 'C1', 'C1'],},
-  {bits: 3, name: 'rs2′',    type: 4, attr: ['3', 'src', 'src', 'src', 'src', 'src', 'src'],},
-  {bits: 2, name: 'funct2', type: 8, attr: ['2', 'C.AND', 'C.OR', 'C.XOR', 'C.SUB', 'C.ADDW', 'C.SUBW'],},
-  {bits: 3, name: 'rd′/rs1′', type: 7, attr: ['3', 'dest', 'dest', 'dest', 'dest', 'dest', 'dest'],},
-  {bits: 6, name: 'funct6', type: 8, attr: ['6', 'C.AND', 'C.OR', 'C.XOR', 'C.SUB', 'C.ADDW', 'C.SUBW'],},
-]} 
-....
-\ No newline at end of file
diff --git a/src/images/wavedrom/c-int-reg-to-reg-ca-format.edn b/src/images/wavedrom/c-int-reg-to-reg-ca-format.edn
new file mode 100644
index 0000000..67e77b0
--- /dev/null
+++ b/src/images/wavedrom/c-int-reg-to-reg-ca-format.edn
@@ -0,0 +1,13 @@
+//
+
+[wavedrom, ,svg]
+
+....
+{reg: [
+  {bits: 2, name: 'op',     attr: ['2', 'C1', 'C1', 'C1', 'C1', 'C1', 'C1'],},
+  {bits: 3, name: 'rs2′',    attr: ['3', 'src', 'src', 'src', 'src', 'src', 'src'],},
+  {bits: 2, name: 'funct2', attr: ['2', 'C.AND', 'C.OR', 'C.XOR', 'C.SUB', 'C.ADDW', 'C.SUBW'],},
+  {bits: 3, name: 'rd′/rs1′', attr: ['3', 'dest', 'dest', 'dest', 'dest', 'dest', 'dest'],},
+  {bits: 6, name: 'funct6', attr: ['6', 'C.AND', 'C.OR', 'C.XOR', 'C.SUB', 'C.ADDW', 'C.SUBW'],},
+]} 
+....
+\ No newline at end of file
diff --git a/src/images/wavedrom/c-int-reg-to-reg-cr-format.adoc b/src/images/wavedrom/c-int-reg-to-reg-cr-format.adoc
deleted file mode 100644
index 5e607f8..0000000
--- a/src/images/wavedrom/c-int-reg-to-reg-cr-format.adoc
+++ /dev/null
@@ -1,12 +0,0 @@
-//
-
-[wavedrom, ,svg]
-
-....
-{reg: [
-  {bits: 2, name: 'op',     type: 8, attr: ['2', 'C2', 'C2'],},
-  {bits: 5, name: 'rs2',    type: 4, attr: ['5', 'src≠0', 'src≠0'],},
-  {bits: 5, name: 'rd/rs1', type: 7, attr: ['5', 'dest≠0', 'dest≠0'],},
-  {bits: 4, name: 'funct4', type: 8, attr: ['4', 'C.MV', 'C.ADD'],},
-], config: {bits: 16}} 
-....
-\ No newline at end of file
diff --git a/src/images/wavedrom/c-int-reg-to-reg-cr-format.edn b/src/images/wavedrom/c-int-reg-to-reg-cr-format.edn
new file mode 100644
index 0000000..ddfa0f8
--- /dev/null
+++ b/src/images/wavedrom/c-int-reg-to-reg-cr-format.edn
@@ -0,0 +1,12 @@
+//
+
+[wavedrom, ,svg]
+
+....
+{reg: [
+  {bits: 2, name: 'op',     attr: ['2', 'C2', 'C2'],},
+  {bits: 5, name: 'rs2',    attr: ['5', 'src≠0', 'src≠0'],},
+  {bits: 5, name: 'rd/rs1', attr: ['5', 'dest≠0', 'dest≠0'],},
+  {bits: 4, name: 'funct4', attr: ['4', 'C.MV', 'C.ADD'],},
+], config: {bits: 16}} 
+....
+\ No newline at end of file
diff --git a/src/images/wavedrom/c-integer-const-gen.adoc b/src/images/wavedrom/c-integer-const-gen.adoc
deleted file mode 100644
index 732961b..0000000
--- a/src/images/wavedrom/c-integer-const-gen.adoc
+++ /dev/null
@@ -1,13 +0,0 @@
-//c-integer-const-gen
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 2, name: 'op', type: 3, attr: ['2','C1', 'C1']},
-  {bits: 5, name: 'imm[4:0]',    type: 1, attr: ['5','imm[4:0]','imm[16:12]']},
-  {bits: 5, name: 'rd',     type: 5, attr: ['5','dest != 0', 'dest != {0, 2}']},
-  {bits: 1, name: 'imm[5]',    type: 5, attr: ['1','imm[5]', 'nzimm[17]'],},
-  {bits: 3, name: 'funct3',    type: 5, attr: ['3','C.LI', 'C.LUI'],},
-], config: {bits: 16}}
-....
-
diff --git a/src/images/wavedrom/c-integer-const-gen.edn b/src/images/wavedrom/c-integer-const-gen.edn
new file mode 100644
index 0000000..977ddb0
--- /dev/null
+++ b/src/images/wavedrom/c-integer-const-gen.edn
@@ -0,0 +1,13 @@
+//c-integer-const-gen
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 2, name: 'op', attr: ['2','C1', 'C1']},
+  {bits: 5, name: 'imm[4:0]',    attr: ['5','imm[4:0]','nzimm[16:12]']},
+  {bits: 5, name: 'rd',     attr: ['5','dest != 0', 'dest != {0, 2}']},
+  {bits: 1, name: 'imm[5]',    attr: ['1','imm[5]', 'nzimm[17]'],},
+  {bits: 3, name: 'funct3',    attr: ['3','C.LI', 'C.LUI'],},
+], config: {bits: 16}}
+....
+
diff --git a/src/images/wavedrom/c-mop.adoc b/src/images/wavedrom/c-mop.adoc
deleted file mode 100644
index 0aee8e4..0000000
--- a/src/images/wavedrom/c-mop.adoc
+++ /dev/null
@@ -1,12 +0,0 @@
-[wavedrom, ,svg]
-....
-{reg:[
-    { bits:  2, name: 0x1, type: 8 },
-    { bits:  5, name: 0x0 },
-    { bits:  1, name: 0x1, type: 4 },
-    { bits:  3, name: 'n[3:1]', type: 4 },
-    { bits:  1, name: 0x0, type: 4 },
-    { bits:  1, name: 0x0 },
-    { bits:  3, name: 0x3 },
-]}
-....
diff --git a/src/images/wavedrom/c-mop.edn b/src/images/wavedrom/c-mop.edn
new file mode 100644
index 0000000..9b850a5
--- /dev/null
+++ b/src/images/wavedrom/c-mop.edn
@@ -0,0 +1,12 @@
+[wavedrom, ,svg]
+....
+{reg:[
+    { bits:  2, name: 0x1 },
+    { bits:  5, name: 0x0 },
+    { bits:  1, name: 0x1 },
+    { bits:  3, name: 'n[3:1]' },
+    { bits:  1, name: 0x0 },
+    { bits:  1, name: 0x0 },
+    { bits:  3, name: 0x3 },
+]}
+....
diff --git a/src/images/wavedrom/c-nop-instr.adoc b/src/images/wavedrom/c-nop-instr.adoc
deleted file mode 100644
index e3fada1..0000000
--- a/src/images/wavedrom/c-nop-instr.adoc
+++ /dev/null
@@ -1,13 +0,0 @@
-//
-
-[wavedrom, ,svg]
-
-....
-{reg: [
-  {bits: 2, name: 'op', type: 8, attr: ['2','C1'],},
-  {bits: 5, name: 'imm[4:0]', type: 4, attr: ['5','0'],},
-  {bits: 5, name: 'rd/rs1', type: 8, attr: ['5','0'],},
-  {bits: 1, name: 'imm[5]', type: 8, attr: ['1','0'],},
-  {bits: 3, name: 'funct3', type: 8, attr: ['3','C.NOP'],},
-]}
-....
-\ No newline at end of file
diff --git a/src/images/wavedrom/c-nop-instr.edn b/src/images/wavedrom/c-nop-instr.edn
new file mode 100644
index 0000000..89da752
--- /dev/null
+++ b/src/images/wavedrom/c-nop-instr.edn
@@ -0,0 +1,13 @@
+//
+
+[wavedrom, ,svg]
+
+....
+{reg: [
+  {bits: 2, name: 'op', attr: ['2','C1'],},
+  {bits: 5, name: 'imm[4:0]', attr: ['5','0'],},
+  {bits: 5, name: 'rd/rs1', attr: ['5','0'],},
+  {bits: 1, name: 'imm[5]', attr: ['1','0'],},
+  {bits: 3, name: 'funct3', attr: ['3','C.NOP'],},
+]}
+....
+\ No newline at end of file
diff --git a/src/images/wavedrom/c-sp-load-store-css.adoc b/src/images/wavedrom/c-sp-load-store-css.adoc
deleted file mode 100644
index 2cafcd8..0000000
--- a/src/images/wavedrom/c-sp-load-store-css.adoc
+++ /dev/null
@@ -1,14 +0,0 @@
-//c-sp load and store, css format--is this correct?
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 2, name: 'op',     type: 8, attr: ['2','C2','C2','C2','C2','C2']},
-  {bits: 5, name: 'rs2',    type: 4, attr: ['5','src', 'src', 'src', 'src', 'src']},
-  {bits: 6, name: 'imm',    type: 3, attr: ['6','offset[5:2|7:6]', 'offset[5:3|8:6]', 'offset[5:4|9:6]', 'offset[5:2|7:6]','offset[5:3|8:6]']},
-  {bits: 3, name: 'funct3', type: 8, attr: ['3','C.SWSP', 'C.SDSP', 'C.SQSP', 'C.FSWSP', 'C.FSDSP']},
-], config: {bits: 16}}
-....
-
-
-
diff --git a/src/images/wavedrom/c-sp-load-store-css.edn b/src/images/wavedrom/c-sp-load-store-css.edn
new file mode 100644
index 0000000..a398c7f
--- /dev/null
+++ b/src/images/wavedrom/c-sp-load-store-css.edn
@@ -0,0 +1,14 @@
+//c-sp load and store, css format--is this correct?
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 2, name: 'op',     attr: ['2','C2','C2','C2','C2','C2']},
+  {bits: 5, name: 'rs2',    attr: ['5','src', 'src', 'src', 'src', 'src']},
+  {bits: 6, name: 'imm',    attr: ['6','offset[5:2|7:6]', 'offset[5:3|8:6]', 'offset[5:4|9:6]', 'offset[5:2|7:6]','offset[5:3|8:6]']},
+  {bits: 3, name: 'funct3', attr: ['3','C.SWSP', 'C.SDSP', 'C.SQSP', 'C.FSWSP', 'C.FSDSP']},
+], config: {bits: 16}}
+....
+
+
+
diff --git a/src/images/wavedrom/c-sp-load-store.adoc b/src/images/wavedrom/c-sp-load-store.adoc
deleted file mode 100644
index c39f2f6..0000000
--- a/src/images/wavedrom/c-sp-load-store.adoc
+++ /dev/null
@@ -1,15 +0,0 @@
-//## 16.3 Load and Store Instructions
-//### Stack-Pointer-Based Loads and Stores
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 2, name: 'op',     type: 8, attr: ['2','C2','C2','C2','C2','C2']},
-  {bits: 5, name: 'imm',    type: 5, attr: ['5','offset[4:2|7:6]', 'offset[4:3|8:6]', 'offset[4|9:6]', 'offset[4:2|7:6]', 'offset[4:3|8:6]']},
-  {bits: 5, name: 'rd',     type: 5, attr: ['5','dest≠0', 'dest≠0', 'dest≠0', 'dest', 'dest']},
-  {bits: 1, name: 'imm',    type: 1, attr: ['1','offset[5]','offset[5]','offset[5]','offset[5]','offset[5]']},
-  {bits: 3, name: 'funct3', type: 3, attr: ['3','C.LWSP', 'C.LDSP', 'C.LQSP', 'C.FLWSP', 'C.FLDSP']},
-], config: {bits: 16}}
-....
-
-
diff --git a/src/images/wavedrom/c-sp-load-store.edn b/src/images/wavedrom/c-sp-load-store.edn
new file mode 100644
index 0000000..f890ac8
--- /dev/null
+++ b/src/images/wavedrom/c-sp-load-store.edn
@@ -0,0 +1,15 @@
+//## 16.3 Load and Store Instructions
+//### Stack-Pointer-Based Loads and Stores
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 2, name: 'op',     attr: ['2','C2','C2','C2','C2','C2']},
+  {bits: 5, name: 'imm',    attr: ['5','offset[4:2|7:6]', 'offset[4:3|8:6]', 'offset[4|9:6]', 'offset[4:2|7:6]', 'offset[4:3|8:6]']},
+  {bits: 5, name: 'rd',     attr: ['5','dest≠0', 'dest≠0', 'dest≠0', 'dest', 'dest']},
+  {bits: 1, name: 'imm',    attr: ['1','offset[5]','offset[5]','offset[5]','offset[5]','offset[5]']},
+  {bits: 3, name: 'funct3', attr: ['3','C.LWSP', 'C.LDSP', 'C.LQSP', 'C.FLWSP', 'C.FLDSP']},
+], config: {bits: 16}}
+....
+
+
diff --git a/src/images/wavedrom/c-srli-srai.adoc b/src/images/wavedrom/c-srli-srai.adoc
deleted file mode 100644
index 557bb39..0000000
--- a/src/images/wavedrom/c-srli-srai.adoc
+++ /dev/null
@@ -1,13 +0,0 @@
-//c-srli-srai.adoc
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 2, name: 'op', type: 3, attr: ['2','C1', 'C1'],},
-  {bits: 5, name: 'shamt[4:0]',    type: 1, attr: ['5','shamt[4:0]', 'shamt[4:0]'],},
-  {bits: 3, name: 'rd′/rs1′',     type: 5, attr: ['3','dest', 'dest'],},
-  {bits: 2, name: 'funct2',    type: 5, attr: ['2','C.SRLI', 'C.SRAI'],},
-  {bits: 1, name: 'shamt[5]',    type: 5, attr: ['1','shamt[5]', 'shamt[5]'],},
-  {bits: 3, name: 'funct3',    type: 5, attr: ['3','C.SRLI', 'C.SRAI'],},
-]}
-....
-\ No newline at end of file
diff --git a/src/images/wavedrom/c-srli-srai.edn b/src/images/wavedrom/c-srli-srai.edn
new file mode 100644
index 0000000..78a1076
--- /dev/null
+++ b/src/images/wavedrom/c-srli-srai.edn
@@ -0,0 +1,13 @@
+//c-srli-srai.adoc
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 2, name: 'op', attr: ['2','C1', 'C1'],},
+  {bits: 5, name: 'shamt[4:0]',    attr: ['5','shamt[4:0]', 'shamt[4:0]'],},
+  {bits: 3, name: 'rd′/rs1′',     attr: ['3','dest', 'dest'],},
+  {bits: 2, name: 'funct2',    attr: ['2','C.SRLI', 'C.SRAI'],},
+  {bits: 1, name: 'shamt[5]',    attr: ['1','shamt[5]', 'shamt[5]'],},
+  {bits: 3, name: 'funct3',    attr: ['3','C.SRLI', 'C.SRAI'],},
+]}
+....
+\ No newline at end of file
diff --git a/src/images/wavedrom/counters-diag.adoc b/src/images/wavedrom/counters-diag.edn
index 8668162..a29d567 100644
--- a/src/images/wavedrom/counters-diag.adoc
+++ b/src/images/wavedrom/counters-diag.edn
@@ -4,11 +4,11 @@
 [wavedrom, ,svg]
 ....
 {reg: [
-  {bits: 7,  name: 'opcode', attr: ['7','SYSTEM','SYSTEM','SYSTEM'], type: 8},
-  {bits: 5,  name: 'rd',     attr: ['5','dest','dest','dest'],  type: 2},
-  {bits: 3,  name: 'funct3',  attr: ['3','CSRRS','CSRRS','CSRRS'],  type: 8},
-  {bits: 5,  name: 'rs1',    attr: ['5','0','0','0'], type: 8},
-  {bits: 12, name: 'csr',    attr: ['12','RDCYCLE[H]', 'RDTIME[H]','RDINSTRET[H]'], type: 4},
+  {bits: 7,  name: 'opcode', attr: ['7','SYSTEM','SYSTEM','SYSTEM']},
+  {bits: 5,  name: 'rd',     attr: ['5','dest','dest','dest']},
+  {bits: 3,  name: 'funct3',  attr: ['3','CSRRS','CSRRS','CSRRS']},
+  {bits: 5,  name: 'rs1',    attr: ['5','0','0','0']},
+  {bits: 12, name: 'csr',    attr: ['12','RDCYCLE[H]', 'RDTIME[H]','RDINSTRET[H]']},
 ]}
 ....
 
diff --git a/src/images/wavedrom/cr-register.adoc b/src/images/wavedrom/cr-register.adoc
deleted file mode 100644
index 63286e4..0000000
--- a/src/images/wavedrom/cr-register.adoc
+++ /dev/null
@@ -1,112 +0,0 @@
-//# 16 "C" Standard Extension for Compressed Instructions, Version 2.0
-//## 16.2 Compressed Instruction Formats
-//Table 16.1: Compressed 16-bit RVC instruction formats.
-//### CR : Register
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 2, name: 'op',     type: 8},
-  {bits: 5, name: 'rs2',    type: 4},
-  {bits: 5, name: 'rd/rs1', type: 7},
-  {bits: 4, name: 'funct4', type: 8},
-  ]}
-....
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 2, name: 'op',     type: 8},
-  {bits: 5, name: 'imm',    type: 3},
-  {bits: 5, name: 'rd/rs1', type: 7},
-  {bits: 1, name: 'imm',    type: 3},
-  {bits: 3, name: 'funct3', type: 8},
-]}
-....
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 2, name: 'op',     type: 8},
-  {bits: 5, name: 'rs2',    type: 4},
-  {bits: 6, name: 'imm',    type: 3},
-  {bits: 3, name: 'funct3', type: 8},
-]}
-....
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 2, name: 'op',     type: 8},
-  {bits: 3, name: 'rdʹ',    type: 2},
-  {bits: 8, name: 'imm',    type: 3},
-  {bits: 3, name: 'funct3', type: 8},
-]}
-....
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 2, name: 'op',     type: 8},
-  {bits: 3, name: 'rdʹ',    type: 2},
-  {bits: 2, name: 'imm',    type: 3},
-  {bits: 3, name: 'rs1ʹ',   type: 4},
-  {bits: 3, name: 'imm',    type: 3},
-  {bits: 3, name: 'funct3', type: 8},
-]}
-....
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 2, name: 'op',     type: 8},
-  {bits: 3, name: 'rs2ʹ',   type: 4},
-  {bits: 2, name: 'imm',    type: 3},
-  {bits: 3, name: 'rs1ʹ',   type: 4},
-  {bits: 3, name: 'imm',    type: 3},
-  {bits: 3, name: 'funct3', type: 8},
-]}
-....
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 2, name: 'op',     type: 8},
-  {bits: 3, name: 'rs2ʹ',   type: 4},
-  {bits: 2, name: 'funct2', type: 8},
-  {bits: 3, name: 'rdʹ/rs1ʹ',   type: 7},
-  {bits: 6, name: 'funct6', type: 8},
-]}
-....
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 2, name: 'op',     type: 8},
-  {bits: 5, name: 'offset', type: 3},
-  {bits: 3, name: 'rdʹ/rs1ʹ',   type: 7},
-  {bits: 3, name: 'offset', type: 3},
-  {bits: 3, name: 'funct3', type: 8},
-]}
-....
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 2,  name: 'op',     type: 8},
-  {bits: 11, name: 'jmp trgt', type: 3},
-  {bits: 3,  name: 'funct3', type: 8},
-]}
-....
-
-//the following configuration broke the build.
-//config: {
-//  hflip: true,
-//  compact: true,
-//  bits: 16 * 9, lanes: 9,
-//  margin: {right: width / 4},
-// label: {right: ['CR : Register', 'CI : Immediate', 'CSS : Stack-relative Store', 'CIW : Wide Immediate', 'CL : Load', 'CS //: Store', 'CA : //Arithmetic', 'CB : Branch/Arithmetic', 'CJ : Jump']}
-//}
-
-
-
diff --git a/src/images/wavedrom/cr-register.edn b/src/images/wavedrom/cr-register.edn
new file mode 100644
index 0000000..30ad1b3
--- /dev/null
+++ b/src/images/wavedrom/cr-register.edn
@@ -0,0 +1,112 @@
+//# 16 "C" Standard Extension for Compressed Instructions, Version 2.0
+//## 16.2 Compressed Instruction Formats
+//Table 16.1: Compressed 16-bit RVC instruction formats.
+//### CR : Register
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 2, name: 'op' },
+  {bits: 5, name: 'rs2' },
+  {bits: 5, name: 'rd/rs1' },
+  {bits: 4, name: 'funct4' },
+  ]}
+....
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 2, name: 'op' },
+  {bits: 5, name: 'imm' },
+  {bits: 5, name: 'rd/rs1' },
+  {bits: 1, name: 'imm' },
+  {bits: 3, name: 'funct3' },
+]}
+....
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 2, name: 'op' },
+  {bits: 5, name: 'rs2' },
+  {bits: 6, name: 'imm' },
+  {bits: 3, name: 'funct3' },
+]}
+....
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 2, name: 'op' },
+  {bits: 3, name: 'rdʹ' },
+  {bits: 8, name: 'imm' },
+  {bits: 3, name: 'funct3' },
+]}
+....
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 2, name: 'op' },
+  {bits: 3, name: 'rdʹ' },
+  {bits: 2, name: 'imm' },
+  {bits: 3, name: 'rs1ʹ' },
+  {bits: 3, name: 'imm' },
+  {bits: 3, name: 'funct3' },
+]}
+....
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 2, name: 'op' },
+  {bits: 3, name: 'rs2ʹ' },
+  {bits: 2, name: 'imm' },
+  {bits: 3, name: 'rs1ʹ' },
+  {bits: 3, name: 'imm' },
+  {bits: 3, name: 'funct3' },
+]}
+....
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 2, name: 'op' },
+  {bits: 3, name: 'rs2ʹ' },
+  {bits: 2, name: 'funct2' },
+  {bits: 3, name: 'rdʹ/rs1ʹ' },
+  {bits: 6, name: 'funct6' },
+]}
+....
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 2, name: 'op' },
+  {bits: 5, name: 'offset' },
+  {bits: 3, name: 'rdʹ/rs1ʹ' },
+  {bits: 3, name: 'offset' },
+  {bits: 3, name: 'funct3' },
+]}
+....
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 2,  name: 'op' },
+  {bits: 11, name: 'jmp trgt' },
+  {bits: 3,  name: 'funct3' },
+]}
+....
+
+//the following configuration broke the build.
+//config: {
+//  hflip: true,
+//  compact: true,
+//  bits: 16 * 9, lanes: 9,
+//  margin: {right: width / 4},
+// label: {right: ['CR : Register', 'CI : Immediate', 'CSS : Stack-relative Store', 'CIW : Wide Immediate', 'CL : Load', 'CS //: Store', 'CA : //Arithmetic', 'CB : Branch/Arithmetic', 'CJ : Jump']}
+//}
+
+
+
diff --git a/src/images/wavedrom/cr-registers-new.adoc b/src/images/wavedrom/cr-registers-new.adoc
deleted file mode 100644
index 46a34e6..0000000
--- a/src/images/wavedrom/cr-registers-new.adoc
+++ /dev/null
@@ -1,62 +0,0 @@
-[wavedrom, ,svg]
-....
-### CR : Register
-${wd({reg: [
-  {bits: 2, name: 'op',     type: 8},
-  {bits: 5, name: 'rs2',    type: 4},
-  {bits: 5, name: 'rd / rs1ʹ, type: 7},
-  {bits: 4, name: 'funct4', type: 8},
-
-  {bits: 2, name: 'op',     type: 8},
-  {bits: 5, name: 'imm',    type: 3},
-  {bits: 5, name: 'rd / rs1', type: 7},
-  {bits: 1, name: 'imm',    type: 3},
-  {bits: 3, name: 'funct3', type: 8},
-
-  {bits: 2, name: 'op',     type: 8},
-  {bits: 5, name: 'rs2',    type: 4},
-  {bits: 6, name: 'imm',    type: 3},
-  {bits: 3, name: 'funct3', type: 8},
-
-  {bits: 2, name: 'op',     type: 8},
-  {bits: 3, name: 'rdʹ',    type: 2},
-  {bits: 8, name: 'imm',    type: 3},
-  {bits: 3, name: 'funct3', type: 8},
-
-  {bits: 2, name: 'op',     type: 8},
-  {bits: 3, name: 'rdʹ',    type: 2},
-  {bits: 2, name: 'imm',    type: 3},
-  {bits: 3, name: 'rs1ʹ',   type: 4},
-  {bits: 3, name: 'imm',    type: 3},
-  {bits: 3, name: 'funct3', type: 8},
-
-  {bits: 2, name: 'op',     type: 8},
-  {bits: 3, name: 'rs2ʹ',   type: 4},
-  {bits: 2, name: 'imm',    type: 3},
-  {bits: 3, name: 'rs1ʹ',   type: 4},
-  {bits: 3, name: 'imm',    type: 3},
-  {bits: 3, name: 'funct3', type: 8},
-
-  {bits: 2, name: 'op',     type: 8},
-  {bits: 3, name: 'rs2ʹ',   type: 4},
-  {bits: 2, name: 'funct2', type: 8},
-  {bits: 3, name: 'rd` / rs1ʹ',   type: 7},
-  {bits: 6, name: 'funct6', type: 8},
-
-  {bits: 2, name: 'op',     type: 8},
-  {bits: 5, name: 'offset', type: 3},
-  {bits: 3, name: 'rd` / rs1ʹ',   type: 7},
-  {bits: 3, name: 'offset', type: 3},
-  {bits: 3, name: 'funct3', type: 8},
-
-  {bits: 2,  name: 'op',     type: 8},
-  {bits: 11, name: 'jump target', type: 3},
-  {bits: 3,  name: 'funct3', type: 8},
-], config: {
-  hflip: true,
-  compact: true,
-  bits: 16 * 9, lanes: 9,
-  margin: {right: width / 4},
-  label: {right: ['CR : Register', 'CI : Immediate', 'CSS : Stack-relative Store', 'CIW : Wide Immediate', 'CL : Load', 'CS : Store', 'CA : Arithmetic', 'CB : Branch/Arithmetic', 'CJ : Jump']}
-}})}
-....
diff --git a/src/images/wavedrom/csr-instr.adoc b/src/images/wavedrom/csr-instr.edn
index 93022be..19d853e 100644
--- a/src/images/wavedrom/csr-instr.adoc
+++ b/src/images/wavedrom/csr-instr.edn
@@ -1,24 +1,24 @@
 //# 10 "Zicsr", Control and Status Register (CSR) Instructions, Version 2.0
-//## 10.1 CSR Instructions
+//## 10.1 CSR Instructions 
 
 [wavedrom, ,svg]
 ....
 {reg: [
-  {bits: 7,  name: 'opcode', attr: ['7', 'SYSTEM', 'SYSTEM', 'SYSTEM', 'SYSTEM', 'SYSTEM', 'SYSTEM'], type: 8},
-  {bits: 5,  name: 'rd',     attr: ['5', 'dest', 'dest', 'dest', 'dest', 'dest', 'dest'], type: 2},
-  {bits: 3,  name: 'funct3', attr: ['3', 'CSRRW', 'CSRRS', 'CSRRC', 'CSRRWI', 'CSRRSI', 'CSRRCI'], type: 8},
-  {bits: 5,  name: 'rs1',    attr: ['5', 'source', 'source', 'source', 'uimm[4:0]', 'uimm[4:0]', 'uimm[4:0]'], type: 4},
-  {bits: 12, name: 'csr',    attr: ['12', 'source/dest', 'source/dest', 'source/dest', 'source/dest', 'source/dest', 'source/dest'], type: 4},
+  {bits: 7,  name: 'opcode', attr: ['7', 'SYSTEM', 'SYSTEM', 'SYSTEM', 'SYSTEM', 'SYSTEM', 'SYSTEM'] },
+  {bits: 5,  name: 'rd',     attr: ['5', 'dest', 'dest', 'dest', 'dest', 'dest', 'dest'] },
+  {bits: 3,  name: 'funct3', attr: ['3', 'CSRRW', 'CSRRS', 'CSRRC', 'CSRRWI', 'CSRRSI', 'CSRRCI'] },
+  {bits: 5,  name: 'rs1',    attr: ['5', 'source', 'source', 'source', 'uimm[4:0]', 'uimm[4:0]', 'uimm[4:0]'] },
+  {bits: 12, name: 'csr',    attr: ['12', 'source/dest', 'source/dest', 'source/dest', 'source/dest', 'source/dest', 'source/dest'], },
 ]}
 ....
 
 //[wavedrom, ,]
 //....
 //{reg: [
-//  {bits: 7,  name: 'opcode', attr: ['7', 'SYSTEM','SYSTEM','SYSTEM'],     type: 8},
-//  {bits: 5,  name: 'rd',     attr: ['3', 'dest','dest', 'dest' ],       type: 2},
-//  {bits: 3,  name: 'funct3',  attr: ['3', 'CSRRWI', 'CSRRSI', 'CSRRCI'], type: 8},
-//  {bits: 5,  name: 'rs1',    attr: ['5', 'uimm[4:0]','uimm[4:0]', 'uimm[4:0]'],   type: 3},
-//  {bits: 12, name: 'csr',    attr: ['12', 'source/dest','source/dest','source/dest'], type: 4},
+//  {bits: 7,  name: 'opcode', attr: ['7', 'SYSTEM','SYSTEM','SYSTEM'] },
+//  {bits: 5,  name: 'rd',     attr: ['3', 'dest','dest', 'dest' ] },
+//  {bits: 3,  name: 'funct3',  attr: ['3', 'CSRRWI', 'CSRRSI', 'CSRRCI'] },
+//  {bits: 5,  name: 'rs1',    attr: ['5', 'uimm[4:0]','uimm[4:0]', 'uimm[4:0]'] },
+//  {bits: 12, name: 'csr',    attr: ['12', 'source/dest','source/dest','source/dest'] },
 //]}
 //....
diff --git a/src/images/wavedrom/ct-conditional.adoc b/src/images/wavedrom/ct-conditional.edn
index b886d7c..e021907 100644
--- a/src/images/wavedrom/ct-conditional.adoc
+++ b/src/images/wavedrom/ct-conditional.edn
@@ -3,11 +3,11 @@
 [wavedrom, ,svg]
 ....
 {reg: [
-  {bits: 7,  name: 'opcode',    attr: ['7', 'BRANCH', 'BRANCH', 'BRANCH'], type: 8},
-  {bits: 5,  name: 'imm[4:1|11]',  attr: ['5', 'offset[4:1|11]', 'offset[4:1|11]', 'offset[4:1|11]'], type: 3},
-  {bits: 3,  name: 'funct3',     attr: ['3', 'BEQ/BNE', 'BLT[U]', 'BGE[U]'], type: 8},
-  {bits: 5,  name: 'rs1', attr: ['5', 'src1', 'src1', 'src1'], type: 4},
-  {bits: 5,  name: 'rs2', attr: ['5', 'src2','src2', 'src2'], type: 4},
-  {bits: 7,  name: 'imm[12|10:5]', attr: ['7', 'offset[12|10:5]', 'offset[12|10:5]', 'offset[12|10:5]'], type: 3},
+  {bits: 7,  name: 'opcode',    attr: ['7', 'BRANCH', 'BRANCH', 'BRANCH'] },
+  {bits: 5,  name: 'imm[4:1|11]',  attr: ['5', 'offset[4:1|11]', 'offset[4:1|11]', 'offset[4:1|11]'] },
+  {bits: 3,  name: 'funct3',     attr: ['3', 'BEQ/BNE', 'BLT[U]', 'BGE[U]'] },
+  {bits: 5,  name: 'rs1', attr: ['5', 'src1', 'src1', 'src1'] },
+  {bits: 5,  name: 'rs2', attr: ['5', 'src2','src2', 'src2'] },
+  {bits: 7,  name: 'imm[12|10:5]', attr: ['7', 'offset[12|10:5]', 'offset[12|10:5]', 'offset[12|10:5]'] },
 ], config:{fontsize: 10}}
 ....
diff --git a/src/images/wavedrom/ct-unconditional-2.adoc b/src/images/wavedrom/ct-unconditional-2.adoc
deleted file mode 100644
index 4dda824..0000000
--- a/src/images/wavedrom/ct-unconditional-2.adoc
+++ /dev/null
@@ -1,12 +0,0 @@
-//ct-unconditional-2
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7,  name: 'opcode',     attr: ['7', 'JALR'], type: 8},
-  {bits: 5,  name: 'rd',         attr: ['5', 'dest'], type: 2},
-  {bits: 3,  name: 'funct3',     attr: ['3', '0'], type: 8},
-  {bits: 5,  name: 'rs1',        attr: ['5', 'base'], type: 4},
-  {bits: 12, name: 'imm[11:0]',  attr: ['12', 'offset[11:0]'], type: 3},
-]}
-....
diff --git a/src/images/wavedrom/ct-unconditional-2.edn b/src/images/wavedrom/ct-unconditional-2.edn
new file mode 100644
index 0000000..95f103e
--- /dev/null
+++ b/src/images/wavedrom/ct-unconditional-2.edn
@@ -0,0 +1,12 @@
+//ct-unconditional-2
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',     attr: ['7', 'JALR'] },
+  {bits: 5,  name: 'rd',         attr: ['5', 'dest'] },
+  {bits: 3,  name: 'funct3',     attr: ['3', '0'] },
+  {bits: 5,  name: 'rs1',        attr: ['5', 'base'] },
+  {bits: 12, name: 'imm[11:0]',  attr: ['12', 'offset[11:0]'] },
+]}
+....
diff --git a/src/images/wavedrom/ct-unconditional.adoc b/src/images/wavedrom/ct-unconditional.adoc
deleted file mode 100644
index 756108f..0000000
--- a/src/images/wavedrom/ct-unconditional.adoc
+++ /dev/null
@@ -1,15 +0,0 @@
-//## 2.5 Control Transfer Instructions
-//### Unconditional Jumps
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7,  name: 'opcode', attr: ['7', 'JAL'], type: 8},
-  {bits: 5,  name: 'rd', attr: ['5', 'dest'], type: 2},
-  {bits: 8,  name: 'imm[19:12]', attr: ['8'], type: 3},
-  {bits: 1,  name: '[11]', attr: ['1'], type: 3},
-  {bits: 10, name: 'imm[10:1]', attr: ['10', 'offset[20:1]'], type: 3},
-  {bits: 1,  name: '[20]', attr: ['1'], type: 3},
-], config:{fontsize: 12}}
-....
-
diff --git a/src/images/wavedrom/ct-unconditional.edn b/src/images/wavedrom/ct-unconditional.edn
new file mode 100644
index 0000000..3dfbd94
--- /dev/null
+++ b/src/images/wavedrom/ct-unconditional.edn
@@ -0,0 +1,15 @@
+//## 2.5 Control Transfer Instructions
+//### Unconditional Jumps
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode', attr: ['7', 'JAL']},
+  {bits: 5,  name: 'rd', attr: ['5', 'dest']},
+  {bits: 8,  name: 'imm[19:12]', attr: ['8']},
+  {bits: 1,  name: '[11]', attr: ['1']},
+  {bits: 10, name: 'imm[10:1]', attr: ['10', 'offset[20:1]']},
+  {bits: 1,  name: '[20]', attr: ['1']},
+], config:{fontsize: 12}}
+....
+
diff --git a/src/images/wavedrom/d-xwwx.adoc b/src/images/wavedrom/d-xwwx.adoc
deleted file mode 100644
index 5965715..0000000
--- a/src/images/wavedrom/d-xwwx.adoc
+++ /dev/null
@@ -1,19 +0,0 @@
-//xw-wx
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP'], type: 8},
-  {bits: 5, name: 'rd',     attr: ['5','dest','dest'], type: 2},
-  {bits: 3, name: 'rm',     attr: ['3','000','000'], type: 8},
-  {bits: 5, name: 'rs1',    attr: ['5','src','src'], type: 4},
-  {bits: 5, name: 'rs2',    attr: ['5','0','0'], type: 4},
-  {bits: 2, name: 'fmt',    attr: ['2','D','D'], type: 8},
-  {bits: 5, name: 'funct5', attr: ['5','FMV.X.D','FMV.D.X'], type: 8},
-]}
-....
-
-
-
-
-
diff --git a/src/images/wavedrom/d-xwwx.edn b/src/images/wavedrom/d-xwwx.edn
new file mode 100644
index 0000000..e5fb261
--- /dev/null
+++ b/src/images/wavedrom/d-xwwx.edn
@@ -0,0 +1,19 @@
+//xw-wx
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP']},
+  {bits: 5, name: 'rd',     attr: ['5','dest','dest']},
+  {bits: 3, name: 'rm',     attr: ['3','000','000']},
+  {bits: 5, name: 'rs1',    attr: ['5','src','src']},
+  {bits: 5, name: 'rs2',    attr: ['5','0','0']},
+  {bits: 2, name: 'fmt',    attr: ['2','D','D']},
+  {bits: 5, name: 'funct5', attr: ['5','FMV.X.D','FMV.D.X']},
+]}
+....
+
+
+
+
+
diff --git a/src/images/wavedrom/division-op.adoc b/src/images/wavedrom/division-op.adoc
deleted file mode 100644
index fabdac1..0000000
--- a/src/images/wavedrom/division-op.adoc
+++ /dev/null
@@ -1,25 +0,0 @@
-//## 8.2 Division Operations
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7,  name: 'opcode', attr: ['7', 'OP', 'OP-32'], type: 8},
-  {bits: 5,  name: 'rd',     attr: ['5', 'dest', 'dest'], type: 2},
-  {bits: 3,  name: 'funct3',  attr: ['3','DIV[U]/REM[U]', 'DIV[U]W/REM[U]W'], type: 8},
-  {bits: 5,  name: 'rs1',    attr: ['5', 'dividend', 'dividend'], type: 4},
-  {bits: 5,  name: 'rs2',    attr: ['5', 'divisor', 'divisor'], type: 4},
-  {bits: 7,  name: 'funct7', attr: ['7', 'MULDIV', 'MULDIV'], type: 8},
-]}
-....
-
-//[wavedrom, ,svg]
-//....
-//{reg: [
-//  {bits: 7,  name: 'opcode', attr: 'OP-32',         type: 8},
-//  {bits: 5,  name: 'rd',     attr: 'dest',          type: 2},
-//  {bits: 3,  name: 'funct3',  attr: ['DIVW', 'DIVUW', 'REMW', 'REMUW'],          type: 8},
-//  {bits: 5,  name: 'rs1',    attr: 'dividend',      type: 4},
-//  {bits: 5,  name: 'rs2',    attr: 'divisor',       type: 4},
-//  {bits: 7,  name: 'funct7', attr: 'MULDIV',        type: 8},
-//]}
-//....
diff --git a/src/images/wavedrom/division-op.edn b/src/images/wavedrom/division-op.edn
new file mode 100644
index 0000000..0dff0e3
--- /dev/null
+++ b/src/images/wavedrom/division-op.edn
@@ -0,0 +1,25 @@
+//## 8.2 Division Operations
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode', attr: ['7', 'OP', 'OP-32']},
+  {bits: 5,  name: 'rd',     attr: ['5', 'dest', 'dest']},
+  {bits: 3,  name: 'funct3',  attr: ['3','DIV[U]/REM[U]', 'DIV[U]W/REM[U]W']},
+  {bits: 5,  name: 'rs1',    attr: ['5', 'dividend', 'dividend']},
+  {bits: 5,  name: 'rs2',    attr: ['5', 'divisor', 'divisor']},
+  {bits: 7,  name: 'funct7', attr: ['7', 'MULDIV', 'MULDIV']},
+]}
+....
+
+//[wavedrom, ,svg]
+//....
+//{reg: [
+//  {bits: 7,  name: 'opcode', attr: 'OP-32'},
+//  {bits: 5,  name: 'rd',     attr: 'dest'},
+//  {bits: 3,  name: 'funct3',  attr: ['DIVW', 'DIVUW', 'REMW', 'REMUW']},
+//  {bits: 5,  name: 'rs1',    attr: 'dividend'},
+//  {bits: 5,  name: 'rs2',    attr: 'divisor'},
+//  {bits: 7,  name: 'funct7', attr: 'MULDIV'},
+//]}
+//....
diff --git a/src/images/wavedrom/double-fl-class.adoc b/src/images/wavedrom/double-fl-class.adoc
deleted file mode 100644
index 143ff5e..0000000
--- a/src/images/wavedrom/double-fl-class.adoc
+++ /dev/null
@@ -1,15 +0,0 @@
-//## 13.7 Double-Precision Floating-Point Classify Instruction
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7, name: 'opcode', attr: ['7','OP-FP'], type: 8},
-  {bits: 5, name: 'rd',     attr: ['5','dest'],   type: 2},
-  {bits: 3, name: 'rm',     attr: ['3','1'], type: 8},
-  {bits: 5, name: 'rs1',    attr: ['5','src'], type: 4},
-  {bits: 5, name: 'rs2',    attr: ['5','0'], type: 8},
-  {bits: 2, name: 'fmt',    attr: ['2','D'], type: 8},
-  {bits: 5, name: 'funct5', attr: ['5','FCLASS'], type: 8},
-]}
-....
-
diff --git a/src/images/wavedrom/double-fl-class.edn b/src/images/wavedrom/double-fl-class.edn
new file mode 100644
index 0000000..2779d1a
--- /dev/null
+++ b/src/images/wavedrom/double-fl-class.edn
@@ -0,0 +1,15 @@
+//## 13.7 Double-Precision Floating-Point Classify Instruction
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7, name: 'opcode', attr: ['7','OP-FP']},
+  {bits: 5, name: 'rd',     attr: ['5','dest']},
+  {bits: 3, name: 'rm',     attr: ['3','1']},
+  {bits: 5, name: 'rs1',    attr: ['5','src']},
+  {bits: 5, name: 'rs2',    attr: ['5','0']},
+  {bits: 2, name: 'fmt',    attr: ['2','D']},
+  {bits: 5, name: 'funct5', attr: ['5','FCLASS']},
+]}
+....
+
diff --git a/src/images/wavedrom/double-fl-compare.adoc b/src/images/wavedrom/double-fl-compare.adoc
deleted file mode 100644
index 8403734..0000000
--- a/src/images/wavedrom/double-fl-compare.adoc
+++ /dev/null
@@ -1,15 +0,0 @@
-//## 13.6 Double-Precision Floating-Point Compare Instructions
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7, name: 'opcode', attr: ['7','OP-FP'], type: 8},
-  {bits: 5, name: 'rd',     attr: ['5','dest'], type: 2},
-  {bits: 3, name: 'rm',  attr: ['3','EQ/LT/LE'], type: 8},
-  {bits: 5, name: 'rs1',    attr: ['5','src1'], type: 4},
-  {bits: 5, name: 'rs2',    attr: ['5','src2'], type: 4},
-  {bits: 2, name: 'fmt',    attr: ['2','D'], type: 8},
-  {bits: 5, name: 'funct5', attr: ['5','FCMP'], type: 8},
-]}
-....
-
diff --git a/src/images/wavedrom/double-fl-compare.edn b/src/images/wavedrom/double-fl-compare.edn
new file mode 100644
index 0000000..550bb00
--- /dev/null
+++ b/src/images/wavedrom/double-fl-compare.edn
@@ -0,0 +1,15 @@
+//## 13.6 Double-Precision Floating-Point Compare Instructions
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7, name: 'opcode', attr: ['7','OP-FP']},
+  {bits: 5, name: 'rd',     attr: ['5','dest']},
+  {bits: 3, name: 'rm',  attr: ['3','EQ/LT/LE']},
+  {bits: 5, name: 'rs1',    attr: ['5','src1']},
+  {bits: 5, name: 'rs2',    attr: ['5','src2']},
+  {bits: 2, name: 'fmt',    attr: ['2','D']},
+  {bits: 5, name: 'funct5', attr: ['5','FCMP']},
+]}
+....
+
diff --git a/src/images/wavedrom/double-fl-compute.adoc b/src/images/wavedrom/double-fl-compute.adoc
deleted file mode 100644
index 4ce3b71..0000000
--- a/src/images/wavedrom/double-fl-compute.adoc
+++ /dev/null
@@ -1,54 +0,0 @@
-//## 13.4 Double-Precision Floating-Point Computational Instructions
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP'], type: 8},
-  {bits: 5, name: 'rd',     attr: ['5','dest','dest','dest','dest'], type: 2},
-  {bits: 3, name: 'rm',     attr: ['3','RM','RM','MIN/MAX','RM'], type: 8},
-  {bits: 5, name: 'rs1',    attr: ['5','src1','src1','src1','src'], type: 4},
-  {bits: 5, name: 'rs2',    attr: ['5','src2','src2','src2','0'], type: 4},
-  {bits: 2, name: 'fmt',    attr: ['2','D','D','D','D'], type: 8},
-  {bits: 5, name: 'funct5', attr: ['5','FADD/FSUB', 'FMUL/FDIV', 'FMIN-MAX', 'FSQRT'], type: 8},
-]}
-....
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7, name: 'opcode', attr: ['7','F[N]MADD/F[N]MSUB'],    type: 8},
-  {bits: 5, name: 'rd',     attr: ['5','dest'],     type: 2},
-  {bits: 3, name: 'rm',     attr: ['3','RM'],       type: 8},
-  {bits: 5, name: 'rs1',    attr: ['5','src'],      type: 4},
-  {bits: 5, name: 'rs2',    attr: ['5','src2'],     type: 4},
-  {bits: 2, name: 'fmt',    attr: ['2','D'],        type: 8},
-  {bits: 5, name: 'rs3',    attr: ['5','src3'],    type: 8},
-]}
-....
-
-//[wavedrom, ,]
-//....
-//{reg: [
-//  {bits: 7, name: 'opcode', attr: 'OP-FP',    type: 8},
-//  {bits: 5, name: 'rd',     attr: 'dest',     type: 2},
-//  {bits: 3, name: 'funct3',  attr: ['MIN', 'MAX'], type: 8},
-//  {bits: 5, name: 'rs1',    attr: 'src1',     type: 4},
-//  {bits: 5, name: 'rs2',    attr: 'src2',     type: 4},
-//  {bits: 2, name: 'fmt',    attr: 'D',        type: 8},
-//  {bits: 5, name: 'funct5', attr: 'FMIN-MAX', type: 8},
-//]}
-//....
-
-//[wavedrom, ,]
-//....
-//{reg: [
-//  {bits: 7, name: 'opcode', attr: ['FMADD', 'FNMADD', 'FMSUB', 'FNMSUB'],    type: 8},
-//  {bits: 5, name: 'rd',     attr: 'dest',     type: 2},
-//  {bits: 3, name: 'funct3',  attr: 'RM', type: 8},
-//  {bits: 5, name: 'rs1',    attr: 'src1',     type: 4},
-//  {bits: 5, name: 'rs2',    attr: 'src2',     type: 4},
-//  {bits: 2, name: 'fmt',    attr: 'D',        type: 8},
-//  {bits: 5, name: 'rs3',    attr: 'src3',     type: 4},
-//]}
-//....
-
diff --git a/src/images/wavedrom/double-fl-compute.edn b/src/images/wavedrom/double-fl-compute.edn
new file mode 100644
index 0000000..8f3922d
--- /dev/null
+++ b/src/images/wavedrom/double-fl-compute.edn
@@ -0,0 +1,54 @@
+//## 13.4 Double-Precision Floating-Point Computational Instructions
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP']},
+  {bits: 5, name: 'rd',     attr: ['5','dest','dest','dest','dest']},
+  {bits: 3, name: 'rm',     attr: ['3','RM','RM','MIN/MAX','RM']},
+  {bits: 5, name: 'rs1',    attr: ['5','src1','src1','src1','src']},
+  {bits: 5, name: 'rs2',    attr: ['5','src2','src2','src2','0']},
+  {bits: 2, name: 'fmt',    attr: ['2','D','D','D','D']},
+  {bits: 5, name: 'funct5', attr: ['5','FADD/FSUB', 'FMUL/FDIV', 'FMIN-MAX', 'FSQRT']},
+]}
+....
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7, name: 'opcode', attr: ['7','F[N]MADD/F[N]MSUB']},
+  {bits: 5, name: 'rd',     attr: ['5','dest']},
+  {bits: 3, name: 'rm',     attr: ['3','RM']},
+  {bits: 5, name: 'rs1',    attr: ['5','src']},
+  {bits: 5, name: 'rs2',    attr: ['5','src2']},
+  {bits: 2, name: 'fmt',    attr: ['2','D']},
+  {bits: 5, name: 'rs3',    attr: ['5','src3']},
+]}
+....
+
+//[wavedrom, ,]
+//....
+//{reg: [
+//  {bits: 7, name: 'opcode', attr: 'OP-FP'},
+//  {bits: 5, name: 'rd',     attr: 'dest'},
+//  {bits: 3, name: 'funct3',  attr: ['MIN', 'MAX']},
+//  {bits: 5, name: 'rs1',    attr: 'src1'},
+//  {bits: 5, name: 'rs2',    attr: 'src2'},
+//  {bits: 2, name: 'fmt',    attr: 'D'},
+//  {bits: 5, name: 'funct5', attr: 'FMIN-MAX'},
+//]}
+//....
+
+//[wavedrom, ,]
+//....
+//{reg: [
+//  {bits: 7, name: 'opcode', attr: ['FMADD', 'FNMADD', 'FMSUB', 'FNMSUB']},
+//  {bits: 5, name: 'rd',     attr: 'dest'},
+//  {bits: 3, name: 'funct3',  attr: 'RM'},
+//  {bits: 5, name: 'rs1',    attr: 'src1'},
+//  {bits: 5, name: 'rs2',    attr: 'src2'},
+//  {bits: 2, name: 'fmt',    attr: 'D'},
+//  {bits: 5, name: 'rs3',    attr: 'src3'},
+//]}
+//....
+
diff --git a/src/images/wavedrom/double-fl-convert-mv.adoc b/src/images/wavedrom/double-fl-convert-mv.adoc
deleted file mode 100644
index fb23b08..0000000
--- a/src/images/wavedrom/double-fl-convert-mv.adoc
+++ /dev/null
@@ -1,16 +0,0 @@
-//## 13.5 Double-Precision Floating-Point Conversion and Move Instructions
-
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP'], type: 8},
-  {bits: 5, name: 'rd',     attr: ['5','dest','dest'], type: 2},
-  {bits: 3, name: 'rm',     attr: ['3','RM','RM'], type: 8},
-  {bits: 5, name: 'rs1',    attr: ['5','src','src'], type: 4},
-  {bits: 5, name: 'rs2',    attr: ['5','W[U]/L[U]','W[U]/L[U]'], type: 4},
-  {bits: 2, name: 'fmt',    attr: ['2','D','D'], type: 8},
-  {bits: 5, name: 'funct5', attr: ['5','FCVT.int.D','FCVT.D.int'], type: 8},
-]}
-....
-
diff --git a/src/images/wavedrom/double-fl-convert-mv.edn b/src/images/wavedrom/double-fl-convert-mv.edn
new file mode 100644
index 0000000..15222d3
--- /dev/null
+++ b/src/images/wavedrom/double-fl-convert-mv.edn
@@ -0,0 +1,16 @@
+//## 13.5 Double-Precision Floating-Point Conversion and Move Instructions
+
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP']},
+  {bits: 5, name: 'rd',     attr: ['5','dest','dest']},
+  {bits: 3, name: 'rm',     attr: ['3','RM','RM']},
+  {bits: 5, name: 'rs1',    attr: ['5','src','src']},
+  {bits: 5, name: 'rs2',    attr: ['5','W[U]/L[U]','W[U]/L[U]']},
+  {bits: 2, name: 'fmt',    attr: ['2','D','D']},
+  {bits: 5, name: 'funct5', attr: ['5','FCVT.int.D','FCVT.D.int']},
+]}
+....
+
diff --git a/src/images/wavedrom/double-ls.adoc b/src/images/wavedrom/double-ls.adoc
deleted file mode 100644
index 0c6f4dd..0000000
--- a/src/images/wavedrom/double-ls.adoc
+++ /dev/null
@@ -1,28 +0,0 @@
-//# "D" Standard Extension for Double-Precision Floating-Point, Version 2.2
-//## 13.3 Double-Precision Load and Store Instructions
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7,  name: 'opcode',    attr: ['7','LOAD-FP'],  type: 8},
-  {bits: 5,  name: 'rd',        attr: ['5','dest'],     type: 2},
-  {bits: 3,  name: 'width',     attr: ['3','D'],    type: 8},
-  {bits: 5,  name: 'rs1',       attr: ['5','base'],     type: 4},
-  {bits: 12, name: 'imm[11:0]', attr: ['12','offset[11:0]'],   type: 3},
-]}
-....
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7,  name: 'opcode',    attr: ['7','STORE-FP'], type: 8},
-  {bits: 5,  name: 'imm[4:0]',  attr: ['5','offset[4:0]'],   type: 3},
-  {bits: 3,  name: 'width',     attr: ['3','D'],    type: 8},
-  {bits: 5,  name: 'rs1',       attr: ['5','base'],     type: 4},
-  {bits: 5,  name: 'rs2',       attr: ['5','src'],      type: 4},
-  {bits: 7, name: 'imm[11:5]', attr: ['7','offset[11:5]'],   type: 3},
-]}
-....
-
-
-
diff --git a/src/images/wavedrom/double-ls.edn b/src/images/wavedrom/double-ls.edn
new file mode 100644
index 0000000..0191a0c
--- /dev/null
+++ b/src/images/wavedrom/double-ls.edn
@@ -0,0 +1,28 @@
+//# "D" Standard Extension for Double-Precision Floating-Point, Version 2.2
+//## 13.3 Double-Precision Load and Store Instructions
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',    attr: ['7','LOAD-FP']},
+  {bits: 5,  name: 'rd',        attr: ['5','dest']},
+  {bits: 3,  name: 'width',     attr: ['3','D']},
+  {bits: 5,  name: 'rs1',       attr: ['5','base']},
+  {bits: 12, name: 'imm[11:0]', attr: ['12','offset[11:0]']},
+]}
+....
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',    attr: ['7','STORE-FP']},
+  {bits: 5,  name: 'imm[4:0]',  attr: ['5','offset[4:0]']},
+  {bits: 3,  name: 'width',     attr: ['3','D']},
+  {bits: 5,  name: 'rs1',       attr: ['5','base']},
+  {bits: 5,  name: 'rs2',       attr: ['5','src']},
+  {bits: 7, name: 'imm[11:5]', attr: ['7','offset[11:5]']},
+]}
+....
+
+
+
diff --git a/src/images/wavedrom/env-call-breakpoint.edn b/src/images/wavedrom/env-call-breakpoint.edn
new file mode 100644
index 0000000..5814faf
--- /dev/null
+++ b/src/images/wavedrom/env-call-breakpoint.edn
@@ -0,0 +1,12 @@
+//## 2.8 Environment Call and Breakpoints
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',    attr: ['7', 'SYSTEM', 'SYSTEM']},
+  {bits: 5,  name: 'rd',    attr: ['5', '0', '0']},
+  {bits: 3,  name: 'funct3', attr: ['3', 'PRIV', 'PRIV']},
+  {bits: 5,  name: 'rs1',   attr: ['5', '0', '0']},
+  {bits: 12, name: 'func12', attr: ['12', 'ECALL', 'EBREAK']},
+]}
+....
diff --git a/src/images/wavedrom/env_call-breakpoint.adoc b/src/images/wavedrom/env_call-breakpoint.adoc
deleted file mode 100644
index 7812687..0000000
--- a/src/images/wavedrom/env_call-breakpoint.adoc
+++ /dev/null
@@ -1,12 +0,0 @@
-//## 2.8 Environment Call and Breakpoints
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7,  name: 'opcode',    attr: ['7', 'SYSTEM', 'SYSTEM'], type: 8},
-  {bits: 5,  name: 'rd',    attr: ['5', '0', '0'], type: 2},
-  {bits: 3,  name: 'funct3', attr: ['3', 'PRIV', 'PRIV'], type: 8},
-  {bits: 5,  name: 'rs1',   attr: ['5', '0', '0'], type: 4},
-  {bits: 12, name: 'func12', attr: ['12', 'ECALL', 'EBREAK'], type: 8},
-]}
-....
diff --git a/src/images/wavedrom/fcvt-sd-ds.adoc b/src/images/wavedrom/fcvt-sd-ds.adoc
deleted file mode 100644
index 5b68a54..0000000
--- a/src/images/wavedrom/fcvt-sd-ds.adoc
+++ /dev/null
@@ -1,16 +0,0 @@
-//FCVT.S.D and FCVT.D.S
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP'], type: 8},
-  {bits: 5, name: 'rd',     attr: ['5','dest','dest'], type: 2},
-  {bits: 3, name: 'rm',     attr: ['3','RM','RM'], type: 8},
-  {bits: 5, name: 'rs1',    attr: ['5','src','src'], type: 4},
-  {bits: 5, name: 'rs2',    attr: ['5','D', 'S'], type: 4},
-  {bits: 2, name: 'fmt',    attr: ['2','S','D'], type: 8},
-  {bits: 5, name: 'funct5', attr: ['5','FCVT.S.D', 'FCVT.D.S'], type: 8},
-]}
-....
-
-
diff --git a/src/images/wavedrom/fcvt-sd-ds.edn b/src/images/wavedrom/fcvt-sd-ds.edn
new file mode 100644
index 0000000..a192ffa
--- /dev/null
+++ b/src/images/wavedrom/fcvt-sd-ds.edn
@@ -0,0 +1,16 @@
+//FCVT.S.D and FCVT.D.S
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP']},
+  {bits: 5, name: 'rd',     attr: ['5','dest','dest']},
+  {bits: 3, name: 'rm',     attr: ['3','RM','RM']},
+  {bits: 5, name: 'rs1',    attr: ['5','src','src']},
+  {bits: 5, name: 'rs2',    attr: ['5','D', 'S']},
+  {bits: 2, name: 'fmt',    attr: ['2','S','D']},
+  {bits: 5, name: 'funct5', attr: ['5','FCVT.S.D', 'FCVT.D.S']},
+]}
+....
+
+
diff --git a/src/images/wavedrom/float-csr.adoc b/src/images/wavedrom/float-csr.adoc
deleted file mode 100644
index 7b2cf24..0000000
--- a/src/images/wavedrom/float-csr.adoc
+++ /dev/null
@@ -1,17 +0,0 @@
-//# "F" Standard Extension for Single-Precision Floating-Point, Version 2.2
-//## 12.2 Floating-Point Control and Status Register
-//### Figure 12.2: Floating-point control and status register.
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 1,  name: 'NX', attr: ['1'], type: 5},
-  {bits: 1,  name: 'UF', attr: ['1'], type: 5},
-  {bits: 1,  name: 'OF', attr: ['1'], type: 5},
-  {bits: 1,  name: 'DZ', attr: ['1'], type: 5},
-  {bits: 1,  name: 'NV', attr: ['1'], type: 5},
-  {bits: 3,  name: 'Rounding Mode', attr:['3'], type: 6},
-  {bits: 24, name: 'Reserved', attr:['24'], type: 7},
-], config: {fontsize: 10}}
-....
-
diff --git a/src/images/wavedrom/float-csr.edn b/src/images/wavedrom/float-csr.edn
new file mode 100644
index 0000000..56be164
--- /dev/null
+++ b/src/images/wavedrom/float-csr.edn
@@ -0,0 +1,17 @@
+//# "F" Standard Extension for Single-Precision Floating-Point, Version 2.2
+//## 12.2 Floating-Point Control and Status Register
+//### Figure 12.2: Floating-point control and status register.
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 1,  name: 'NX', attr: ['1']},
+  {bits: 1,  name: 'UF', attr: ['1']},
+  {bits: 1,  name: 'OF', attr: ['1']},
+  {bits: 1,  name: 'DZ', attr: ['1']},
+  {bits: 1,  name: 'NV', attr: ['1']},
+  {bits: 3,  name: 'Rounding Mode', attr:['3']},
+  {bits: 24, name: 'Reserved', attr:['24']},
+], config: {fontsize: 10}}
+....
+
diff --git a/src/images/wavedrom/flt-pt-to-int-move.adoc b/src/images/wavedrom/flt-pt-to-int-move.adoc
deleted file mode 100644
index fc2a95a..0000000
--- a/src/images/wavedrom/flt-pt-to-int-move.adoc
+++ /dev/null
@@ -1,14 +0,0 @@
-// 16.3 Instructions for moving bit patterns between floating-point and integer registers.
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP'],  type: 8},
-  {bits: 5, name: 'rd',     attr: ['5','dest','dest'],   type: 2},
-  {bits: 3, name: 'rm',  attr: ['3','000','000'], type: 8},
-  {bits: 5, name: 'rs1',    attr: ['5','src','src'],   type: 4},
-  {bits: 5, name: 'rs2',    attr: ['5','0','0'],   type: 4},
-  {bits: 2, name: 'fmt',    attr: ['2','H','H'],      type: 8},
-  {bits: 5, name: 'funct5', attr: ['5','FMV.X.H','FMV.H.X'],  type: 8},
-]}
-....
-\ No newline at end of file
diff --git a/src/images/wavedrom/flt-pt-to-int-move.edn b/src/images/wavedrom/flt-pt-to-int-move.edn
new file mode 100644
index 0000000..861085e
--- /dev/null
+++ b/src/images/wavedrom/flt-pt-to-int-move.edn
@@ -0,0 +1,14 @@
+// 16.3 Instructions for moving bit patterns between floating-point and integer registers.
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP']},
+  {bits: 5, name: 'rd',     attr: ['5','dest','dest']},
+  {bits: 3, name: 'rm',  attr: ['3','000','000']},
+  {bits: 5, name: 'rs1',    attr: ['5','src','src']},
+  {bits: 5, name: 'rs2',    attr: ['5','0','0']},
+  {bits: 2, name: 'fmt',    attr: ['2','H','H']},
+  {bits: 5, name: 'funct5', attr: ['5','FMV.X.H','FMV.H.X']},
+]}
+....
+\ No newline at end of file
diff --git a/src/images/wavedrom/flt-to-flt-sgn-inj-instr.adoc b/src/images/wavedrom/flt-to-flt-sgn-inj-instr.adoc
deleted file mode 100644
index 43250a4..0000000
--- a/src/images/wavedrom/flt-to-flt-sgn-inj-instr.adoc
+++ /dev/null
@@ -1,14 +0,0 @@
-// 16.3 Floating point to floating point sign injection instructions.
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7, name: 'opcode', attr: ['7','OP-FP'],  type: 8},
-  {bits: 5, name: 'rd',     attr: ['5','dest'],   type: 2},
-  {bits: 3, name: 'funct3',  attr: ['3','J[N]/JX'], type: 8},
-  {bits: 5, name: 'rs1',    attr: ['5','src1'],   type: 4},
-  {bits: 5, name: 'rs2',    attr: ['5','src2'],   type: 4},
-  {bits: 2, name: 'fmt',    attr: ['2','H'],      type: 8},
-  {bits: 5, name: 'funct5', attr: ['5','FSGNJ'],  type: 8},
-]}
-....
-\ No newline at end of file
diff --git a/src/images/wavedrom/flt-to-flt-sgn-inj-instr.edn b/src/images/wavedrom/flt-to-flt-sgn-inj-instr.edn
new file mode 100644
index 0000000..830cb2a
--- /dev/null
+++ b/src/images/wavedrom/flt-to-flt-sgn-inj-instr.edn
@@ -0,0 +1,14 @@
+// 16.3 Floating point to floating point sign injection instructions.
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7, name: 'opcode', attr: ['7','OP-FP']},
+  {bits: 5, name: 'rd',     attr: ['5','dest']},
+  {bits: 3, name: 'funct3',  attr: ['3','J[N]/JX']},
+  {bits: 5, name: 'rs1',    attr: ['5','src1']},
+  {bits: 5, name: 'rs2',    attr: ['5','src2']},
+  {bits: 2, name: 'fmt',    attr: ['2','H']},
+  {bits: 5, name: 'funct5', attr: ['5','FSGNJ']},
+]}
+....
+\ No newline at end of file
diff --git a/src/images/wavedrom/fnmaddsub.adoc b/src/images/wavedrom/fnmaddsub.adoc
deleted file mode 100644
index e8bda1b..0000000
--- a/src/images/wavedrom/fnmaddsub.adoc
+++ /dev/null
@@ -1,16 +0,0 @@
-
-//FNMSUP and FNMADD
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7, name: 'opcode', attr: ['FMADD', 'FNMADD', 'FMSUB', 'FNMSUB'],    type: 8},
-  {bits: 5, name: 'rd',     attr: 'dest',     type: 2},
-  {bits: 3, name: 'funct3',  attr: 'RM', type: 8},
-  {bits: 5, name: 'rs1',    attr: 'src1',     type: 4},
-  {bits: 5, name: 'rs2',    attr: 'src2',     type: 4},
-  {bits: 2, name: 'fmt',    attr: 'S',        type: 8},
-  {bits: 5, name: 'rs3',    attr: 'src3',     type: 4},
-]}
-....
-
diff --git a/src/images/wavedrom/fsjgnjnx-d.adoc b/src/images/wavedrom/fsjgnjnx-d.adoc
deleted file mode 100644
index fff7808..0000000
--- a/src/images/wavedrom/fsjgnjnx-d.adoc
+++ /dev/null
@@ -1,15 +0,0 @@
-//FSGNJ.D, FSGNJN.D, and FSGNJX.D
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7, name: 'opcode', attr: ['7','OP-FP'], type: 8},
-  {bits: 5, name: 'rd',     attr: ['5','dest'], type: 2},
-  {bits: 3, name: 'rm',     attr: ['3','J[N]/JX'], type: 8},
-  {bits: 5, name: 'rs1',    attr: ['5','src1'], type: 4},
-  {bits: 5, name: 'rs2',    attr: ['5','src2'], type: 4},
-  {bits: 2, name: 'fmt',    attr: ['2','D'],      type: 8},
-  {bits: 5, name: 'funct5', attr: ['5','FSGNJ'],  type: 8},
-]}
-....
-
diff --git a/src/images/wavedrom/fsjgnjnx-d.edn b/src/images/wavedrom/fsjgnjnx-d.edn
new file mode 100644
index 0000000..6247a94
--- /dev/null
+++ b/src/images/wavedrom/fsjgnjnx-d.edn
@@ -0,0 +1,15 @@
+//FSGNJ.D, FSGNJN.D, and FSGNJX.D
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7, name: 'opcode', attr: ['7','OP-FP']},
+  {bits: 5, name: 'rd',     attr: ['5','dest']},
+  {bits: 3, name: 'rm',     attr: ['3','J[N]/JX']},
+  {bits: 5, name: 'rs1',    attr: ['5','src1']},
+  {bits: 5, name: 'rs2',    attr: ['5','src2']},
+  {bits: 2, name: 'fmt',    attr: ['2','D']},
+  {bits: 5, name: 'funct5', attr: ['5','FSGNJ']},
+]}
+....
+
diff --git a/src/images/wavedrom/half-ls.adoc b/src/images/wavedrom/half-ls.adoc
deleted file mode 100644
index fb26d9b..0000000
--- a/src/images/wavedrom/half-ls.adoc
+++ /dev/null
@@ -1,14 +0,0 @@
-//## 15.1 Half-Precision Load and Store Instructions
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7,  name: 'opcode',    attr: 'LOAD-FP',  type: 8},
-  {bits: 5,  name: 'rd',        attr: 'dest',     type: 2},
-  {bits: 3,  name: 'width',     attr: 'H',        type: 8},
-  {bits: 5,  name: 'rs1',       attr: 'base',     type: 4},
-  {bits: 12, name: 'imm[11:0]', attr: 'offset',   type: 3},
-]}
-
-....
-
diff --git a/src/images/wavedrom/half-ls.edn b/src/images/wavedrom/half-ls.edn
new file mode 100644
index 0000000..1d74b69
--- /dev/null
+++ b/src/images/wavedrom/half-ls.edn
@@ -0,0 +1,14 @@
+//## 15.1 Half-Precision Load and Store Instructions
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',    attr: 'LOAD-FP'},
+  {bits: 5,  name: 'rd',        attr: 'dest'},
+  {bits: 3,  name: 'width',     attr: 'H'},
+  {bits: 5,  name: 'rs1',       attr: 'base'},
+  {bits: 12, name: 'imm[11:0]', attr: 'offset'},
+]}
+
+....
+
diff --git a/src/images/wavedrom/half-pr-flt-pt-class.adoc b/src/images/wavedrom/half-pr-flt-pt-class.adoc
deleted file mode 100644
index 5490f5e..0000000
--- a/src/images/wavedrom/half-pr-flt-pt-class.adoc
+++ /dev/null
@@ -1,14 +0,0 @@
-//## 15.5 Half-Precision Floating-Point Classify Instruction
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7, name: 'opcode', attr: ['7', 'OP-FP'],  type: 8},
-  {bits: 5, name: 'rd',     attr: ['5','dest'],   type: 2},
-  {bits: 3, name: 'rm',     attr: ['3','001'],        type: 8},
-  {bits: 5, name: 'rs1',    attr: ['5', 'src'],    type: 4},
-  {bits: 5, name: 'rs2',    attr: ['5','0'],        type: 8},
-  {bits: 2, name: 'fmt',    attr: ['2','H'],      type: 8},
-  {bits: 5, name: 'funct5', attr: ['5','FCLASS'], type: 8},
-]}
-....
-\ No newline at end of file
diff --git a/src/images/wavedrom/half-pr-flt-pt-class.edn b/src/images/wavedrom/half-pr-flt-pt-class.edn
new file mode 100644
index 0000000..d2af321
--- /dev/null
+++ b/src/images/wavedrom/half-pr-flt-pt-class.edn
@@ -0,0 +1,14 @@
+//## 15.5 Half-Precision Floating-Point Classify Instruction
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7, name: 'opcode', attr: ['7', 'OP-FP']},
+  {bits: 5, name: 'rd',     attr: ['5','dest']},
+  {bits: 3, name: 'rm',     attr: ['3','001']},
+  {bits: 5, name: 'rs1',    attr: ['5', 'src']},
+  {bits: 5, name: 'rs2',    attr: ['5','0']},
+  {bits: 2, name: 'fmt',    attr: ['2','H']},
+  {bits: 5, name: 'funct5', attr: ['5','FCLASS']},
+]}
+....
+\ No newline at end of file
diff --git a/src/images/wavedrom/half-pr-flt-pt-compare.adoc b/src/images/wavedrom/half-pr-flt-pt-compare.adoc
deleted file mode 100644
index 78033c1..0000000
--- a/src/images/wavedrom/half-pr-flt-pt-compare.adoc
+++ /dev/null
@@ -1,14 +0,0 @@
-// 16.4 Half-Precision Floating-Point Compare Instructions.
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7, name: 'opcode', attr: ['7','OP-FP'],  type: 8},
-  {bits: 5, name: 'rd',     attr: ['5','dest'],   type: 2},
-  {bits: 3, name: 'rm',  attr: ['3','EQ/LT/LE'], type: 8},
-  {bits: 5, name: 'rs1',    attr: ['5','src1'],   type: 4},
-  {bits: 5, name: 'rs2',    attr: ['5','src2'],   type: 4},
-  {bits: 2, name: 'fmt',    attr: ['2','H'],      type: 8},
-  {bits: 5, name: 'funct5', attr: ['5','FCMP'],  type: 8},
-]}
-....
-\ No newline at end of file
diff --git a/src/images/wavedrom/half-pr-flt-pt-compare.edn b/src/images/wavedrom/half-pr-flt-pt-compare.edn
new file mode 100644
index 0000000..47e2e9f
--- /dev/null
+++ b/src/images/wavedrom/half-pr-flt-pt-compare.edn
@@ -0,0 +1,14 @@
+// 16.4 Half-Precision Floating-Point Compare Instructions.
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7, name: 'opcode', attr: ['7','OP-FP']},
+  {bits: 5, name: 'rd',     attr: ['5','dest']},
+  {bits: 3, name: 'rm',  attr: ['3','EQ/LT/LE']},
+  {bits: 5, name: 'rs1',    attr: ['5','src1']},
+  {bits: 5, name: 'rs2',    attr: ['5','src2']},
+  {bits: 2, name: 'fmt',    attr: ['2','H']},
+  {bits: 5, name: 'funct5', attr: ['5','FCMP']},
+]}
+....
+\ No newline at end of file
diff --git a/src/images/wavedrom/half-prec-conv-and-mv.adoc b/src/images/wavedrom/half-prec-conv-and-mv.adoc
deleted file mode 100644
index 013f1b9..0000000
--- a/src/images/wavedrom/half-prec-conv-and-mv.adoc
+++ /dev/null
@@ -1,15 +0,0 @@
-//## 16.3 Half-Precision Conversion and Move Instructions
-
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7,  name: 'opcode',    attr: ['7','OP-FP','OP-FP'],  type: 8},
-  {bits: 5,  name: 'rd',        attr: ['5','dest','dest'],     type: 2},
-  {bits: 3,  name: 'rm',        attr: ['3','RM','RM'],        type: 8},
-  {bits: 5,  name: 'rs1',       attr: ['5','src','src'],     type: 4},
-  {bits: 5,  name: 'rs2',       attr: ['5','W[U]/L[U]','W[U]/L[U]'],   type: 3},
-  {bits: 2,  name: 'fmt',       attr: ['2','H', 'H'],   type: 2},
-  {bits: 5,  name: 'funct5',    attr: ['5','FCVT.int.H','FCVT.H.int'],    type: 8},
-]}
-....
-\ No newline at end of file
diff --git a/src/images/wavedrom/half-prec-conv-and-mv.edn b/src/images/wavedrom/half-prec-conv-and-mv.edn
new file mode 100644
index 0000000..7f05de4
--- /dev/null
+++ b/src/images/wavedrom/half-prec-conv-and-mv.edn
@@ -0,0 +1,15 @@
+//## 16.3 Half-Precision Conversion and Move Instructions
+
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',    attr: ['7','OP-FP','OP-FP']},
+  {bits: 5,  name: 'rd',        attr: ['5','dest','dest']},
+  {bits: 3,  name: 'rm',        attr: ['3','RM','RM']},
+  {bits: 5,  name: 'rs1',       attr: ['5','src','src']},
+  {bits: 5,  name: 'rs2',       attr: ['5','W[U]/L[U]','W[U]/L[U]']},
+  {bits: 2,  name: 'fmt',       attr: ['2','H', 'H']},
+  {bits: 5,  name: 'funct5',    attr: ['5','FCVT.int.H','FCVT.H.int']},
+]}
+....
+\ No newline at end of file
diff --git a/src/images/wavedrom/half-prec-flpt-to-flpt-conv.adoc b/src/images/wavedrom/half-prec-flpt-to-flpt-conv.edn
index c42038c..f95854d 100644
--- a/src/images/wavedrom/half-prec-flpt-to-flpt-conv.adoc
+++ b/src/images/wavedrom/half-prec-flpt-to-flpt-conv.edn
@@ -3,12 +3,12 @@
 [wavedrom, ,svg]
 ....
 {reg: [
-  {bits: 7,  name: 'opcode',    attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP','OP-FP','OP-FP'],  type: 8},
-  {bits: 5,  name: 'rd',        attr: ['5','dest','dest','dest','dest','dest','dest'],     type: 2},
-  {bits: 3,  name: 'rm',        attr: ['3','RM','RM','RM','RM','RM','RM'],        type: 8},
-  {bits: 5,  name: 'rs1',       attr: ['5','src','src','src','src','src','SRC'],     type: 4},
-  {bits: 5,  name: 'rs2',       attr: ['5','H','S','H','D','H','Q'],   type: 3},
-  {bits: 2,  name: 'fmt',       attr: ['2','S','H','D','H','Q','H'],   type: 2},
-  {bits: 5,  name: 'funct5',    attr: ['5','FCVT.S.H','FCVT.H.S','FCVT.D.H','FCVT.H.D','FCVT.Q.H','FCVT.H.Q'],    type: 8},
+  {bits: 7,  name: 'opcode',    attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP','OP-FP','OP-FP']},
+  {bits: 5,  name: 'rd',        attr: ['5','dest','dest','dest','dest','dest','dest']},
+  {bits: 3,  name: 'rm',        attr: ['3','RM','RM','RM','RM','RM','RM']},
+  {bits: 5,  name: 'rs1',       attr: ['5','src','src','src','src','src','SRC']},
+  {bits: 5,  name: 'rs2',       attr: ['5','H','S','H','D','H','Q']},
+  {bits: 2,  name: 'fmt',       attr: ['2','S','H','D','H','Q','H']},
+  {bits: 5,  name: 'funct5',    attr: ['5','FCVT.S.H','FCVT.H.S','FCVT.D.H','FCVT.H.D','FCVT.Q.H','FCVT.H.Q']},
 ]}
 ....
 \ No newline at end of file
diff --git a/src/images/wavedrom/half-store.adoc b/src/images/wavedrom/half-store.adoc
deleted file mode 100644
index fb0d18c..0000000
--- a/src/images/wavedrom/half-store.adoc
+++ /dev/null
@@ -1,11 +0,0 @@
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7,  name: 'opcode',    attr: 'STORE-FP', type: 8},
-  {bits: 5,  name: 'imm[4:0]',  attr: 'offset',   type: 3},
-  {bits: 3,  name: 'width',     attr: 'H',        type: 8},
-  {bits: 5,  name: 'rs1',       attr: 'base',     type: 4},
-  {bits: 5,  name: 'rs2',       attr: 'src',      type: 4},
-  {bits: 12, name: 'imm[11:5]', attr: 'offset',   type: 3},
-]}
-....
-\ No newline at end of file
diff --git a/src/images/wavedrom/hint-nopv_rv32i.adoc b/src/images/wavedrom/hint-nopv_rv32i.adoc
deleted file mode 100644
index b26a6d1..0000000
--- a/src/images/wavedrom/hint-nopv_rv32i.adoc
+++ /dev/null
@@ -1,55 +0,0 @@
-//### RV32I
-//These instructions reserved as HINTs in the latest spec: https://github.com/riscv/riscv-isa-manual/releases (2.9)
-//{ADDI, SLTI, SLTIU, XORI, ORI, ANDI} x0, ? ( ${ 6 * 1 << 17} )
-[wavedrom, ,svg]
-....
-{reg: [
-    {name: 'OP-IMM', bits: 7, attr: 0b0010011},
-    {name: 'rd',     bits: 5, attr: 0},
-    {name: 'funct3',  bits: 3, attr: ['ADDI', 'SLTI', 'SLTIU', 'XORI', 'ORI', 'ANDI']},
-    {bits: 17}
-], config: {hspace: width}}
-....
-//{SLLI, SRLI, SRAI} x0, ? ( ${ 3 * 1 << 10} )
-
-[wavedrom, ,svg]
-....
-{reg:[
-    {name: 'OP-IMM', bits: 7, attr: 0b0010011},
-    {name: 'rd',     bits: 5, attr: 0},
-    {name: 'funct3',  bits: 3, attr: ['SLLI', 'SRLI', 'SRAI']},
-    {bits: 10},
-    {name: 'imm?',   bits: 7, attr: [0, 0, 32]}
-], config: {hspace: width}}
-....
-//{LUI, AUIPC} x0, ? ( ${ 2 * (1 << 20) } )
-
-[wavedrom, ,svg]
-....
-{reg:[
-    {name: 'opcode', bits: 7,  attr: ['AUIPC', 'LUI']},
-    {name: 'rd',     bits: 5,  attr: 0},
-    {bits: 20}
-], config: {hspace: width}}
-....
-//{ADD, SUB, SLL, SLT, SLTU, XOR, SRL, SRA, OR, AND} x0, ?, ? ( ${ 10 * 1 << 10} )
-
-[wavedrom, ,svg]
-....
-{reg:[
-    {name: 'OP',     bits: 7, attr: 0b0110011},
-    {name: 'rd',     bits: 5, attr: 0},
-    {name: 'funct3',  bits: 3, attr: 'ADD SUB SLL SLT SLTU XOR SRL SRA OR AND'.split(' ',
-    {bits: 10},
-    {name: 'funct7',  bits: 7, attr: [0, 0, 0, 0, 0, 0, 32, 32, 0, 0]}
-], config: {hspace: width}}
-....
-
-//RV32I_extra = (
-//  3 * 31 +
-//  31 +
-//  7 * 31 +
-//  3 * 31 +
-//  2 * 31
-//)
-
diff --git a/src/images/wavedrom/hint-nopv_rv64i.adoc b/src/images/wavedrom/hint-nopv_rv64i.adoc
deleted file mode 100644
index ee78cf8..0000000
--- a/src/images/wavedrom/hint-nopv_rv64i.adoc
+++ /dev/null
@@ -1,57 +0,0 @@
-//### RV64I
-//These instructions reserved as HINTs in the latest spec: https://github.com/riscv/riscv-isa-manual/releases (4.4)
-//All RV32I NOPs plus:
-//ADDIW x0, ? ( ${ 1 << 17 } )
-[wavedrom, ,svg]
-....
-{reg:[
-    {name: 'OP-IMM-32', bits: 7,  attr: 0b0011011},
-    {name: 'rd',     bits: 5,  attr: 0},
-    {name: 'funct3',  bits: 3,  attr: 'ADDIW'},
-    {bits: 17}
-], config: {hspace: width}}
-....
-//Extra bit for the shift ammont:
-//{SLLI, SRLI, SRAI} x0, ? ( ${ 3 * 1 << 10} )
-
-[wavedrom, ,svg]
-....
-{reg: [
-    {name: 'OP-IMM', bits: 7, attr: 0b0010011},
-    {name: 'rd',     bits: 5, attr: 0},
-    {name: 'funct3',  bits: 3, attr: ['SLLI', 'SRLI', 'SRAI']},
-    {bits: 10},
-    {name: 'imm?',   bits: 7, attr: [1, 33, 33]}
-], config: {hspace: width}}
-....
-//{SLLIW, SRLIW, SRAIW} x0, ?( ${ 3 * 1 << 10} )
-
-[wavedrom, ,svg]
-....
-{reg:[
-    {name: 'OP-IMM-32', bits: 7,  attr: 0b0011011},
-    {name: 'rd',     bits: 5,  attr: 0},
-    {name: 'funct3',  bits: 3,  attr: ['SLLIW', 'SRLIW', 'SRAIW']},
-    {bits: 10},
-    {name: 'imm?',   bits: 7, attr: [0, 32, 32]}
-], config: {hspace: width}}
-....
-//SLL, SLT, SRA ( ??? )
-//{ADDW, SLLW, SRLW, SUBW, SRAW} x0, ?, ? ( ${ 5 * 1 << 10 } )
-
-[wavedrom, ,svg]
-....
-{reg:[
-    {name: 'OP-32', bits: 7,  attr: 0b0111011},
-    {name: 'rd',     bits: 5,  attr: 0},
-    {name: 'funct3',  bits: 3, attr: ['ADDW', 'SLLW', 'SRLW', 'SUBW', 'SRAW']},
-    {bits: 10},
-    {name: 'funct7',  bits: 7, attr: [0, 0, 32, 0, 32]}
-], config: {hspace: width}}
-....
-
-//RV64I_extra = (
-//  4 * 31 +
-//  5 * 31 +
-//  31
-//`
diff --git a/src/images/wavedrom/hinvalgvma.edn b/src/images/wavedrom/hinvalgvma.edn
index ab1a0cd..d3f9dd9 100644
--- a/src/images/wavedrom/hinvalgvma.edn
+++ b/src/images/wavedrom/hinvalgvma.edn
@@ -1,11 +1,11 @@
 [wavedrom, ,svg]
 ....
 {reg: [
-  {bits: 7,  name: 'opcode',    attr: ['7', 'SYSTEM'],  type: 8},
-  {bits: 5,  name: 'rd',        attr: ['5', '0'],     type: 2},
-  {bits: 3,  name: 'funct3',     attr: ['3', 'PRIV'],    type: 8},
-  {bits: 5,  name: 'rs1',       attr: ['5', 'gaddr'],     type: 4},
-  {bits: 5,  name: 'rs2',       attr: ['5', 'vmid'],     type: 4},
-  {bits: 7,  name: 'funct7',     attr: ['7', 'HINVAL.GVMA'],    type: 8},
+  {bits: 7,  name: 'opcode',    attr: ['7', 'SYSTEM']},
+  {bits: 5,  name: 'rd',        attr: ['5', '0']},
+  {bits: 3,  name: 'funct3',     attr: ['3', 'PRIV']},
+  {bits: 5,  name: 'rs1',       attr: ['5', 'gaddr']},
+  {bits: 5,  name: 'rs2',       attr: ['5', 'vmid']},
+  {bits: 7,  name: 'funct7',     attr: ['7', 'HINVAL.GVMA']},
 ]}
 ....
 \ No newline at end of file
diff --git a/src/images/wavedrom/hinvalvvma.edn b/src/images/wavedrom/hinvalvvma.edn
index 0b93b9f..05f5d40 100644
--- a/src/images/wavedrom/hinvalvvma.edn
+++ b/src/images/wavedrom/hinvalvvma.edn
@@ -1,11 +1,11 @@
 [wavedrom, ,svg]
 ....
 {reg: [
-  {bits: 7,  name: 'opcode',    attr: ['7', 'SYSTEM'],  type: 8},
-  {bits: 5,  name: 'rd',        attr: ['5', '0'],     type: 2},
-  {bits: 3,  name: 'funct3',     attr: ['3', 'PRIV'],    type: 8},
-  {bits: 5,  name: 'rs1',       attr: ['5', 'vaddr'],     type: 4},
-  {bits: 5,  name: 'rs2',       attr: ['5', 'asid'],     type: 4},
-  {bits: 7,  name: 'funct7',     attr: ['7', 'HINVAL.VVMA'],    type: 8},
+  {bits: 7,  name: 'opcode',    attr: ['7', 'SYSTEM']},
+  {bits: 5,  name: 'rd',        attr: ['5', '0']},
+  {bits: 3,  name: 'funct3',     attr: ['3', 'PRIV']},
+  {bits: 5,  name: 'rs1',       attr: ['5', 'vaddr']},
+  {bits: 5,  name: 'rs2',       attr: ['5', 'asid']},
+  {bits: 7,  name: 'funct7',     attr: ['7', 'HINVAL.VVMA']},
 ]}
 ....
 \ No newline at end of file
diff --git a/src/images/wavedrom/hypv-mm-fence.edn b/src/images/wavedrom/hypv-mm-fence.edn
index 2840b1a..a653d4e 100644
--- a/src/images/wavedrom/hypv-mm-fence.edn
+++ b/src/images/wavedrom/hypv-mm-fence.edn
@@ -3,11 +3,11 @@
 [wavedrom, ,svg]
 ....
 {reg: [
-  {bits: 7, name: 'opcode',    type: 3, attr: ['7', 'SYSTEM', 'SYSTEM']},
-  {bits: 5, name: 'rd',  type: 5, attr: ['5','0', '0']},
-  {bits: 3, name: 'funct3',    type: 5, attr: ['3','PRIV', 'PRIV']},
-  {bits: 5, name: 'rs1',    type: 4, attr: ['5','vaddr', 'gaddr']},
-  {bits: 5, name: 'rs2',    type: 4, attr: ['5','asid', 'vmid']},
-  {bits: 7, name: 'funct7',        type: 5, attr: ['7','HFENCE.VVMA', 'HFENCE.GVMA']},
+  {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM', 'SYSTEM']},
+  {bits: 5, name: 'rd', attr: ['5','0', '0']},
+  {bits: 3, name: 'funct3', attr: ['3','PRIV', 'PRIV']},
+  {bits: 5, name: 'rs1', attr: ['5','vaddr', 'gaddr']},
+  {bits: 5, name: 'rs2', attr: ['5','asid', 'vmid']},
+  {bits: 7, name: 'funct7', attr: ['7','HFENCE.VVMA', 'HFENCE.GVMA']},
 ], config: {bits: 32}}
 ....
 \ No newline at end of file
diff --git a/src/images/wavedrom/hypv-virt-load-and-store.edn b/src/images/wavedrom/hypv-virt-load-and-store.edn
index d0e1d9e..2ee4486 100644
--- a/src/images/wavedrom/hypv-virt-load-and-store.edn
+++ b/src/images/wavedrom/hypv-virt-load-and-store.edn
@@ -3,11 +3,11 @@
 [wavedrom, ,svg]
 ....
 {reg: [
-  {bits: 7, name: 'opcode',    type: 3, attr: ['7','SYSTEM', 'SYSTEM', 'SYSTEM']},
-  {bits: 5, name: 'rd',  type: 5, attr: ['5','dest', 'dest', '0']},
-  {bits: 3, name: 'funct3',    type: 5, attr: ['3','PRIVM', 'PRIVM', 'PRIVM']},
-  {bits: 5, name: 'rs1',    type: 4, attr: ['5','addr', 'addr', 'addr']},
-  {bits: 5, name: 'rs2',    type: 4, attr: ['5','[U]', 'HLVX', 'src']},
-  {bits: 7, name: 'funct7',        type: 5, attr: ['7','HLV.width', 'HLVX.HU/WU', 'HSV.width']},
+  {bits: 7, name: 'opcode', attr: ['7','SYSTEM', 'SYSTEM', 'SYSTEM']},
+  {bits: 5, name: 'rd', attr: ['5','dest', 'dest', '0']},
+  {bits: 3, name: 'funct3', attr: ['3','PRIVM', 'PRIVM', 'PRIVM']},
+  {bits: 5, name: 'rs1', attr: ['5','addr', 'addr', 'addr']},
+  {bits: 5, name: 'rs2', attr: ['5','[U]', 'HLVX', 'src']},
+  {bits: 7, name: 'funct7', attr: ['7','HLV.width', 'HLVX.HU/WU', 'HSV.width']},
 ], config: {bits: 32}}
 ....
 \ No newline at end of file
diff --git a/src/images/wavedrom/i-immediate.edn b/src/images/wavedrom/i-immediate.edn
new file mode 100644
index 0000000..578b0e3
--- /dev/null
+++ b/src/images/wavedrom/i-immediate.edn
@@ -0,0 +1,14 @@
+//### Figure 2.4
+//Types of immediate produced by RISC-V instructions. The fields are labeled with the instruction bits used to construct their value. Sign extension always uses inst[31].
+//#### I-immediate
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 1,  name: '[20]'},
+  {bits: 4,  name: 'inst[24:21]'},
+  {bits: 6,  name: 'inst[30:25]'},
+  {bits: 21,  name: '— inst[31] —'},
+], config:{fontsize: 12, label:{right: 'I-immediate'}}}
+....
+
diff --git a/src/images/wavedrom/immediate_variants.adoc b/src/images/wavedrom/immediate-variants.edn
index c1f8335..8f9be0c 100644
--- a/src/images/wavedrom/immediate_variants.adoc
+++ b/src/images/wavedrom/immediate-variants.edn
@@ -21,7 +21,7 @@
   {bits: 5,  name: 'rd'},
   {bits: 3,  name: 'funct3'},
   {bits: 5,  name: 'rs1'},
-  {bits: 12, name: 'imm[11:0]', type: 3},
+  {bits: 12, name: 'imm[11:0]'},
 ], config: {label: {right: 'I-Type'}}}
 ....
 
@@ -29,11 +29,11 @@
 ....
 {reg: [
   {bits: 7,  name: 'opcode'},
-  {bits: 5,  name: 'imm[4:0]', type: 3},
+  {bits: 5,  name: 'imm[4:0]'},
   {bits: 3,  name: 'funct3'},
   {bits: 5,  name: 'rs1'},
   {bits: 5,  name: 'rs2'},
-  {bits: 7,  name: 'imm[11:5]', type: 3}
+  {bits: 7,  name: 'imm[11:5]'}
 ], config: {label: {right: 'S-Type'}}}
 ....
 
@@ -41,13 +41,13 @@
 ....
 {reg: [
   {bits: 7,  name: 'opcode'},
-  {bits: 1,  name: '[11]',      type: 3},
-  {bits: 4,  name: 'imm[4:1]',  type: 3},
+  {bits: 1,  name: '[11]'},
+  {bits: 4,  name: 'imm[4:1]'},
   {bits: 3,  name: 'funct3'},
   {bits: 5,  name: 'rs1'},
   {bits: 5,  name: 'rs2'},
-  {bits: 6,  name: 'imm[10:5]', type: 3},
-  {bits: 1,  name: '[12]',      type: 3}
+  {bits: 6,  name: 'imm[10:5]'},
+  {bits: 1,  name: '[12]'}
 ], config: {fontsize: 12, label: {right: 'B-Type'}}}
 ....
 
@@ -56,7 +56,7 @@
 {reg: [
   {bits: 7,  name: 'opcode'},
   {bits: 5,  name: 'rd'},
-  {bits: 20, name: 'imm[31:12]', type: 3}
+  {bits: 20, name: 'imm[31:12]'}
 ], config: {label: {right: 'U-Type'}}}
 ....
 
@@ -65,10 +65,10 @@
 {reg: [
   {bits: 7,  name: 'opcode'},
   {bits: 5,  name: 'rd'},
-  {bits: 8,  name: 'imm[19:12]', type: 3},
-  {bits: 1,  name: '[11]',       type: 3},
-  {bits: 10, name: 'imm[10:1]',  type: 3},
-  {bits: 1,  name: '[20]',       type: 3}
+  {bits: 8,  name: 'imm[19:12]'},
+  {bits: 1,  name: '[11]'},
+  {bits: 10, name: 'imm[10:1]'},
+  {bits: 1,  name: '[20]'}
 ], config: {fontsize: 12, label: {right: 'J-Type'}}}
 ....
 
diff --git a/src/images/wavedrom/immediate.adoc b/src/images/wavedrom/immediate.adoc
deleted file mode 100644
index c6fb00d..0000000
--- a/src/images/wavedrom/immediate.adoc
+++ /dev/null
@@ -1,60 +0,0 @@
-//### Figure 2.4
-//Types of immediate produced by RISC-V instructions. The fields are labeled with the instruction bits used to construct their value. Sign extension always uses inst[31].
-//#### I-immediate
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 1,  name: '[20]'},
-  {bits: 4,  name: 'inst[24:21]'},
-  {bits: 6,  name: 'inst[30:25]'},
-  {bits: 21,  name: '— inst[31] —', type: 7},
-], config:{fontsize: 12, label:{right: 'I-immediate'}}}
-....
-//#### S-immediate
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 1,  name: '[7]'},
-  {bits: 4,  name: 'inst[11:8]'},
-  {bits: 6,  name: 'inst[30:25]'},
-  {bits: 21,  name: '— inst[31] —', type: 7},
-], config:{fontsize: 12, label:{right: 'S-immediate'}}}
-....
-//#### B-immediate
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 1,  name: '0', type: 5},
-  {bits: 4,  name: 'inst[11:8]'},
-  {bits: 6,  name: 'inst[30:25]'},
-  {bits: 1,  name: '[7]'},
-  {bits: 20, name: '— inst[31] —', type: 7},
-], config:{fontsize: 12, label:{right: 'B-immediate'}}}
-....
-//#### U-immediate
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 12, name: '0', type: 5},
-  {bits: 8,  name: 'inst[19:12]'},
-  {bits: 11, name: 'inst[30:20]'},
-  {bits: 1,  name: '[31]', type: 7},
-], config:{fontsize: 12, label:{right: 'U-immediate'}}}
-....
-//#### J-immediate
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 1,  name: '0', type: 5},
-  {bits: 4,  name: 'inst[24:21]'},
-  {bits: 6,  name: 'inst[30:25]'},
-  {bits: 1,  name: '[20]'},
-  {bits: 8,  name: 'inst[19:12]'},
-  {bits: 12, name: '— inst[31] —', type: 7},
-], config:{fontsize: 12, label:{right: 'J-immediate'}}}
-....
diff --git a/src/images/wavedrom/immediate.edn b/src/images/wavedrom/immediate.edn
new file mode 100644
index 0000000..e8a034a
--- /dev/null
+++ b/src/images/wavedrom/immediate.edn
@@ -0,0 +1,17 @@
+//### Figure 2.4
+//Types of immediate produced by RISC-V instructions. The fields are labeled with the instruction bits used to construct their value. Sign extension always uses inst[31].
+//#### I-immediate
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 1,  name: '[20]'},
+  {bits: 4,  name: 'inst[24:21]'},
+  {bits: 6,  name: 'inst[30:25]'},
+  {bits: 21,  name: '— inst[31] —'},
+], config:{fontsize: 12, label:{right: 'I-immediate'}}}
+....
+
+
+
+
diff --git a/src/images/wavedrom/immediate_variants2.adoc b/src/images/wavedrom/immediate_variants2.adoc
deleted file mode 100644
index 498b282..0000000
--- a/src/images/wavedrom/immediate_variants2.adoc
+++ /dev/null
@@ -1,56 +0,0 @@
-## 2.3 Immediate Encoding Variants
-### Figure 2.3
-
-RISC-V base instruction formats showing immediate variants.
-
-${wd({reg: [
-  {bits: 7,  name: 'opcode'},
-  {bits: 5,  name: 'rd'},
-  {bits: 3,  name: 'func3'},
-  {bits: 5,  name: 'rs1'},
-  {bits: 5,  name: 'rs2'},
-  {bits: 7,  name: 'funct7'}
-], config: {label: {right: 'R-Type'}}})}
-
-${wd({reg: [
-  {bits: 7,  name: 'opcode'},
-  {bits: 5,  name: 'rd'},
-  {bits: 3,  name: 'func3'},
-  {bits: 5,  name: 'rs1'},
-  {bits: 12, name: 'imm[11:0]', type: 3},
-], config: {label: {right: 'I-Type'}}})}
-
-${wd({reg: [
-  {bits: 7,  name: 'opcode'},
-  {bits: 5,  name: 'imm[4:0]', type: 3},
-  {bits: 3,  name: 'func3'},
-  {bits: 5,  name: 'rs1'},
-  {bits: 5,  name: 'rs2'},
-  {bits: 7,  name: 'imm[11:5]', type: 3}
-], config: {label: {right: 'S-Type'}}})}
-
-${wd({reg: [
-  {bits: 7,  name: 'opcode'},
-  {bits: 1,  name: '[11]',      type: 3},
-  {bits: 4,  name: 'imm[4:1]',  type: 3},
-  {bits: 3,  name: 'func3'},
-  {bits: 5,  name: 'rs1'},
-  {bits: 5,  name: 'rs2'},
-  {bits: 6,  name: 'imm[10:5]', type: 3},
-  {bits: 1,  name: '[12]',      type: 3}
-], config: {label: {right: 'B-Type'}}})}
-
-${wd({reg: [
-  {bits: 7,  name: 'opcode'},
-  {bits: 5,  name: 'rd'},
-  {bits: 20, name: 'imm[31:12]', type: 3}
-], config: {label: {right: 'U-Type'}}})}
-
-${wd({reg: [
-  {bits: 7,  name: 'opcode'},
-  {bits: 5,  name: 'rd'},
-  {bits: 8,  name: 'imm[19:12]', type: 3},
-  {bits: 1,  name: '[11]',       type: 3},
-  {bits: 10, name: 'imm[10:1]',  type: 3},
-  {bits: 1,  name: '[20]',       type: 3}
-], config: {label: {right: 'J-Type'}}})}
-\ No newline at end of file
diff --git a/src/images/wavedrom/instruction-formats.edn b/src/images/wavedrom/instruction-formats.edn
new file mode 100644
index 0000000..0741210
--- /dev/null
+++ b/src/images/wavedrom/instruction-formats.edn
@@ -0,0 +1,48 @@
+//### Figure 2.2
+
+//RISC-V base instruction formats. Each immediate subfield is labeled with the bit position (imm[x]) in the immediate value being produced, rather than the bit position within the instruction’s immediate field as is usually done.
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode'},
+  {bits: 5,  name: 'rd'},
+  {bits: 3,  name: 'funct3'},
+  {bits: 5,  name: 'rs1'},
+  {bits: 5,  name: 'rs2'},
+  {bits: 7,  name: 'funct7'}
+], config: {label: {right: 'R-Type'}}}
+....
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode'},
+  {bits: 5,  name: 'rd'},
+  {bits: 3,  name: 'funct3'},
+  {bits: 5,  name: 'rs1'},
+  {bits: 12, name: 'imm[11:0]'},
+], config: {label: {right: 'I-Type'}}}
+....
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode'},
+  {bits: 5,  name: 'imm[4:0]'},
+  {bits: 3,  name: 'funct3'},
+  {bits: 5,  name: 'rs1'},
+  {bits: 5,  name: 'rs2'},
+  {bits: 7,  name: 'imm[11:5]'}
+], config: {label: {right: 'S-Type'}}}
+....
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode'},
+  {bits: 5,  name: 'rd'},
+  {bits: 20,  name: 'imm[31:12]'}
+], config: {label: {right: 'U-Type'}}}
+....
+
diff --git a/src/images/wavedrom/instruction_formats.adoc b/src/images/wavedrom/instruction_formats.adoc
deleted file mode 100644
index 442e27d..0000000
--- a/src/images/wavedrom/instruction_formats.adoc
+++ /dev/null
@@ -1,48 +0,0 @@
-//### Figure 2.2
-
-//RISC-V base instruction formats. Each immediate subfield is labeled with the bit position (imm[x]) in the immediate value being produced, rather than the bit position within the instruction’s immediate field as is usually done.
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7,  name: 'opcode', type: 8},
-  {bits: 5,  name: 'rd', type: 2},
-  {bits: 3,  name: 'funct3', type: 8},
-  {bits: 5,  name: 'rs1', type: 4},
-  {bits: 5,  name: 'rs2', type: 4},
-  {bits: 7,  name: 'funct7', type: 8}
-], config: {label: {right: 'R-Type'}}}
-....
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7,  name: 'opcode', type: 8},
-  {bits: 5,  name: 'rd', type: 2},
-  {bits: 3,  name: 'funct3', type: 8},
-  {bits: 5,  name: 'rs1', type: 4},
-  {bits: 12, name: 'imm[11:0]', type: 3},
-], config: {label: {right: 'I-Type'}}}
-....
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7,  name: 'opcode', type: 8},
-  {bits: 5,  name: 'imm[4:0]', type: 3},
-  {bits: 3,  name: 'funct3', type: 8},
-  {bits: 5,  name: 'rs1', type: 4},
-  {bits: 5,  name: 'rs2', type: 4},
-  {bits: 7,  name: 'imm[11:5]', type: 3}
-], config: {label: {right: 'S-Type'}}}
-....
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7,  name: 'opcode', type: 8},
-  {bits: 5,  name: 'rd', type: 2},
-  {bits: 20,  name: 'imm[31:12]', type: 3}
-], config: {label: {right: 'U-Type'}}}
-....
-
diff --git a/src/images/wavedrom/int-comp-lui-aiupc.adoc b/src/images/wavedrom/int-comp-lui-aiupc.edn
index c3dbf95..dfb77d1 100644
--- a/src/images/wavedrom/int-comp-lui-aiupc.adoc
+++ b/src/images/wavedrom/int-comp-lui-aiupc.edn
@@ -5,8 +5,8 @@
 [wavedrom, ,svg]
 ....
 {reg: [
-  {bits: 7,  name: 'opcode',     attr: ['7', 'LUI', 'AUIPC'], type: 8},
-  {bits: 5,  name: 'rd',         attr: ['5', 'dest', 'dest'], type: 2},
-  {bits: 20, name: 'imm[31:12]', attr: ['20', 'U-immediate[31:12]', 'U-immediate[31:12]'], type: 3}
+  {bits: 7,  name: 'opcode',     attr: ['7', 'LUI', 'AUIPC']},
+  {bits: 5,  name: 'rd',         attr: ['5', 'dest', 'dest']},
+  {bits: 20, name: 'imm[31:12]', attr: ['20', 'U-immediate[31:12]', 'U-immediate[31:12]']}
 ]}
 ....
diff --git a/src/images/wavedrom/int-comp-slli-srli-srai.adoc b/src/images/wavedrom/int-comp-slli-srli-srai.edn
index 3fa49a4..3e86d08 100644
--- a/src/images/wavedrom/int-comp-slli-srli-srai.adoc
+++ b/src/images/wavedrom/int-comp-slli-srli-srai.edn
@@ -5,12 +5,12 @@
 [wavedrom, ,svg]
 ....
 {reg: [
-  {bits: 7,  name: 'opcode',    attr: ['7', 'OP-IMM', 'OP-IMM', 'OP-IMM'], type: 8},
-  {bits: 5,  name: 'rd',        attr: ['5', 'dest', 'dest', 'dest'], type: 2},
-  {bits: 3,  name: 'funct3',     attr: ['3', 'SLLI', 'SRLI', 'SRAI'], type: 8},
-  {bits: 5,  name: 'rs1',       attr: ['5', 'src', 'src', 'src'], type: 4},
-  {bits: 5,  name: 'imm[4:0]',  attr: ['5', 'shamt[4:0]', 'shamt[4:0]', 'shamt[4:0]'], type: 3},
-  {bits: 7,  name: 'imm[11:5]', attr: ['7', 0, 0, 32], type: 8}
+  {bits: 7,  name: 'opcode',    attr: ['7', 'OP-IMM', 'OP-IMM', 'OP-IMM']},
+  {bits: 5,  name: 'rd',        attr: ['5', 'dest', 'dest', 'dest']},
+  {bits: 3,  name: 'funct3',     attr: ['3', 'SLLI', 'SRLI', 'SRAI']},
+  {bits: 5,  name: 'rs1',       attr: ['5', 'src', 'src', 'src']},
+  {bits: 5,  name: 'imm[4:0]',  attr: ['5', 'shamt[4:0]', 'shamt[4:0]', 'shamt[4:0]']},
+  {bits: 7,  name: 'imm[11:5]', attr: ['7', 0, 0, 32]}
 ]}
 ....
 
diff --git a/src/images/wavedrom/int_reg-reg.adoc b/src/images/wavedrom/int-reg-reg.edn
index 1ec0c17..3fd19f7 100644
--- a/src/images/wavedrom/int_reg-reg.adoc
+++ b/src/images/wavedrom/int-reg-reg.edn
@@ -3,11 +3,11 @@
 [wavedrom, ,svg]
 ....
 {reg: [
-  {bits: 7,  name: 'opcode',    attr: ['7', 'OP', 'OP', 'OP', 'OP'], type: 8},
-  {bits: 5,  name: 'rd',        attr: ['5', 'dest', 'dest', 'dest','dest'], type: 2},
-  {bits: 3,  name: 'funct3',     attr: ['3', 'ADD/SLT[U]', 'AND/OR/XOR', 'SLL/SRL', 'SUB/SRA'], type: 8},
-  {bits: 5,  name: 'rs1',       attr: ['5', 'src1', 'src1', 'src1', 'src1'], type: 4},
-  {bits: 5,  name: 'rs2',       attr: ['5', 'src2', 'src2', 'src2', 'src2'], type: 4},
-  {bits: 7,  name: 'funct7', attr: ['7', 0, 0, 0, 32], type: 8}
+  {bits: 7,  name: 'opcode',    attr: ['7', 'OP', 'OP', 'OP', 'OP']},
+  {bits: 5,  name: 'rd',        attr: ['5', 'dest', 'dest', 'dest','dest']},
+  {bits: 3,  name: 'funct3',     attr: ['3', 'ADD/SLT[U]', 'AND/OR/XOR', 'SLL/SRL', 'SUB/SRA']},
+  {bits: 5,  name: 'rs1',       attr: ['5', 'src1', 'src1', 'src1', 'src1']},
+  {bits: 5,  name: 'rs2',       attr: ['5', 'src2', 'src2', 'src2', 'src2']},
+  {bits: 7,  name: 'funct7', attr: ['7', 0, 0, 0, 32]}
 ]}
 ....
diff --git a/src/images/wavedrom/integer-computational.edn b/src/images/wavedrom/integer-computational.edn
new file mode 100644
index 0000000..707f06f
--- /dev/null
+++ b/src/images/wavedrom/integer-computational.edn
@@ -0,0 +1,15 @@
+//## 2.4 Integer Computational Instructions
+//### Integer Register-Immediate Instructions
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',    attr: ['7', 'OP-IMM', 'OP-IMM']},
+  {bits: 5,  name: 'rd',        attr: ['5', 'dest', 'dest']},
+  {bits: 3,  name: 'funct3',     attr: ['3', 'ADDI/SLTI[U]', 'ANDI/ORI/XORI']},
+  {bits: 5,  name: 'rs1',       attr: ['5', 'src', 'src']},
+  {bits: 12, name: 'imm[11:0]', attr: ['12', 'I-immediate[11:0]', 'I-immediate[11:0]']}
+]}
+....
+
+//<snio>
diff --git a/src/images/wavedrom/integer_computational.adoc b/src/images/wavedrom/integer_computational.adoc
deleted file mode 100644
index 5172d4e..0000000
--- a/src/images/wavedrom/integer_computational.adoc
+++ /dev/null
@@ -1,15 +0,0 @@
-//## 2.4 Integer Computational Instructions
-//### Integer Register-Immediate Instructions
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7,  name: 'opcode',    attr: ['7', 'OP-IMM', 'OP-IMM'], type: 8},
-  {bits: 5,  name: 'rd',        attr: ['5', 'dest', 'dest'], type: 2},
-  {bits: 3,  name: 'funct3',     attr: ['3', 'ADDI/SLTI[U]', 'ANDI/ORI/XORI'], type: 8},
-  {bits: 5,  name: 'rs1',       attr: ['5', 'src', 'src'], type: 4},
-  {bits: 12, name: 'imm[11:0]', attr: ['12', 'I-immediate[11:0]', 'I-immediate[11:0]'], type: 3}
-]}
-....
-
-//<snio>
diff --git a/src/images/wavedrom/j-immediate.edn b/src/images/wavedrom/j-immediate.edn
new file mode 100644
index 0000000..dbeddd9
--- /dev/null
+++ b/src/images/wavedrom/j-immediate.edn
@@ -0,0 +1,13 @@
+//#### J-immediate
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 1,  name: '0'},
+  {bits: 4,  name: 'inst[24:21]'},
+  {bits: 6,  name: 'inst[30:25]'},
+  {bits: 1,  name: '[20]'},
+  {bits: 8,  name: 'inst[19:12]'},
+  {bits: 12, name: '— inst[31] —'},
+], config:{fontsize: 12, label:{right: 'J-immediate'}}}
+....
+\ No newline at end of file
diff --git a/src/images/wavedrom/load-reserve-st-conditional.adoc b/src/images/wavedrom/load-reserve-st-conditional.adoc
deleted file mode 100644
index 355342c..0000000
--- a/src/images/wavedrom/load-reserve-st-conditional.adoc
+++ /dev/null
@@ -1,19 +0,0 @@
-//# 9 "A" Standard Extension for Atomic Instructions, Version 2.1
-//## 9.2 Load-Reserved/Store-Conditional Instructions
-
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7,  name: 'opcode',    attr: ['7', 'AMO', 'AMO'], type: 8},
-  {bits: 5,  name: 'rd',        attr: ['5', 'dest', 'dest'], type: 2},
-  {bits: 3,  name: 'funct3',    attr: ['3', 'width', 'width'], type: 8},
-  {bits: 5,  name: 'rs1',       attr: ['5', 'addr', 'addr'], type: 4},
-  {bits: 5,  name: 'rs2',       attr: ['5', '0', 'src'], type: 4},
-  {bits: 1,  name: 'rl',        attr: ['1', 'ring', 'ring'], type: 8},
-  {bits: 1,  name: 'aq',        attr: ['1', 'orde', 'orde'], type: 8},
-  {bits: 5,  name: 'funct5',    attr: ['5', 'LR.W/D', 'SC.W/D'], type: 8},
-]}
-....
-
-
diff --git a/src/images/wavedrom/load-reserve-st-conditional.edn b/src/images/wavedrom/load-reserve-st-conditional.edn
new file mode 100644
index 0000000..c1addd3
--- /dev/null
+++ b/src/images/wavedrom/load-reserve-st-conditional.edn
@@ -0,0 +1,19 @@
+//# 9 "A" Standard Extension for Atomic Instructions, Version 2.1
+//## 9.2 Load-Reserved/Store-Conditional Instructions
+
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',    attr: ['7', 'AMO', 'AMO']},
+  {bits: 5,  name: 'rd',        attr: ['5', 'dest', 'dest']},
+  {bits: 3,  name: 'funct3',    attr: ['3', 'width', 'width']},
+  {bits: 5,  name: 'rs1',       attr: ['5', 'addr', 'addr']},
+  {bits: 5,  name: 'rs2',       attr: ['5', '0', 'src']},
+  {bits: 1,  name: 'rl',        attr: ['1', 'ring', 'ring']},
+  {bits: 1,  name: 'aq',        attr: ['1', 'orde', 'orde']},
+  {bits: 5,  name: 'funct5',    attr: ['5', 'LR.W/D', 'SC.W/D']},
+]}
+....
+
+
diff --git a/src/images/wavedrom/load-store.edn b/src/images/wavedrom/load-store.edn
new file mode 100644
index 0000000..ac23d35
--- /dev/null
+++ b/src/images/wavedrom/load-store.edn
@@ -0,0 +1,24 @@
+//## 2.6 Load and Store Instructions
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',    attr: ['7', 'LOAD']},
+  {bits: 5,  name: 'rd', attr: ['5', 'dest']},
+  {bits: 3,  name: 'funct3', attr: ['3', 'width']},
+  {bits: 5,  name: 'rs1', attr: ['5', 'base']},
+  {bits: 12, name: 'imm[11:0]', attr: ['12', 'offset[11:0]']},
+]}
+....
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',   attr: ['7', 'STORE']},
+  {bits: 5,  name: 'imm[4:0]', attr: ['5', 'offset[4:0]']},
+  {bits: 3,  name: 'funct3', attr: ['3', 'width']},
+  {bits: 5,  name: 'rs1', attr: ['5', 'base']},
+  {bits: 5,  name: 'rs2', attr: ['5', 'src']},
+  {bits: 7, name: 'imm[11:5]', attr: ['7', 'offset[11:5]']},
+]}
+....
diff --git a/src/images/wavedrom/load_store.adoc b/src/images/wavedrom/load_store.adoc
deleted file mode 100644
index f9de4d1..0000000
--- a/src/images/wavedrom/load_store.adoc
+++ /dev/null
@@ -1,24 +0,0 @@
-//## 2.6 Load and Store Instructions
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7,  name: 'opcode',    attr: ['7', 'LOAD'], type: 8},
-  {bits: 5,  name: 'rd', attr: ['5', 'dest'], type: 2},
-  {bits: 3,  name: 'funct3', attr: ['3', 'width'], type: 8},
-  {bits: 5,  name: 'rs1', attr: ['5', 'base'], type: 4},
-  {bits: 12, name: 'imm[11:0]', attr: ['12', 'offset[11:0]'], type: 3},
-]}
-....
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7,  name: 'opcode',   attr: ['7', 'STORE'], type: 8},
-  {bits: 5,  name: 'imm[4:0]', attr: ['5', 'offset[4:0]'], type: 3},
-  {bits: 3,  name: 'funct3', attr: ['3', 'width'], type: 8},
-  {bits: 5,  name: 'rs1', attr: ['5', 'base'], type: 4},
-  {bits: 5,  name: 'rs2', attr: ['5', 'src'], type: 4},
-  {bits: 7, name: 'imm[11:5]', attr: ['7', 'offset[11:5]'], type: 3},
-]}
-....
diff --git a/src/images/wavedrom/m-st-ext-for-int-mult.adoc b/src/images/wavedrom/m-st-ext-for-int-mult.adoc
deleted file mode 100644
index 520951c..0000000
--- a/src/images/wavedrom/m-st-ext-for-int-mult.adoc
+++ /dev/null
@@ -1,28 +0,0 @@
-//# 8 "M" Standard Extension for Integer Multiplication and Division, Version 2.0
-//## 8.1 Multiplication Operations
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7,  name: 'opcode', attr: ['7', 'OP', 'OP-32'], type: 8},
-  {bits: 5,  name: 'rd',     attr: ['5', 'dest', 'dest'], type: 2},
-  {bits: 3,  name: 'funct3', attr: ['3', 'MUL/MULH[[S]U]', 'MULW'], type: 8},
-  {bits: 5,  name: 'rs1',    attr: ['5', 'multiplicand', 'multiplicand'], type: 4},
-  {bits: 5,  name: 'rs2',    attr: ['5', 'multiplier', 'multiplier'], type: 4},
-  {bits: 7,  name: 'funct7', attr: ['7', 'MULDIV', 'MULDIV'], type: 8},
-]}
-....
-
-//[wavedrom, ,]
-//....
-//{reg: [
-//  {bits: 7,  name: 'opcode', attr: 'OP-32',         type: 8},
-//  {bits: 5,  name: 'rd',     attr: 'dest',          type: 2},
-//  {bits: 3,  name: 'funct3',  attr: 'MULW',          type: 8},
-//  {bits: 5,  name: 'rs1',    attr: 'multiplicand',  type: 4},
-//  {bits: 5,  name: 'rs2',    attr: 'multiplier',    type: 4},
-//  {bits: 7,  name: 'funct7', attr: 'MULDIV',        type: 8},
-//]}
-//....
-
-
diff --git a/src/images/wavedrom/m-st-ext-for-int-mult.edn b/src/images/wavedrom/m-st-ext-for-int-mult.edn
new file mode 100644
index 0000000..77a3507
--- /dev/null
+++ b/src/images/wavedrom/m-st-ext-for-int-mult.edn
@@ -0,0 +1,28 @@
+//# 8 "M" Standard Extension for Integer Multiplication and Division, Version 2.0
+//## 8.1 Multiplication Operations
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode', attr: ['7', 'OP', 'OP-32']},
+  {bits: 5,  name: 'rd',     attr: ['5', 'dest', 'dest']},
+  {bits: 3,  name: 'funct3', attr: ['3', 'MUL/MULH[[S]U]', 'MULW']},
+  {bits: 5,  name: 'rs1',    attr: ['5', 'multiplicand', 'multiplicand']},
+  {bits: 5,  name: 'rs2',    attr: ['5', 'multiplier', 'multiplier']},
+  {bits: 7,  name: 'funct7', attr: ['7', 'MULDIV', 'MULDIV']},
+]}
+....
+
+//[wavedrom, ,]
+//....
+//{reg: [
+//  {bits: 7,  name: 'opcode', attr: 'OP-32'},
+//  {bits: 5,  name: 'rd',     attr: 'dest'},
+//  {bits: 3,  name: 'funct3',  attr: 'MULW'},
+//  {bits: 5,  name: 'rs1',    attr: 'multiplicand'},
+//  {bits: 5,  name: 'rs2',    attr: 'multiplier'},
+//  {bits: 7,  name: 'funct7', attr: 'MULDIV'},
+//]}
+//....
+
+
diff --git a/src/images/wavedrom/mem_order.adoc b/src/images/wavedrom/mem-order.edn
index 75b5ab0..c7e0ba4 100644
--- a/src/images/wavedrom/mem_order.adoc
+++ b/src/images/wavedrom/mem-order.edn
@@ -3,10 +3,10 @@
 [wavedrom,mem-order ,]
 ....
 {reg: [
-  {bits: 7,  name: 'opcode',    attr: ['7', 'MISC-MEM'], type: 8},
-  {bits: 5,  name: 'rd', attr: ['5', '0'], type: 2},
-  {bits: 3,  name: 'funct3', attr: ['3', 'FENCE'], type: 8},
-  {bits: 5,  name: 'rs1', attr: ['5', '0'], type: 4},
+  {bits: 7,  name: 'opcode',    attr: ['7', 'MISC-MEM']},
+  {bits: 5,  name: 'rd', attr: ['5', '0']},
+  {bits: 3,  name: 'funct3', attr: ['3', 'FENCE']},
+  {bits: 5,  name: 'rs1', attr: ['5', '0']},
   {bits: 1,  name: 'SW', attr: 1},
   {bits: 1,  name: 'SR', attr: 1},
   {bits: 1,  name: 'SO', attr: 1},
@@ -15,6 +15,6 @@
   {bits: 1,  name: 'PR', attr: 1},
   {bits: 1,  name: 'PO', attr: 1},
   {bits: 1,  name: 'PI', attr: 1},
-  {bits: 4,  name: 'fm', attr: ['4', 'FM'], type: 8},
+  {bits: 4,  name: 'fm', attr: ['4', 'FM']},
 ]}
 ....
diff --git a/src/images/wavedrom/menvcfgreg.edn b/src/images/wavedrom/menvcfgreg.edn
new file mode 100644
index 0000000..5ed6fb6
--- /dev/null
+++ b/src/images/wavedrom/menvcfgreg.edn
@@ -0,0 +1,21 @@
+//.Machine environment configuration (`menvcfg`) register.
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits:  1, name: 'FIOM'},
+  {bits:  1, name: 'WPRI'},
+  {bits:  1, name: 'LPE'},
+  {bits:  1, name: 'SSE'},
+  {bits:  2, name: 'CBIE'},
+  {bits:  1, name: 'CBCFE'},
+  {bits:  1, name: 'CBZE'},
+  {bits: 24, name: 'WPRI'},
+  {bits:  2, name: 'PMM'},
+  {bits: 25, name: 'WPRI'},
+  {bits:  1, name: 'DTE'},
+  {bits:  1, name: 'CDE'},
+  {bits:  1, name: 'ADUE'},
+  {bits:  1, name: 'PBMTE'},
+  {bits:  1, name: 'STCE'},
+], config:{lanes: 4, hspace:1024}}
+....
diff --git a/src/images/wavedrom/mm-env-call.adoc b/src/images/wavedrom/mm-env-call.adoc
deleted file mode 100644
index 9838230..0000000
--- a/src/images/wavedrom/mm-env-call.adoc
+++ /dev/null
@@ -1,13 +0,0 @@
-//
-
-[wavedrom, ,svg]
-
-....
-{reg: [
-  {bits: 7, name: 'opcode', type: 8, attr: ['7','SYSTEM','SYSTEM'],},
-  {bits: 5, name: 'rd', type: 2, attr: ['5','0','0'],},
-  {bits: 3, name: 'funct3', type: 8, attr: ['3','PRIV','PRIV'],},
-  {bits: 5, name: 'rs1', type: 4, attr: ['5','0','0'],},
-  {bits: 12, name: 'funct12', type: 8, attr: ['12','ECALL','EBREAK',]},
-], config: {bits: 32}}
-....
-\ No newline at end of file
diff --git a/src/images/wavedrom/mm-env-call.edn b/src/images/wavedrom/mm-env-call.edn
new file mode 100644
index 0000000..703c0be
--- /dev/null
+++ b/src/images/wavedrom/mm-env-call.edn
@@ -0,0 +1,13 @@
+//
+
+[wavedrom, ,svg]
+
+....
+{reg: [
+  {bits: 7, name: 'opcode', attr: ['7','SYSTEM','SYSTEM'],},
+  {bits: 5, name: 'rd', attr: ['5','0','0'],},
+  {bits: 3, name: 'funct3', attr: ['3','PRIV','PRIV'],},
+  {bits: 5, name: 'rs1', attr: ['5','0','0'],},
+  {bits: 12, name: 'funct12', attr: ['12','ECALL','EBREAK',]},
+], config: {bits: 32}}
+....
+\ No newline at end of file
diff --git a/src/images/wavedrom/mop-r.adoc b/src/images/wavedrom/mop-r.edn
index 713b37c..55347e0 100644
--- a/src/images/wavedrom/mop-r.adoc
+++ b/src/images/wavedrom/mop-r.edn
@@ -1,10 +1,10 @@
 [wavedrom, ,svg]
 ....
 {reg:[
-    { bits:  7, name: 0x73, attr: ['SYSTEM'], type: 8 },
-    { bits:  5, name: 'rd', type: 2 },
+    { bits:  7, name: 0x73, attr: ['SYSTEM']},
+    { bits:  5, name: 'rd'},
     { bits:  3, name: 0x4 },
-    { bits:  5, name: 'rs1', type: 4 },
+    { bits:  5, name: 'rs1'},
     { bits:  2, name: 'n[1:0]' },
     { bits:  4, name: 0x7 },
     { bits:  2, name: 'n[3:2]' },
diff --git a/src/images/wavedrom/mop-rr.adoc b/src/images/wavedrom/mop-rr.edn
index b70f854..879e372 100644
--- a/src/images/wavedrom/mop-rr.adoc
+++ b/src/images/wavedrom/mop-rr.edn
@@ -1,11 +1,11 @@
 [wavedrom, ,svg]
 ....
 {reg:[
-    { bits:  7, name: 0x73, attr: ['SYSTEM'], type: 8 },
-    { bits:  5, name: 'rd', type: 2 },
+    { bits:  7, name: 0x73, attr: ['SYSTEM']},
+    { bits:  5, name: 'rd'},
     { bits:  3, name: 0x4 },
-    { bits:  5, name: 'rs1', type: 4 },
-    { bits:  5, name: 'rs2', type: 4 },
+    { bits:  5, name: 'rs1'},
+    { bits:  5, name: 'rs2'},
     { bits:  1, name: 0x1 },
     { bits:  2, name: 'n[1:0]' },
     { bits:  2, name: 0x0 },
diff --git a/src/images/wavedrom/mseccfg.edn b/src/images/wavedrom/mseccfg.edn
new file mode 100644
index 0000000..82242ca
--- /dev/null
+++ b/src/images/wavedrom/mseccfg.edn
@@ -0,0 +1,14 @@
+//.Machine security configuration (`mseccfg`) register.
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits:  1, name: 'MML'},
+  {bits:  1, name: 'MMWP'},
+  {bits:  1, name: 'RLB'},
+  {bits:  5, name: 'WPRI'},
+  {bits:  1, name: 'USEED'},
+  {bits:  1, name: 'SSEED'},
+  {bits:  1, name: 'MLPE'},
+  {bits: 53, name: 'WPRI'},
+], config:{lanes: 4, hspace:1024}}
+....
diff --git a/src/images/wavedrom/mstatushreg.edn b/src/images/wavedrom/mstatushreg.edn
new file mode 100644
index 0000000..702ea11
--- /dev/null
+++ b/src/images/wavedrom/mstatushreg.edn
@@ -0,0 +1,15 @@
+//.Additional machine-mode status (`mstatush`) register  for RV32.
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits:  4, name: 'WPRI'},
+  {bits:  1, name: 'SBE'},
+  {bits:  1, name: 'MBE'},
+  {bits:  1, name: 'GVA'},
+  {bits:  1, name: 'MPV'},
+  {bits:  1, name: 'WPRI'},
+  {bits:  1, name: 'MPELP'},
+  {bits:  1, name: 'MDT'},
+  {bits: 21, name: 'WPRI'},
+], config:{lanes: 2, hspace:1024}}
+....
diff --git a/src/images/wavedrom/mstatusreg-rv321.edn b/src/images/wavedrom/mstatusreg-rv321.edn
new file mode 100644
index 0000000..cc77fc2
--- /dev/null
+++ b/src/images/wavedrom/mstatusreg-rv321.edn
@@ -0,0 +1,29 @@
+//.Machine-mode status (`mstatus`) register for RV32
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits:  1, name: 'WPRI'},
+  {bits:  1, name: 'SIE'},
+  {bits:  1, name: 'WPRI'},
+  {bits:  1, name: 'MIE'},
+  {bits:  1, name: 'WPRI'},
+  {bits:  1, name: 'SPIE'},
+  {bits:  1, name: 'UBE'},
+  {bits:  1, name: 'MPIE'},
+  {bits:  1, name: 'SPP'},
+  {bits:  2, name: 'VS[1:0]'},
+  {bits:  2, name: 'MPP[1:0]'},
+  {bits:  2, name: 'FS[1:0]'},
+  {bits:  2, name: 'XS[1:0]'},
+  {bits:  1, name: 'MPRV'},
+  {bits:  1, name: 'SUM'},
+  {bits:  1, name: 'MXR'},
+  {bits:  1, name: 'TVM'},
+  {bits:  1, name: 'TW'},
+  {bits:  1, name: 'TSR'},
+  {bits:  1, name: 'SPELP'},
+  {bits:  1, name: 'SDT'},
+  {bits:  6, name: 'WPRI'},
+  {bits:  1, name: 'SD'},
+], config:{lanes: 2, hspace:1024}}
+....
diff --git a/src/images/wavedrom/mstatusreg.edn b/src/images/wavedrom/mstatusreg.edn
new file mode 100644
index 0000000..db24626
--- /dev/null
+++ b/src/images/wavedrom/mstatusreg.edn
@@ -0,0 +1,39 @@
+//.Machine-mode status (`mstatus`) register for RV64
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits:  1, name: 'WPRI'},
+  {bits:  1, name: 'SIE'},
+  {bits:  1, name: 'WPRI'},
+  {bits:  1, name: 'MIE'},
+  {bits:  1, name: 'WPRI'},
+  {bits:  1, name: 'SPIE'},
+  {bits:  1, name: 'UBE'},
+  {bits:  1, name: 'MPIE'},
+  {bits:  1, name: 'SPP'},
+  {bits:  2, name: 'VS[1:0]'},
+  {bits:  2, name: 'MPP[1:0]'},
+  {bits:  2, name: 'FS[1:0]'},
+  {bits:  2, name: 'XS[1:0]'},
+  {bits:  1, name: 'MPRV'},
+  {bits:  1, name: 'SUM'},
+  {bits:  1, name: 'MXR'},
+  {bits:  1, name: 'TVM'},
+  {bits:  1, name: 'TW'},
+  {bits:  1, name: 'TSR'},
+  {bits:  1, name: 'SPELP'},
+  {bits:  1, name: 'SDT'},
+  {bits:  7, name: 'WPRI'},
+  {bits:  2, name: 'UXL[1:0]'},
+  {bits:  2, name: 'SXL[1:0]'},
+  {bits:  1, name: 'SBE'},
+  {bits:  1, name: 'MBE'},
+  {bits:  1, name: 'GVA'},
+  {bits:  1, name: 'MPV'},
+  {bits:  1, name: 'WPRI'},
+  {bits:  1, name: 'MPELP'},
+  {bits:  1, name: 'MDT'},
+  {bits: 20, name: 'WPRI'},
+  {bits:  1, name: 'SD'},
+], config:{lanes: 4, hspace:1024}}
+....
diff --git a/src/images/wavedrom/nop-v.adoc b/src/images/wavedrom/nop-v.adoc
deleted file mode 100644
index 0c990e4..0000000
--- a/src/images/wavedrom/nop-v.adoc
+++ /dev/null
@@ -1,29 +0,0 @@
-//# NOP-V
-
-The RISC-V [User-Level ISA Specification](https://riscv.org/specifications/) defines NOP instruction as follows:
-
-* The NOP instruction does not change any user-visible state, except for advancing the pc.
-* NOP is encoded as \`ADDI x0, x0, 0\`.
-
-[wavedrom, , ]
-----
-{reg:[
-    {name: 'opcode', bits: 7,  attr: 0b0010011},
-    {name: 'rd',     bits: 5,  attr: 0},
-    {name: 'funct3',  bits: 3,  attr: 0},
-    {name: 'rs1',    bits: 5,  attr: 0},
-    {name: 'imm',    bits: 12, attr: 0}
-], config: {hspace: width}}
-----
-
-
-NOTE: NOPs can be used to align code segments to microarchitecturally significant address boundaries, or to leave space for inline code modifications. Although **there are many possible ways** to encode a NOP, we define a canonical NOP encoding to allow microarchitectural optimizations as well as for more readable disassembly output.
-
-How many other possible ways to encode NOP?
-----
-rd = 0
-----
-
-Any Integer Computational instruction writing into \`x0\` is NOP.
-
-`
diff --git a/src/images/wavedrom/nop.adoc b/src/images/wavedrom/nop.adoc
deleted file mode 100644
index 34ad70e..0000000
--- a/src/images/wavedrom/nop.adoc
+++ /dev/null
@@ -1,11 +0,0 @@
-//### NOP Instruction
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7,  name: 'opcode',    attr: ['7', 'OP-IMM'], type: 8},
-  {bits: 5,  name: 'rd',        attr: ['5', '0'], type: 2},
-  {bits: 3,  name: 'funct3',     attr: ['3', 'ADDI'], type: 8},
-  {bits: 5,  name: 'rs1',       attr: ['5', '0'], type: 4},
-  {bits: 12, name: 'imm[11:0]', attr: ['12', '0'], type: 3}
-]}
-....
diff --git a/src/images/wavedrom/nop.edn b/src/images/wavedrom/nop.edn
new file mode 100644
index 0000000..b566909
--- /dev/null
+++ b/src/images/wavedrom/nop.edn
@@ -0,0 +1,11 @@
+//### NOP Instruction
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',    attr: ['7', 'OP-IMM']},
+  {bits: 5,  name: 'rd',        attr: ['5', '0']},
+  {bits: 3,  name: 'funct3',     attr: ['3', 'ADDI']},
+  {bits: 5,  name: 'rs1',       attr: ['5', '0']},
+  {bits: 12, name: 'imm[11:0]', attr: ['12', '0']}
+]}
+....
diff --git a/src/images/wavedrom/quad-cnvrt-intch-xqqx.adoc b/src/images/wavedrom/quad-cnvrt-intch-xqqx.adoc
deleted file mode 100644
index ba4e224..0000000
--- a/src/images/wavedrom/quad-cnvrt-intch-xqqx.adoc
+++ /dev/null
@@ -1,15 +0,0 @@
-//quad-cnvrt-intch-xqqx
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7, name: 'opcode', attr: ['7','OP-FP'], type: 8},
-  {bits: 5, name: 'rd',     attr: ['5','dest'], type: 2},
-  {bits: 3, name: 'rm',  attr: ['3', 'J[N]/JX'], type: 8},
-  {bits: 5, name: 'rs1',    attr: ['5','src1'], type: 4},
-  {bits: 5, name: 'rs2',    attr: ['5','src2'], type: 4},
-  {bits: 2, name: 'fmt',    attr: ['2','Q'], type: 8},
-  {bits: 5, name: 'funct5', attr: ['5','FSGNJ'],  type: 8},
-]}
-....
-
diff --git a/src/images/wavedrom/quad-cnvrt-intch-xqqx.edn b/src/images/wavedrom/quad-cnvrt-intch-xqqx.edn
new file mode 100644
index 0000000..a388033
--- /dev/null
+++ b/src/images/wavedrom/quad-cnvrt-intch-xqqx.edn
@@ -0,0 +1,15 @@
+//quad-cnvrt-intch-xqqx
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7, name: 'opcode', attr: ['7','OP-FP']},
+  {bits: 5, name: 'rd',     attr: ['5','dest']},
+  {bits: 3, name: 'rm',  attr: ['3', 'J[N]/JX']},
+  {bits: 5, name: 'rs1',    attr: ['5','src1']},
+  {bits: 5, name: 'rs2',    attr: ['5','src2']},
+  {bits: 2, name: 'fmt',    attr: ['2','Q']},
+  {bits: 5, name: 'funct5', attr: ['5','FSGNJ']},
+]}
+....
+
diff --git a/src/images/wavedrom/quad-cnvrt-mv.adoc b/src/images/wavedrom/quad-cnvrt-mv.adoc
deleted file mode 100644
index 3fc9f86..0000000
--- a/src/images/wavedrom/quad-cnvrt-mv.adoc
+++ /dev/null
@@ -1,28 +0,0 @@
-//## 14.3 Quad-Precision Convert and Move Instructions
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP'], type: 8},
-  {bits: 5, name: 'rd',     attr: ['5','dest','dest'], type: 2},
-  {bits: 3, name: 'rm',  attr: ['3','RM','RM'], type: 8},
-  {bits: 5, name: 'rs1',    attr: ['5','src','src'], type: 4},
-  {bits: 5, name: 'rs2',    attr: ['5','W[U]/L[U]', 'W[U]/L[U]'], type: 4},
-  {bits: 2, name: 'fmt',    attr: ['2','Q','Q'], type: 8},
-  {bits: 5, name: 'funct5', attr: ['5','FCVT.int.Q','FCVT.Q.int'], type: 8},
-]}
-....
-
-//[wavedrom, ,]
-//....
-//{reg: [
-//  {bits: 7, name: 'opcode', attr: 'OP-FP',        type: 8},
-//  {bits: 5, name: 'rd',     attr: 'dest',         type: 2},
-//  {bits: 3, name: 'rm',  attr: 'RM',           type: 8},
-//  {bits: 5, name: 'rs1',    attr: 'src',          type: 4},
-//  {bits: 5, name: 'rs2',    attr: ['W', 'WU', 'L', 'LU'], type: 4},
-//  {bits: 2, name: 'fmt',    attr: 'Q',            type: 8},
-//  {bits: 5, name: 'funct5', attr: 'FCVT.Q.int', type: 8},
-//]}
-//....
-
diff --git a/src/images/wavedrom/quad-cnvrt-mv.edn b/src/images/wavedrom/quad-cnvrt-mv.edn
new file mode 100644
index 0000000..840118d
--- /dev/null
+++ b/src/images/wavedrom/quad-cnvrt-mv.edn
@@ -0,0 +1,28 @@
+//## 14.3 Quad-Precision Convert and Move Instructions
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP']},
+  {bits: 5, name: 'rd',     attr: ['5','dest','dest']},
+  {bits: 3, name: 'rm',  attr: ['3','RM','RM']},
+  {bits: 5, name: 'rs1',    attr: ['5','src','src']},
+  {bits: 5, name: 'rs2',    attr: ['5','W[U]/L[U]', 'W[U]/L[U]']},
+  {bits: 2, name: 'fmt',    attr: ['2','Q','Q']},
+  {bits: 5, name: 'funct5', attr: ['5','FCVT.int.Q','FCVT.Q.int']},
+]}
+....
+
+//[wavedrom, ,]
+//....
+//{reg: [
+//  {bits: 7, name: 'opcode', attr: 'OP-FP'},
+//  {bits: 5, name: 'rd',     attr: 'dest'},
+//  {bits: 3, name: 'rm',  attr: 'RM'},
+//  {bits: 5, name: 'rs1',    attr: 'src'},
+//  {bits: 5, name: 'rs2',    attr: ['W', 'WU', 'L', 'LU']},
+//  {bits: 2, name: 'fmt',    attr: 'Q'},
+//  {bits: 5, name: 'funct5', attr: 'FCVT.Q.int'},
+//]}
+//....
+
diff --git a/src/images/wavedrom/quad-cnvt-interchange.adoc b/src/images/wavedrom/quad-cnvt-interchange.adoc
deleted file mode 100644
index 1178397..0000000
--- a/src/images/wavedrom/quad-cnvt-interchange.adoc
+++ /dev/null
@@ -1,16 +0,0 @@
-//14 conv-mv
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7, name: 'opcode', attr: ['7', 'OP-FP', 'OP-FP','OP-FP','OP-FP'], type: 8},
-  {bits: 5, name: 'rd',     attr: ['5','dest','dest','dest','dest'], type: 2},
-  {bits: 3, name: 'rm',     attr: ['3','RM','RM','RM','RM'], type: 8},
-  {bits: 5, name: 'rs1',    attr: ['5','src','src','src','src'], type: 4},
-  {bits: 5, name: 'rs2',    attr: ['5','Q', 'S', 'Q', 'D'], type: 4},
-  {bits: 2, name: 'fmt',    attr: ['2','S','Q', 'D', 'Q'],      type: 8},
-  {bits: 5, name: 'funct5', attr: ['5','FCVT.S.Q', 'FCVT.Q.S', 'FCVT.D.Q', 'FCVT.Q.D'], type: 8},
-]}
-....
-
-
diff --git a/src/images/wavedrom/quad-cnvt-interchange.edn b/src/images/wavedrom/quad-cnvt-interchange.edn
new file mode 100644
index 0000000..54adc1f
--- /dev/null
+++ b/src/images/wavedrom/quad-cnvt-interchange.edn
@@ -0,0 +1,16 @@
+//14 conv-mv
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7, name: 'opcode', attr: ['7', 'OP-FP', 'OP-FP','OP-FP','OP-FP']},
+  {bits: 5, name: 'rd',     attr: ['5','dest','dest','dest','dest']},
+  {bits: 3, name: 'rm',     attr: ['3','RM','RM','RM','RM']},
+  {bits: 5, name: 'rs1',    attr: ['5','src','src','src','src']},
+  {bits: 5, name: 'rs2',    attr: ['5','Q', 'S', 'Q', 'D']},
+  {bits: 2, name: 'fmt',    attr: ['2','S','Q', 'D', 'Q']},
+  {bits: 5, name: 'funct5', attr: ['5','FCVT.S.Q', 'FCVT.Q.S', 'FCVT.D.Q', 'FCVT.Q.D']},
+]}
+....
+
+
diff --git a/src/images/wavedrom/quad-compute.adoc b/src/images/wavedrom/quad-compute.adoc
deleted file mode 100644
index 6aa3953..0000000
--- a/src/images/wavedrom/quad-compute.adoc
+++ /dev/null
@@ -1,54 +0,0 @@
-//## 14.2 Quad-Precision Computational Instructions
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP'], type: 8},
-  {bits: 5, name: 'rd',     attr: ['5','dest','dest','dest','dest'], type: 2},
-  {bits: 3, name: 'rm',     attr: ['3','RM','RM','MIN/MAX','RM'], type: 8},
-  {bits: 5, name: 'rs1',    attr: ['5','src1','src1','src1','src'], type: 4},
-  {bits: 5, name: 'rs2',    attr: ['5','src2','src2','src2','0'], type: 4},
-  {bits: 2, name: 'fmt',    attr: ['2','Q','Q','Q','Q'], type: 8},
-  {bits: 5, name: 'funct5', attr: ['5','FADD/FSUB', 'FMUL/FDIV', 'FMIN-MAX', 'FSQRT'], type: 8},
-]}
-....
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7, name: 'opcode', attr: ['7','F[N]MADD/F[N]MSUB'], type: 8},
-  {bits: 5, name: 'rd',     attr: ['5','dest'], type: 2},
-  {bits: 3, name: 'rm',     attr: ['3','RM'], type: 8},
-  {bits: 5, name: 'rs1',    attr: ['5','src1'], type: 4},
-  {bits: 5, name: 'rs2',    attr: ['5','src2'], type: 8},
-  {bits: 2, name: 'fmt',    attr: ['2','Q'], type: 8},
-  {bits: 5, name: 'rs3',    attr: ['5','src3'], type: 8},
-]}
-....
-
-//[wavedrom, ,]
-//....
-//{reg: [
-//  {bits: 7, name: 'opcode', attr: 'OP-FP',    type: 8},
-//  {bits: 5, name: 'rd',     attr: 'dest',     type: 2},
-//  {bits: 3, name: 'funct3',  attr: ['MIN', 'MAX'], type: 8},
-//  {bits: 5, name: 'rs1',    attr: 'src1',     type: 4},
-//  {bits: 5, name: 'rs2',    attr: 'src2',     type: 4},
-//  {bits: 2, name: 'fmt',    attr: 'Q',        type: 8},
-//  {bits: 5, name: 'funct5', attr: 'FMIN-MAX', type: 8},
-//]}
-//....
-
-
-//[wavedrom, ,]
-//....
-//{reg: [
-//  {bits: 7, name: 'opcode', attr: ['FMADD', 'FNMADD', 'FMSUB', 'FNMSUB'],    type: 8},
-//  {bits: 5, name: 'rd',     attr: 'dest',     type: 2},
-//  {bits: 3, name: 'funct3',  attr: 'RM', type: 8},
-//  {bits: 5, name: 'rs1',    attr: 'src1',     type: 4},
-//  {bits: 5, name: 'rs2',    attr: 'src2',     type: 4},
-//  {bits: 2, name: 'fmt',    attr: 'Q',        type: 8},
-//  {bits: 5, name: 'rs3',    attr: 'src3',     type: 4},
-//]}
-//....
-\ No newline at end of file
diff --git a/src/images/wavedrom/quad-compute.edn b/src/images/wavedrom/quad-compute.edn
new file mode 100644
index 0000000..2451ac9
--- /dev/null
+++ b/src/images/wavedrom/quad-compute.edn
@@ -0,0 +1,54 @@
+//## 14.2 Quad-Precision Computational Instructions
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP']},
+  {bits: 5, name: 'rd',     attr: ['5','dest','dest','dest','dest']},
+  {bits: 3, name: 'rm',     attr: ['3','RM','RM','MIN/MAX','RM']},
+  {bits: 5, name: 'rs1',    attr: ['5','src1','src1','src1','src']},
+  {bits: 5, name: 'rs2',    attr: ['5','src2','src2','src2','0']},
+  {bits: 2, name: 'fmt',    attr: ['2','Q','Q','Q','Q']},
+  {bits: 5, name: 'funct5', attr: ['5','FADD/FSUB', 'FMUL/FDIV', 'FMIN-MAX', 'FSQRT']},
+]}
+....
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7, name: 'opcode', attr: ['7','F[N]MADD/F[N]MSUB']},
+  {bits: 5, name: 'rd',     attr: ['5','dest']},
+  {bits: 3, name: 'rm',     attr: ['3','RM']},
+  {bits: 5, name: 'rs1',    attr: ['5','src1']},
+  {bits: 5, name: 'rs2',    attr: ['5','src2']},
+  {bits: 2, name: 'fmt',    attr: ['2','Q']},
+  {bits: 5, name: 'rs3',    attr: ['5','src3']},
+]}
+....
+
+//[wavedrom, ,]
+//....
+//{reg: [
+//  {bits: 7, name: 'opcode', attr: 'OP-FP'},
+//  {bits: 5, name: 'rd',     attr: 'dest'},
+//  {bits: 3, name: 'funct3',  attr: ['MIN', 'MAX']},
+//  {bits: 5, name: 'rs1',    attr: 'src1'},
+//  {bits: 5, name: 'rs2',    attr: 'src2'},
+//  {bits: 2, name: 'fmt',    attr: 'Q'},
+//  {bits: 5, name: 'funct5', attr: 'FMIN-MAX'},
+//]}
+//....
+
+
+//[wavedrom, ,]
+//....
+//{reg: [
+//  {bits: 7, name: 'opcode', attr: ['FMADD', 'FNMADD', 'FMSUB', 'FNMSUB']},
+//  {bits: 5, name: 'rd',     attr: 'dest'}
+//  {bits: 3, name: 'funct3',  attr: 'RM'},
+//  {bits: 5, name: 'rs1',    attr: 'src1'},
+//  {bits: 5, name: 'rs2',    attr: 'src2'},
+//  {bits: 2, name: 'fmt',    attr: 'Q'},
+//  {bits: 5, name: 'rs3',    attr: 'src3'},
+//]}
+//....
+\ No newline at end of file
diff --git a/src/images/wavedrom/quad-float-clssfy.adoc b/src/images/wavedrom/quad-float-clssfy.adoc
deleted file mode 100644
index 0023c7d..0000000
--- a/src/images/wavedrom/quad-float-clssfy.adoc
+++ /dev/null
@@ -1,15 +0,0 @@
-//## 14.5 Quad-Precision Floating-Point Classify Instruction
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7, name: 'opcode', attr: ['7','OP-FP'], type: 8},
-  {bits: 5, name: 'rd',     attr: ['5','dest'], type: 2},
-  {bits: 3, name: 'rm',     attr: ['3','001'], type: 8},
-  {bits: 5, name: 'rs1',    attr: ['5','src'], type: 4},
-  {bits: 5, name: 'rs2',    attr: ['5','0'], type: 8},
-  {bits: 2, name: 'fmt',    attr: ['2','Q'], type: 8},
-  {bits: 5, name: 'funct5', attr: ['5','FCLASS'], type: 8},
-]}
-....
-
diff --git a/src/images/wavedrom/quad-float-clssfy.edn b/src/images/wavedrom/quad-float-clssfy.edn
new file mode 100644
index 0000000..325239e
--- /dev/null
+++ b/src/images/wavedrom/quad-float-clssfy.edn
@@ -0,0 +1,15 @@
+//## 14.5 Quad-Precision Floating-Point Classify Instruction
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7, name: 'opcode', attr: ['7','OP-FP']},
+  {bits: 5, name: 'rd',     attr: ['5','dest']},
+  {bits: 3, name: 'rm',     attr: ['3','001']},
+  {bits: 5, name: 'rs1',    attr: ['5','src']},
+  {bits: 5, name: 'rs2',    attr: ['5','0']},
+  {bits: 2, name: 'fmt',    attr: ['2','Q']},
+  {bits: 5, name: 'funct5', attr: ['5','FCLASS']},
+]}
+....
+
diff --git a/src/images/wavedrom/quad-float-compare.adoc b/src/images/wavedrom/quad-float-compare.adoc
deleted file mode 100644
index 2269bc9..0000000
--- a/src/images/wavedrom/quad-float-compare.adoc
+++ /dev/null
@@ -1,15 +0,0 @@
-//## 14.4 Quad-Precision Floating-Point Compare Instructions
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7, name: 'opcode', attr: ['7','OP-FP'], type: 8},
-  {bits: 5, name: 'rd',     attr: ['5','dest'], type: 2},
-  {bits: 3, name: 'rm',  attr: ['3','EQ/LT/LE'], type: 8},
-  {bits: 5, name: 'rs1',    attr: ['5','src1'], type: 4},
-  {bits: 5, name: 'rs2',    attr: ['5','src2'], type: 4},
-  {bits: 2, name: 'fmt',    attr: ['2','Q'], type: 8},
-  {bits: 5, name: 'funct5', attr: ['5','FCMP'], type: 8},
-]}
-....
-
diff --git a/src/images/wavedrom/quad-float-compare.edn b/src/images/wavedrom/quad-float-compare.edn
new file mode 100644
index 0000000..86e8f83
--- /dev/null
+++ b/src/images/wavedrom/quad-float-compare.edn
@@ -0,0 +1,15 @@
+//## 14.4 Quad-Precision Floating-Point Compare Instructions
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7, name: 'opcode', attr: ['7','OP-FP']},
+  {bits: 5, name: 'rd',     attr: ['5','dest']},
+  {bits: 3, name: 'rm',  attr: ['3','EQ/LT/LE']},
+  {bits: 5, name: 'rs1',    attr: ['5','src1']},
+  {bits: 5, name: 'rs2',    attr: ['5','src2']},
+  {bits: 2, name: 'fmt',    attr: ['2','Q']},
+  {bits: 5, name: 'funct5', attr: ['5','FCMP']},
+]}
+....
+
diff --git a/src/images/wavedrom/quad-ls.adoc b/src/images/wavedrom/quad-ls.adoc
deleted file mode 100644
index 3ba4099..0000000
--- a/src/images/wavedrom/quad-ls.adoc
+++ /dev/null
@@ -1,26 +0,0 @@
-//## 14.1 Quad-Precision Load and Store Instructions
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7,  name: 'opcode',    attr: ['7','LOAD-FP'],  type: 8},
-  {bits: 5,  name: 'rd',        attr: ['5','dest'],     type: 2},
-  {bits: 3,  name: 'width',     attr: ['3','Q'],        type: 8},
-  {bits: 5,  name: 'rs1',       attr: ['5','base'],     type: 4},
-  {bits: 12, name: 'imm[11:0]', attr: ['12','offset[11:0]'],   type: 3},
-]}
-....
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7,  name: 'opcode',    attr: ['7','STORE-FP'], type: 8},
-  {bits: 5,  name: 'imm[4:0]',  attr: ['5','offset[4:0]'],   type: 3},
-  {bits: 3,  name: 'width',     attr: ['3','Q'],        type: 8},
-  {bits: 5,  name: 'rs1',       attr: ['5','base'],     type: 4},
-  {bits: 5,  name: 'rs2',       attr: ['5','src'],      type: 4},
-  {bits: 7, name: 'imm[11:5]', attr: ['7','offset[11:5]'],   type: 3},
-]}
-....
-
-
diff --git a/src/images/wavedrom/quad-ls.edn b/src/images/wavedrom/quad-ls.edn
new file mode 100644
index 0000000..d855534
--- /dev/null
+++ b/src/images/wavedrom/quad-ls.edn
@@ -0,0 +1,26 @@
+//## 14.1 Quad-Precision Load and Store Instructions
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',    attr: ['7','LOAD-FP']},
+  {bits: 5,  name: 'rd',        attr: ['5','dest']},
+  {bits: 3,  name: 'width',     attr: ['3','Q']},
+  {bits: 5,  name: 'rs1',       attr: ['5','base']},
+  {bits: 12, name: 'imm[11:0]', attr: ['12','offset[11:0]']},
+]}
+....
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',    attr: ['7','STORE-FP']},
+  {bits: 5,  name: 'imm[4:0]',  attr: ['5','offset[4:0]']},
+  {bits: 3,  name: 'width',     attr: ['3','Q']},
+  {bits: 5,  name: 'rs1',       attr: ['5','base']},
+  {bits: 5,  name: 'rs2',       attr: ['5','src']},
+  {bits: 7, name: 'imm[11:5]', attr: ['7','offset[11:5]']},
+]}
+....
+
+
diff --git a/src/images/wavedrom/reg-based-ldnstr.adoc b/src/images/wavedrom/reg-based-ldnstr.edn
index ea9e245..031ea1a 100644
--- a/src/images/wavedrom/reg-based-ldnstr.adoc
+++ b/src/images/wavedrom/reg-based-ldnstr.edn
@@ -4,12 +4,12 @@
 [wavedrom, ,svg]
 ....
 {reg: [
-  {bits: 2, name: 'op', attr: ['2', 'C0', 'C0', 'C0', 'C0', 'C0'], type: 8},
-  {bits: 3, name: 'rdʹ',  attr: ['3', 'dest', 'dest','dest','dest','dest'], type: 3},
-  {bits: 2, name: 'imm', attr:['2', 'offset[2|6]', 'offset[7:6]', 'offset[7:6]', 'offset[2|6]', 'offset[7:6]'], type: 2},
-  {bits: 3, name: 'rs1ʹ', attr: ['3', 'base', 'base', 'base', 'base', 'base'], type: 2},
-  {bits: 3, name: 'imm',  attr: ['3', 'offset[5:3]', 'offset[5:3]', 'offset[5|4|8]', 'offset[5:3]', 'offset[5:3]'], type: 3},
-  {bits: 3, name: 'funct3',  attr: ['3', 'C.LW', 'C.LD', 'C.LQ', 'C.FLW', 'C.FLD'], type: 8},
+  {bits: 2, name: 'op', attr: ['2', 'C0', 'C0', 'C0', 'C0', 'C0']},
+  {bits: 3, name: 'rdʹ',  attr: ['3', 'dest', 'dest','dest','dest','dest']},
+  {bits: 2, name: 'imm', attr:['2', 'offset[2|6]', 'offset[7:6]', 'offset[7:6]', 'offset[2|6]', 'offset[7:6]']},
+  {bits: 3, name: 'rs1ʹ', attr: ['3', 'base', 'base', 'base', 'base', 'base']},
+  {bits: 3, name: 'imm',  attr: ['3', 'offset[5:3]', 'offset[5:3]', 'offset[5|4|8]', 'offset[5:3]', 'offset[5:3]']},
+  {bits: 3, name: 'funct3',  attr: ['3', 'C.LW', 'C.LD', 'C.LQ', 'C.FLW', 'C.FLD']},
 ], config: {bits: 16}}
 ....
 
diff --git a/src/images/wavedrom/rv64-lui-auipc.edn b/src/images/wavedrom/rv64-lui-auipc.edn
new file mode 100644
index 0000000..5850133
--- /dev/null
+++ b/src/images/wavedrom/rv64-lui-auipc.edn
@@ -0,0 +1,10 @@
+//lui-auipc
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',     attr: ['7', 'LUI', 'AUIPC']},
+  {bits: 5,  name: 'rd',         attr: ['5', 'dest', 'dest']},
+  {bits: 20, name: 'imm[31:12]', attr: ['20', 'U-immediate[31:12]', 'U-immediate[31:12]']}
+]}
+....
diff --git a/src/images/wavedrom/rv64_lui-auipc.adoc b/src/images/wavedrom/rv64_lui-auipc.adoc
deleted file mode 100644
index 132c770..0000000
--- a/src/images/wavedrom/rv64_lui-auipc.adoc
+++ /dev/null
@@ -1,10 +0,0 @@
-//lui-auipc
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7,  name: 'opcode',     attr: ['7', 'LUI', 'AUIPC'], type: 8},
-  {bits: 5,  name: 'rd',         attr: ['5', 'dest', 'dest'], type: 2},
-  {bits: 20, name: 'imm[31:12]', attr: ['20', 'U-immediate[31:12]', 'U-immediate[31:12]'], type: 3}
-]}
-....
diff --git a/src/images/wavedrom/rv64i-base-int.adoc b/src/images/wavedrom/rv64i-base-int.adoc
deleted file mode 100644
index e4edaf3..0000000
--- a/src/images/wavedrom/rv64i-base-int.adoc
+++ /dev/null
@@ -1,15 +0,0 @@
-//# 6 RV64I Base Integer Instruction Set, Version 2.1
-//## 6.2 Integer Computational Instructions
-//### Integer Register-Immediate Instructions
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7,  name: 'opcode',    attr: ['7', 'OP-IMM-32'], type: 8},
-  {bits: 5,  name: 'rd',        attr: ['5', 'dest'], type: 2},
-  {bits: 3,  name: 'funct3',     attr: ['3', 'ADDIW'], type: 8},
-  {bits: 5,  name: 'rs1',       attr: ['5', 'src'], type: 4},
-  {bits: 12, name: 'imm[11:0]', attr: ['12', 'I-immediate[11:0]'], type: 3}
-]}
-....
-
diff --git a/src/images/wavedrom/rv64i-base-int.edn b/src/images/wavedrom/rv64i-base-int.edn
new file mode 100644
index 0000000..4ff3b83
--- /dev/null
+++ b/src/images/wavedrom/rv64i-base-int.edn
@@ -0,0 +1,15 @@
+//# 6 RV64I Base Integer Instruction Set, Version 2.1
+//## 6.2 Integer Computational Instructions
+//### Integer Register-Immediate Instructions
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',    attr: ['7', 'OP-IMM-32']},
+  {bits: 5,  name: 'rd',        attr: ['5', 'dest']},
+  {bits: 3,  name: 'funct3',     attr: ['3', 'ADDIW']},
+  {bits: 5,  name: 'rs1',       attr: ['5', 'src']},
+  {bits: 12, name: 'imm[11:0]', attr: ['12', 'I-immediate[11:0]']}
+]}
+....
+
diff --git a/src/images/wavedrom/rv64i-int-reg-reg.edn b/src/images/wavedrom/rv64i-int-reg-reg.edn
new file mode 100644
index 0000000..6d29ec7
--- /dev/null
+++ b/src/images/wavedrom/rv64i-int-reg-reg.edn
@@ -0,0 +1,27 @@
+
+//rv64i int-reg-reg
+//### Integer Register-Register Operations
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',    attr: ['7', 'OP', 'OP', 'OP-32', 'OP-32', 'OP-32']},
+  {bits: 5,  name: 'rd',        attr: ['5', 'dest', 'dest', 'dest', 'dest', 'dest']},
+  {bits: 3,  name: 'funct3',    attr: ['3', 'SLL/SRL', 'SRA', 'ADDW', 'SLLW/SRLW', 'SUBW/SRAW']},
+  {bits: 5,  name: 'rs1',       attr: ['5', 'src1', 'src1', 'src1', 'src1', 'src1']},
+  {bits: 5,  name: 'rs2',       attr: ['5', 'src2', 'src2', 'src2', 'src2', 'src2']},
+  {bits: 7,  name: 'funct7',    attr: ['7', '0000000', '0100000', '0000000', '0000000', '0100000']}
+]}
+....
+
+//[wavedrom, ,svg]
+//....
+//{reg: [
+//  {bits: 7,  name: 'opcode',    attr: 'OP-32'},
+//  {bits: 5,  name: 'rd',        attr: 'dest'},
+//  {bits: 3,  name: 'funct3',     attr: ['ADDW', 'SLLW', 'SRLW', 'SUBW', 'SRAW']},
+//  {bits: 5,  name: 'rs1',       attr: 'src1'},
+//  {bits: 5,  name: 'rs2',       attr: 'src2'},
+//  {bits: 7,  name: 'funct7', attr: [0, 0, 0, 32, 32]}
+//]}
+//....
diff --git a/src/images/wavedrom/rv64i-slli.adoc b/src/images/wavedrom/rv64i-slli.edn
index 038a052..b261564 100644
--- a/src/images/wavedrom/rv64i-slli.adoc
+++ b/src/images/wavedrom/rv64i-slli.edn
@@ -1,11 +1,11 @@
 [wavedrom, ,svg]
 ....
 {reg: [
-  {bits: 7,  name: 'opcode',    attr: ['7', 'OP-IMM', 'OP-IMM', 'OP-IMM'], type: 8},
-  {bits: 5,  name: 'rd',        attr: ['5', 'dest', 'dest', 'dest'], type: 2},
-  {bits: 3,  name: 'funct3',    attr: ['3', 'SLLI', 'SRLI', 'SRAI'], type: 8},
-  {bits: 5,  name: 'rs1',       attr: ['5', 'src', 'src', 'src'], type: 4},
-  {bits: 6,  name: 'imm[5:0]',  attr: ['6', 'shamt[5:0]', 'shamt[5:0]', 'shamt[5:0]'], type: 3},
-  {bits: 6,  name: 'imm[11:6]', attr: ['6', '000000', '000000', '010000'], type: 8}
+  {bits: 7,  name: 'opcode',    attr: ['7', 'OP-IMM', 'OP-IMM', 'OP-IMM']},
+  {bits: 5,  name: 'rd',        attr: ['5', 'dest', 'dest', 'dest']},
+  {bits: 3,  name: 'funct3',    attr: ['3', 'SLLI', 'SRLI', 'SRAI']},
+  {bits: 5,  name: 'rs1',       attr: ['5', 'src', 'src', 'src']},
+  {bits: 6,  name: 'imm[5:0]',  attr: ['6', 'shamt[5:0]', 'shamt[5:0]', 'shamt[5:0]']},
+  {bits: 6,  name: 'imm[11:6]', attr: ['6', '000000', '000000', '010000']}
 ]}
 ....
diff --git a/src/images/wavedrom/rv64i-slliw.adoc b/src/images/wavedrom/rv64i-slliw.edn
index bd51e9b..0ca01ba 100644
--- a/src/images/wavedrom/rv64i-slliw.adoc
+++ b/src/images/wavedrom/rv64i-slliw.edn
@@ -1,12 +1,12 @@
 [wavedrom, ,svg]
 ....
 {reg: [
-  {bits: 7,  name: 'opcode',    attr: ['7', 'OP-IMM-32', 'OP-IMM-32', 'OP-IMM-32'], type: 8},
-  {bits: 5,  name: 'rd',        attr: ['5', 'dest', 'dest', 'dest'], type: 2},
-  {bits: 3,  name: 'funct3',    attr: ['3', 'SLLIW', 'SRLIW', 'SRAIW'], type: 8},
-  {bits: 5,  name: 'rs1',       attr: ['5', 'src', 'src', 'src'], type: 4},
-  {bits: 5,  name: 'imm[4:0]',  attr: ['5', 'shamt[4:0]', 'shamt[4:0]', 'shamt[4:0]'], type: 3},
-  {bits: 1,  name: '[5]',    attr: ['1', '0', '0', '0'], type: 3},
-  {bits: 6,  name: 'imm[11:6]', attr: ['6', '000000', '000000', '010000'], type: 8}
+  {bits: 7,  name: 'opcode',    attr: ['7', 'OP-IMM-32', 'OP-IMM-32', 'OP-IMM-32']},
+  {bits: 5,  name: 'rd',        attr: ['5', 'dest', 'dest', 'dest']},
+  {bits: 3,  name: 'funct3',    attr: ['3', 'SLLIW', 'SRLIW', 'SRAIW']},
+  {bits: 5,  name: 'rs1',       attr: ['5', 'src', 'src', 'src']},
+  {bits: 5,  name: 'imm[4:0]',  attr: ['5', 'shamt[4:0]', 'shamt[4:0]', 'shamt[4:0]']},
+  {bits: 1,  name: '[5]',    attr: ['1', '0', '0', '0']},
+  {bits: 6,  name: 'imm[11:6]', attr: ['6', '000000', '000000', '010000']}
 ]}
 ....
diff --git a/src/images/wavedrom/rv64i_int-reg-reg.adoc b/src/images/wavedrom/rv64i_int-reg-reg.adoc
deleted file mode 100644
index a69e718..0000000
--- a/src/images/wavedrom/rv64i_int-reg-reg.adoc
+++ /dev/null
@@ -1,27 +0,0 @@
-
-//rv64i int-reg-reg
-//### Integer Register-Register Operations
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7,  name: 'opcode',    attr: ['7', 'OP', 'OP', 'OP-32', 'OP-32', 'OP-32'], type: 8},
-  {bits: 5,  name: 'rd',        attr: ['5', 'dest', 'dest', 'dest', 'dest', 'dest'], type: 2},
-  {bits: 3,  name: 'funct3',    attr: ['3', 'SLL/SRL', 'SRA', 'ADDW', 'SLLW/SRLW', 'SUBW/SRAW'], type: 8},
-  {bits: 5,  name: 'rs1',       attr: ['5', 'src1', 'src1', 'src1', 'src1', 'src1'], type: 4},
-  {bits: 5,  name: 'rs2',       attr: ['5', 'src2', 'src2', 'src2', 'src2', 'src2'], type: 4},
-  {bits: 7,  name: 'funct7',    attr: ['7', '000000', '010000', '000000', '000000', '010000'], type: 8}
-]}
-....
-
-//[wavedrom, ,svg]
-//....
-//{reg: [
-//  {bits: 7,  name: 'opcode',    attr: 'OP-32', type: 8},
-//  {bits: 5,  name: 'rd',        attr: 'dest', type: 2},
-//  {bits: 3,  name: 'funct3',     attr: ['ADDW', 'SLLW', 'SRLW', 'SUBW', 'SRAW'], type: 8},
-//  {bits: 5,  name: 'rs1',       attr: 'src1', type: 4},
-//  {bits: 5,  name: 'rs2',       attr: 'src2', type: 4},
-//  {bits: 7,  name: 'funct7', attr: [0, 0, 0, 32, 32], type: 8}
-//]}
-//....
diff --git a/src/images/wavedrom/s-immediate.edn b/src/images/wavedrom/s-immediate.edn
new file mode 100644
index 0000000..324b4a3
--- /dev/null
+++ b/src/images/wavedrom/s-immediate.edn
@@ -0,0 +1,11 @@
+//#### S-immediate
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 1,  name: '[7]'},
+  {bits: 4,  name: 'inst[11:8]'},
+  {bits: 6,  name: 'inst[30:25]'},
+  {bits: 21,  name: '— inst[31] —'},
+], config:{fontsize: 12, label:{right: 'S-immediate'}}}
+....
+\ No newline at end of file
diff --git a/src/images/wavedrom/sfenceinvalir.edn b/src/images/wavedrom/sfenceinvalir.edn
index 639be34..747df40 100644
--- a/src/images/wavedrom/sfenceinvalir.edn
+++ b/src/images/wavedrom/sfenceinvalir.edn
@@ -1,11 +1,11 @@
 [wavedrom, ,svg]
 ....
 {reg: [
-  {bits: 7,  name: 'opcode',    attr: ['7', 'SYSTEM'],  type: 8},
-  {bits: 5,  name: 'rd',        attr: ['5', '0'],     type: 2},
-  {bits: 3,  name: 'funct3',     attr: ['3', 'PRIV'],    type: 8},
-  {bits: 5,  name: 'rs1',       attr: ['5', '0'],     type: 4},
-  {bits: 5,  name: 'rs2',       attr: ['5', '1'],     type: 4},
-  {bits: 7,  name: 'funct7',     attr: ['7', 'SFENCE.INVAL.IR'],    type: 8},
+  {bits: 7,  name: 'opcode',    attr: ['7', 'SYSTEM']},
+  {bits: 5,  name: 'rd',        attr: ['5', '0']},
+  {bits: 3,  name: 'funct3',     attr: ['3', 'PRIV']},
+  {bits: 5,  name: 'rs1',       attr: ['5', '0']},
+  {bits: 5,  name: 'rs2',       attr: ['5', '1']},
+  {bits: 7,  name: 'funct7',     attr: ['7', 'SFENCE.INVAL.IR']},
 ]}
 ....
 \ No newline at end of file
diff --git a/src/images/wavedrom/sfencevma.edn b/src/images/wavedrom/sfencevma.edn
index a7a7663..e06d949 100644
--- a/src/images/wavedrom/sfencevma.edn
+++ b/src/images/wavedrom/sfencevma.edn
@@ -1,11 +1,11 @@
 [wavedrom, ,svg]
 ....
 {reg: [
-  {bits: 7,  name: 'opcode', attr: ['7', 'SYSTEM'], type: 8},
-  {bits: 5,  name: 'rd', attr: ['5', '0'], type: 2},
-  {bits: 3,  name: 'funct3', attr: ['3', 'PRIV'], type: 8},
-  {bits: 5,  name: 'rs1', attr: ['5', 'vaddr'], type: 4},
-  {bits: 5,  name: 'rs2', attr: ['5', 'asid'], type: 4},
-  {bits: 7,  name: 'funct7', attr: ['7', 'SFENCE.VMA'], type: 8},
+  {bits: 7,  name: 'opcode', attr: ['7', 'SYSTEM']},
+  {bits: 5,  name: 'rd', attr: ['5', '0']},
+  {bits: 3,  name: 'funct3', attr: ['3', 'PRIV']},
+  {bits: 5,  name: 'rs1', attr: ['5', 'vaddr']},
+  {bits: 5,  name: 'rs2', attr: ['5', 'asid']},
+  {bits: 7,  name: 'funct7', attr: ['7', 'SFENCE.VMA']},
 ]}
 ....
 \ No newline at end of file
diff --git a/src/images/wavedrom/sfencewinval.edn b/src/images/wavedrom/sfencewinval.edn
index 2973af8..712f1c1 100644
--- a/src/images/wavedrom/sfencewinval.edn
+++ b/src/images/wavedrom/sfencewinval.edn
@@ -1,11 +1,11 @@
 [wavedrom, ,svg]
 ....
 {reg: [
-  {bits: 7,  name: 'opcode',    attr: ['7', 'SYSTEM'],  type: 8},
-  {bits: 5,  name: 'rd',        attr: ['5', '0'],     type: 2},
-  {bits: 3,  name: 'funct3',     attr: ['3', 'PRIV'],    type: 8},
-  {bits: 5,  name: 'rs1',       attr: ['5', '0'],     type: 4},
-  {bits: 5,  name: 'rs2',       attr: ['5', '0'],     type: 4},
-  {bits: 7,  name: 'funct7',     attr: ['7', 'SFENCE.W.INVAL'],    type: 8},
+  {bits: 7,  name: 'opcode',    attr: ['7', 'SYSTEM']},
+  {bits: 5,  name: 'rd',        attr: ['5', '0']},
+  {bits: 3,  name: 'funct3',     attr: ['3', 'PRIV']},
+  {bits: 5,  name: 'rs1',       attr: ['5', '0']},
+  {bits: 5,  name: 'rs2',       attr: ['5', '0']},
+  {bits: 7,  name: 'funct7',     attr: ['7', 'SFENCE.W.INVAL']},
 ]}
 ....
 \ No newline at end of file
diff --git a/src/images/wavedrom/sinvalvma.edn b/src/images/wavedrom/sinvalvma.edn
index 89d0d40..1752a52 100644
--- a/src/images/wavedrom/sinvalvma.edn
+++ b/src/images/wavedrom/sinvalvma.edn
@@ -1,11 +1,11 @@
 [wavedrom, ,svg]
 ....
 {reg: [
-  {bits: 7,  name: 'opcode',    attr: ['7', 'SYSTEM'],  type: 8},
-  {bits: 5,  name: 'rd',        attr: ['5', '0'],     type: 2},
-  {bits: 3,  name: 'funct3',     attr: ['3', 'PRIV'],    type: 8},
-  {bits: 5,  name: 'rs1',       attr: ['5', 'vaddr'],     type: 4},
-  {bits: 5,  name: 'rs2',       attr: ['5', 'asid'],     type: 4},
-  {bits: 7,  name: 'funct7',     attr: ['7', 'SINVAL.VMA'],    type: 8},
+  {bits: 7,  name: 'opcode',    attr: ['7', 'SYSTEM']},
+  {bits: 5,  name: 'rd',        attr: ['5', '0']},
+  {bits: 3,  name: 'funct3',     attr: ['3', 'PRIV']},
+  {bits: 5,  name: 'rs1',       attr: ['5', 'vaddr']},
+  {bits: 5,  name: 'rs2',       attr: ['5', 'asid']},
+  {bits: 7,  name: 'funct7',     attr: ['7', 'SINVAL.VMA']},
 ]}
 ....
 \ No newline at end of file
diff --git a/src/images/wavedrom/sp-load-store-2.adoc b/src/images/wavedrom/sp-load-store-2.adoc
deleted file mode 100644
index f1025e9..0000000
--- a/src/images/wavedrom/sp-load-store-2.adoc
+++ /dev/null
@@ -1,24 +0,0 @@
-//## 12.5 Single-Precision Load and Store Instructions
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7,  name: 'opcode',    attr: ['7', 'LOAD-FP'],  type: 8},
-  {bits: 5,  name: 'rd',        attr: ['5', 'dest'],     type: 2},
-  {bits: 3,  name: 'width',     attr: ['3', 'W'],    type: 8},
-  {bits: 5,  name: 'rs1',       attr: ['5', 'base'],     type: 4},
-  {bits: 12, name: 'imm[11:0]', attr: ['12', 'offset[11:0]'],   type: 3},
-]}
-....
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7,  name: 'opcode',    attr: ['7', 'STORE-FP'], type: 8},
-  {bits: 5,  name: 'imm[4:0]',  attr: ['5', 'offset[4:0]'],   type: 3},
-  {bits: 3,  name: 'width',     attr: ['3', 'W'],    type: 8},
-  {bits: 5,  name: 'rs1',       attr: ['5', 'base'],     type: 4},
-  {bits: 5,  name: 'rs2',       attr: ['5', 'src'],      type: 4},
-  {bits: 7, name: 'imm[11:5]', attr: ['7', 'offset[11:5]'],   type: 3},
-]}
-....
-\ No newline at end of file
diff --git a/src/images/wavedrom/sp-load-store-2.edn b/src/images/wavedrom/sp-load-store-2.edn
new file mode 100644
index 0000000..a95b861
--- /dev/null
+++ b/src/images/wavedrom/sp-load-store-2.edn
@@ -0,0 +1,24 @@
+//## 12.5 Single-Precision Load and Store Instructions
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',    attr: ['7', 'LOAD-FP']},
+  {bits: 5,  name: 'rd',        attr: ['5', 'dest']},
+  {bits: 3,  name: 'width',     attr: ['3', 'W']},
+  {bits: 5,  name: 'rs1',       attr: ['5', 'base']},
+  {bits: 12, name: 'imm[11:0]', attr: ['12', 'offset[11:0]']},
+]}
+....
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',    attr: ['7', 'STORE-FP']},
+  {bits: 5,  name: 'imm[4:0]',  attr: ['5', 'offset[4:0]']},
+  {bits: 3,  name: 'width',     attr: ['3', 'W']},
+  {bits: 5,  name: 'rs1',       attr: ['5', 'base']},
+  {bits: 5,  name: 'rs2',       attr: ['5', 'src']},
+  {bits: 7, name: 'imm[11:5]', attr: ['7', 'offset[11:5]']},
+]}
+....
+\ No newline at end of file
diff --git a/src/images/wavedrom/sp-load-store.adoc b/src/images/wavedrom/sp-load-store.adoc
deleted file mode 100644
index 192626b..0000000
--- a/src/images/wavedrom/sp-load-store.adoc
+++ /dev/null
@@ -1,25 +0,0 @@
-//## 12.5 Single-Precision Load and Store Instructions
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7,  name: 'opcode',    attr: ['7', 'LOAD-FP'],  type: 8},
-  {bits: 5,  name: 'rd',        attr: ['5', 'dest'],     type: 2},
-  {bits: 3,  name: 'width',     attr: ['3', 'H'],    type: 8},
-  {bits: 5,  name: 'rs1',       attr: ['5', 'base'],     type: 4},
-  {bits: 12, name: 'imm[11:0]', attr: ['12', 'offset[11:0]'],   type: 3},
-]}
-....
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7,  name: 'opcode',    attr: ['7', 'STORE-FP'], type: 8},
-  {bits: 5,  name: 'imm[4:0]',  attr: ['5', 'offset[4:0]'],   type: 3},
-  {bits: 3,  name: 'width',     attr: ['3', 'H'],    type: 8},
-  {bits: 5,  name: 'rs1',       attr: ['5', 'base'],     type: 4},
-  {bits: 5,  name: 'rs2',       attr: ['5', 'src'],      type: 4},
-  {bits: 7, name: 'imm[11:5]', attr: ['7', 'offset[11:5]'],   type: 3},
-]}
-....
-
diff --git a/src/images/wavedrom/sp-load-store.edn b/src/images/wavedrom/sp-load-store.edn
new file mode 100644
index 0000000..6b1fe49
--- /dev/null
+++ b/src/images/wavedrom/sp-load-store.edn
@@ -0,0 +1,25 @@
+//## 12.5 Single-Precision Load and Store Instructions
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',    attr: ['7', 'LOAD-FP']},
+  {bits: 5,  name: 'rd',        attr: ['5', 'dest']},
+  {bits: 3,  name: 'width',     attr: ['3', 'H']},
+  {bits: 5,  name: 'rs1',       attr: ['5', 'base']},
+  {bits: 12, name: 'imm[11:0]', attr: ['12', 'offset[11:0]']},
+]}
+....
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',    attr: ['7', 'STORE-FP']},
+  {bits: 5,  name: 'imm[4:0]',  attr: ['5', 'offset[4:0]']},
+  {bits: 3,  name: 'width',     attr: ['3', 'H']},
+  {bits: 5,  name: 'rs1',       attr: ['5', 'base']},
+  {bits: 5,  name: 'rs2',       attr: ['5', 'src']},
+  {bits: 7, name: 'imm[11:5]', attr: ['7', 'offset[11:5]']},
+]}
+....
+
diff --git a/src/images/wavedrom/spfloat-classify.adoc b/src/images/wavedrom/spfloat-classify.adoc
deleted file mode 100644
index 236880d..0000000
--- a/src/images/wavedrom/spfloat-classify.adoc
+++ /dev/null
@@ -1,14 +0,0 @@
-//## 12.9 Single-Precision Floating-Point Classify Instruction
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7, name: 'opcode', attr: ['7','OP-FP'],  type: 8},
-  {bits: 5, name: 'rd',     attr: ['5','dest'],   type: 2},
-  {bits: 3, name: 'rm',     attr: ['3','001'],        type: 8},
-  {bits: 5, name: 'rs1',    attr: ['5','src'],    type: 4},
-  {bits: 5, name: 'rs2',    attr: ['5','0'],        type: 8},
-  {bits: 2, name: 'fmt',    attr: ['2','S'],      type: 8},
-  {bits: 5, name: 'funct5', attr: ['5','FCLASS'], type: 8},
-]}
-....
diff --git a/src/images/wavedrom/spfloat-classify.edn b/src/images/wavedrom/spfloat-classify.edn
new file mode 100644
index 0000000..52ec8bc
--- /dev/null
+++ b/src/images/wavedrom/spfloat-classify.edn
@@ -0,0 +1,14 @@
+//## 12.9 Single-Precision Floating-Point Classify Instruction
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7, name: 'opcode', attr: ['7','OP-FP']},
+  {bits: 5, name: 'rd',     attr: ['5','dest']},
+  {bits: 3, name: 'rm',     attr: ['3','001']},
+  {bits: 5, name: 'rs1',    attr: ['5','src']},
+  {bits: 5, name: 'rs2',    attr: ['5','0']},
+  {bits: 2, name: 'fmt',    attr: ['2','S']},
+  {bits: 5, name: 'funct5', attr: ['5','FCLASS']},
+]}
+....
diff --git a/src/images/wavedrom/spfloat-cn-cmp.adoc b/src/images/wavedrom/spfloat-cn-cmp.adoc
deleted file mode 100644
index e46a099..0000000
--- a/src/images/wavedrom/spfloat-cn-cmp.adoc
+++ /dev/null
@@ -1,16 +0,0 @@
-//sp float convert and compare
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7, name: 'opcode', attr: ['7','OP-FP', 'OP-FP'],        type: 8},
-  {bits: 5, name: 'rd',     attr: ['5','dest', 'dest'],         type: 2},
-  {bits: 3, name: 'rm',  attr: ['3','RM','RM'],           type: 8},
-  {bits: 5, name: 'rs1',    attr: ['5','src', 'src'],         type: 4},
-  {bits: 5, name: 'rs2',    attr: ['5','W[U]/L[U]D', 'W[U]/L[U]'], type: 4},
-  {bits: 2, name: 'fmt',    attr: ['2','S','S'],      type: 8},
-  {bits: 5, name: 'funct5', attr: ['5','FCVT.int.fmt', 'FCVT.fmt.int'], type: 8},
-]}
-....
-
-
diff --git a/src/images/wavedrom/spfloat-cn-cmp.edn b/src/images/wavedrom/spfloat-cn-cmp.edn
new file mode 100644
index 0000000..0e5db87
--- /dev/null
+++ b/src/images/wavedrom/spfloat-cn-cmp.edn
@@ -0,0 +1,16 @@
+//sp float convert and compare
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7, name: 'opcode', attr: ['7','OP-FP', 'OP-FP']},
+  {bits: 5, name: 'rd',     attr: ['5','dest', 'dest']},
+  {bits: 3, name: 'rm',  attr: ['3','RM','RM']},
+  {bits: 5, name: 'rs1',    attr: ['5','src', 'src']},
+  {bits: 5, name: 'rs2',    attr: ['5','W[U]/L[U]D', 'W[U]/L[U]']},
+  {bits: 2, name: 'fmt',    attr: ['2','S','S']},
+  {bits: 5, name: 'funct5', attr: ['5','FCVT.int.fmt', 'FCVT.fmt.int']},
+]}
+....
+
+
diff --git a/src/images/wavedrom/spfloat-comp.adoc b/src/images/wavedrom/spfloat-comp.adoc
deleted file mode 100644
index 7059e8e..0000000
--- a/src/images/wavedrom/spfloat-comp.adoc
+++ /dev/null
@@ -1,15 +0,0 @@
-//## 12.8 Single-Precision Floating-Point Compare Instructions
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7, name: 'opcode', attr: ['7','OP-FP'],  type: 8},
-  {bits: 5, name: 'rd',     attr: ['5','dest'],   type: 2},
-  {bits: 3, name: 'rm',  attr: ['3','EQ', 'LT', 'LE'], type: 8},
-  {bits: 5, name: 'rs1',    attr: ['5','src1'],   type: 4},
-  {bits: 5, name: 'rs2',    attr: ['5','src2'],   type: 4},
-  {bits: 2, name: 'fmt',    attr: ['2','S'],      type: 8},
-  {bits: 5, name: 'funct5', attr: ['5','FCMP'],   type: 8},
-]}
-....
-
diff --git a/src/images/wavedrom/spfloat-comp.edn b/src/images/wavedrom/spfloat-comp.edn
new file mode 100644
index 0000000..05012a7
--- /dev/null
+++ b/src/images/wavedrom/spfloat-comp.edn
@@ -0,0 +1,15 @@
+//## 12.8 Single-Precision Floating-Point Compare Instructions
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7, name: 'opcode', attr: ['7','OP-FP']},
+  {bits: 5, name: 'rd',     attr: ['5','dest']},
+  {bits: 3, name: 'rm',  attr: ['3','EQ', 'LT', 'LE']},
+  {bits: 5, name: 'rs1',    attr: ['5','src1']},
+  {bits: 5, name: 'rs2',    attr: ['5','src2']},
+  {bits: 2, name: 'fmt',    attr: ['2','S']},
+  {bits: 5, name: 'funct5', attr: ['5','FCMP']},
+]}
+....
+
diff --git a/src/images/wavedrom/spfloat-mv.adoc b/src/images/wavedrom/spfloat-mv.adoc
deleted file mode 100644
index d5df81d..0000000
--- a/src/images/wavedrom/spfloat-mv.adoc
+++ /dev/null
@@ -1,15 +0,0 @@
-//SP flating point move
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP'],    type: 8},
-  {bits: 5, name: 'rd',     attr: ['5','dest','dest'],     type: 2},
-  {bits: 3, name: 'rm',     attr: ['3','000', '000'], type: 8},
-  {bits: 5, name: 'rs1',    attr: ['5','src','src'],     type: 4},
-  {bits: 5, name: 'rs2',    attr: ['5','0','0'],     type: 4},
-  {bits: 2, name: 'fmt',    attr: ['2','S','S'],        type: 8},
-  {bits: 5, name: 'funct5', attr: ['5','FMV.X.W','FMV.W.X'], type: 8},
-]}
-....
-
diff --git a/src/images/wavedrom/spfloat-mv.edn b/src/images/wavedrom/spfloat-mv.edn
new file mode 100644
index 0000000..47a63ee
--- /dev/null
+++ b/src/images/wavedrom/spfloat-mv.edn
@@ -0,0 +1,15 @@
+//SP flating point move
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP']},
+  {bits: 5, name: 'rd',     attr: ['5','dest','dest']},
+  {bits: 3, name: 'rm',     attr: ['3','000', '000']},
+  {bits: 5, name: 'rs1',    attr: ['5','src','src']},
+  {bits: 5, name: 'rs2',    attr: ['5','0','0']},
+  {bits: 2, name: 'fmt',    attr: ['2','S','S']},
+  {bits: 5, name: 'funct5', attr: ['5','FMV.X.W','FMV.W.X']},
+]}
+....
+
diff --git a/src/images/wavedrom/spfloat-sign-inj.adoc b/src/images/wavedrom/spfloat-sign-inj.adoc
deleted file mode 100644
index 74040b7..0000000
--- a/src/images/wavedrom/spfloat-sign-inj.adoc
+++ /dev/null
@@ -1,14 +0,0 @@
-//sp float sign injection
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7, name: 'opcode', attr: ['7','OP-FP'],        type: 8},
-  {bits: 5, name: 'rd',     attr: ['5', 'dest'],         type: 2},
-  {bits: 3, name: 'rm',  attr: ['3','J[N]/JX'],           type: 8},
-  {bits: 5, name: 'rs1',    attr: ['5','src1'],         type: 4},
-  {bits: 5, name: 'rs2',    attr: ['5','src2'], type: 4},
-  {bits: 2, name: 'fmt',    attr: ['2','S'],      type: 8},
-  {bits: 5, name: 'funct5', attr: ['5','FSGNJ'], type: 8},
-]}
-....
-\ No newline at end of file
diff --git a/src/images/wavedrom/spfloat-sign-inj.edn b/src/images/wavedrom/spfloat-sign-inj.edn
new file mode 100644
index 0000000..8c81976
--- /dev/null
+++ b/src/images/wavedrom/spfloat-sign-inj.edn
@@ -0,0 +1,14 @@
+//sp float sign injection
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7, name: 'opcode', attr: ['7','OP-FP']},
+  {bits: 5, name: 'rd',     attr: ['5', 'dest']},
+  {bits: 3, name: 'rm',  attr: ['3','J[N]/JX']},
+  {bits: 5, name: 'rs1',    attr: ['5','src1']},
+  {bits: 5, name: 'rs2',    attr: ['5','src2']},
+  {bits: 2, name: 'fmt',    attr: ['2','S']},
+  {bits: 5, name: 'funct5', attr: ['5','FSGNJ']},
+]}
+....
+\ No newline at end of file
diff --git a/src/images/wavedrom/spfloat-zfh.adoc b/src/images/wavedrom/spfloat-zfh.edn
index d53e6bd..4221c2d 100644
--- a/src/images/wavedrom/spfloat-zfh.adoc
+++ b/src/images/wavedrom/spfloat-zfh.edn
@@ -3,12 +3,12 @@
 [wavedrom, ,svg]
 ....
 {reg: [
-  {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP'],    type: 8},
-  {bits: 5, name: 'rd',     attr: ['5','dest','dest','dest','dest'],     type: 2},
-  {bits: 3, name: 'rm',  attr: ['3','RM', 'RM', 'MIN/MAX', 'RM'],       type: 8},
-  {bits: 5, name: 'rs1',    attr: ['5','src1', 'src1', 'src1', 'src'],     type: 4},
-  {bits: 5, name: 'rs2',    attr: ['5','src2', 'src2', 'src2', '0'],     type: 4},
-  {bits: 2, name: 'fmt',    attr: ['2','H', 'H', 'H', 'H'],        type: 8},
-  {bits: 5, name: 'funct5', attr: ['5', 'FADD/FSUB', 'FMUL/FDIV', 'FMIN-MAX', 'FSQRT'], type: 8},
+  {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP']},
+  {bits: 5, name: 'rd',     attr: ['5','dest','dest','dest','dest']},
+  {bits: 3, name: 'rm',  attr: ['3','RM', 'RM', 'MIN/MAX', 'RM']},
+  {bits: 5, name: 'rs1',    attr: ['5','src1', 'src1', 'src1', 'src']},
+  {bits: 5, name: 'rs2',    attr: ['5','src2', 'src2', 'src2', '0']},
+  {bits: 2, name: 'fmt',    attr: ['2','H', 'H', 'H', 'H']},
+  {bits: 5, name: 'funct5', attr: ['5', 'FADD/FSUB', 'FMUL/FDIV', 'FMIN-MAX', 'FSQRT']},
 ]}
 ....
 \ No newline at end of file
diff --git a/src/images/wavedrom/spfloat.adoc b/src/images/wavedrom/spfloat.edn
index 9384544..97679bd 100644
--- a/src/images/wavedrom/spfloat.adoc
+++ b/src/images/wavedrom/spfloat.edn
@@ -3,13 +3,13 @@
 [wavedrom, ,svg]
 ....
 {reg: [
-  {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP'],    type: 8},
-  {bits: 5, name: 'rd',     attr: ['5','dest','dest','dest','dest'],     type: 2},
-  {bits: 3, name: 'rm',  attr: ['3','RM', 'RM', 'RM','MIN/MAX'],       type: 8},
-  {bits: 5, name: 'rs1',    attr: ['5','src1', 'src1', 'src', 'src1'],     type: 4},
-  {bits: 5, name: 'rs2',    attr: ['5','src2', 'src2', '0', 'src2'],     type: 4},
-  {bits: 2, name: 'fmt',    attr: ['2','S', 'S', 'S', 'S'],        type: 8},
-  {bits: 5, name: 'funct5', attr: ['5', 'FADD/FSUB', 'FMUL/FDIV', 'FSQRT','FMIN-MAX'], type: 8},
+  {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP']},
+  {bits: 5, name: 'rd',     attr: ['5','dest','dest','dest','dest']},
+  {bits: 3, name: 'rm',  attr: ['3','RM', 'RM', 'RM','MIN/MAX']},
+  {bits: 5, name: 'rs1',    attr: ['5','src1', 'src1', 'src', 'src1']},
+  {bits: 5, name: 'rs2',    attr: ['5','src2', 'src2', '0', 'src2']},
+  {bits: 2, name: 'fmt',    attr: ['2','S', 'S', 'S', 'S']},
+  {bits: 5, name: 'funct5', attr: ['5', 'FADD/FSUB', 'FMUL/FDIV', 'FSQRT','FMIN-MAX']},
 ]}
 ....
 
diff --git a/src/images/wavedrom/spfloat2-zfh.adoc b/src/images/wavedrom/spfloat2-zfh.adoc
deleted file mode 100644
index 44789da..0000000
--- a/src/images/wavedrom/spfloat2-zfh.adoc
+++ /dev/null
@@ -1,12 +0,0 @@
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7, name: 'opcode', attr: ['7','F[N]MADD/F[N]MSUB'],    type: 8},
-  {bits: 5, name: 'rd',     attr: ['5','dest'],     type: 2},
-  {bits: 3, name: 'rm',     attr: ['3','RM'],       type: 8},
-  {bits: 5, name: 'rs1',    attr: ['5','src1'],     type: 4},
-  {bits: 5, name: 'rs2',    attr: ['5','src2'],     type: 4},
-  {bits: 2, name: 'fmt',    attr: ['2','H'],        type: 8},
-  {bits: 5, name: 'rs3', attr: ['5','src3'], type: 4},
-]}
-....
-\ No newline at end of file
diff --git a/src/images/wavedrom/spfloat2-zfh.edn b/src/images/wavedrom/spfloat2-zfh.edn
new file mode 100644
index 0000000..64d3fa7
--- /dev/null
+++ b/src/images/wavedrom/spfloat2-zfh.edn
@@ -0,0 +1,12 @@
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7, name: 'opcode', attr: ['7','F[N]MADD/F[N]MSUB']},
+  {bits: 5, name: 'rd',     attr: ['5','dest']},
+  {bits: 3, name: 'rm',     attr: ['3','RM']},
+  {bits: 5, name: 'rs1',    attr: ['5','src1']},
+  {bits: 5, name: 'rs2',    attr: ['5','src2']},
+  {bits: 2, name: 'fmt',    attr: ['2','H']},
+  {bits: 5, name: 'rs3', attr: ['5','src3']},
+]}
+....
+\ No newline at end of file
diff --git a/src/images/wavedrom/spfloat2.adoc b/src/images/wavedrom/spfloat2.adoc
deleted file mode 100644
index 8c2b976..0000000
--- a/src/images/wavedrom/spfloat2.adoc
+++ /dev/null
@@ -1,12 +0,0 @@
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7, name: 'opcode', attr: ['7','F[N]MADD/F[N]MSUB'],    type: 8},
-  {bits: 5, name: 'rd',     attr: ['5','dest'],     type: 2},
-  {bits: 3, name: 'rm',     attr: ['3','RM'],       type: 8},
-  {bits: 5, name: 'rs1',    attr: ['5','src1'],     type: 4},
-  {bits: 5, name: 'rs2',    attr: ['5','src2'],     type: 4},
-  {bits: 2, name: 'fmt',    attr: ['2','S'],        type: 8},
-  {bits: 5, name: 'rs3', attr: ['5','src3'], type: 4},
-]}
-....
-\ No newline at end of file
diff --git a/src/images/wavedrom/spfloat2.edn b/src/images/wavedrom/spfloat2.edn
new file mode 100644
index 0000000..cee5bdc
--- /dev/null
+++ b/src/images/wavedrom/spfloat2.edn
@@ -0,0 +1,12 @@
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7, name: 'opcode', attr: ['7','F[N]MADD/F[N]MSUB']},
+  {bits: 5, name: 'rd',     attr: ['5','dest']},
+  {bits: 3, name: 'rm',     attr: ['3','RM']},
+  {bits: 5, name: 'rs1',    attr: ['5','src1']},
+  {bits: 5, name: 'rs2',    attr: ['5','src2']},
+  {bits: 2, name: 'fmt',    attr: ['2','S']},
+  {bits: 5, name: 'rs3', attr: ['5','src3']},
+]}
+....
+\ No newline at end of file
diff --git a/src/images/wavedrom/sploat2.adoc b/src/images/wavedrom/sploat2.adoc
deleted file mode 100644
index e69de29..0000000
--- a/src/images/wavedrom/sploat2.adoc
+++ /dev/null
diff --git a/src/images/wavedrom/transformedatomicinst.edn b/src/images/wavedrom/transformedatomicinst.edn
index d598bc3..ab4f989 100644
--- a/src/images/wavedrom/transformedatomicinst.edn
+++ b/src/images/wavedrom/transformedatomicinst.edn
@@ -1,13 +1,13 @@
 [wavedrom, ,svg]
 ....
 {reg: [
-  {bits: 7, name: 'opcode', type: 8, attr: ['7']},
-  {bits: 5, name: 'rd', type: 2, attr: ['5']},
-  {bits: 3, name: 'funct3', type: 8, attr: ['3']},
-  {bits: 5, name: 'Addr. Offset', type: 4, attr: ['5']},
-  {bits: 5, name: 'rs2',type: 4, attr: ['5']},
-  {bits: 1, name: 'rl',type: 4, attr: ['1']},
-  {bits: 1, name: 'aq',type: 4, attr: ['1']},
-  {bits: 5, name: 'funct5', type: 8, attr: ['5']},
+  {bits: 7, name: 'opcode', attr: ['7']},
+  {bits: 5, name: 'rd', attr: ['5']},
+  {bits: 3, name: 'funct3', attr: ['3']},
+  {bits: 5, name: 'Addr. Offset', attr: ['5']},
+  {bits: 5, name: 'rs2', attr: ['5']},
+  {bits: 1, name: 'rl', attr: ['1']},
+  {bits: 1, name: 'aq', attr: ['1']},
+  {bits: 5, name: 'funct5', attr: ['5']},
 ], config: {bits: 32}}
 ....
 \ No newline at end of file
diff --git a/src/images/wavedrom/transformedloadinst.edn b/src/images/wavedrom/transformedloadinst.edn
index 0d6e5ab..3d14134 100644
--- a/src/images/wavedrom/transformedloadinst.edn
+++ b/src/images/wavedrom/transformedloadinst.edn
@@ -1,11 +1,11 @@
 [wavedrom, ,svg]
 ....
 {reg: [
-  {bits: 7, name: 'opcode', type: 8, attr: ['7']},
-  {bits: 5, name: 'rd', type: 2, attr: ['5']},
-  {bits: 3, name: 'funct3', type: 8, attr: ['3']},
-  {bits: 5, name: 'Addr. Offset', type: 4, attr: ['5']},
-  {bits: 5, name: '0', type: 4, attr: ['5']},
-  {bits: 7, name: '0', type: 8, attr: ['7']},
+  {bits: 7, name: 'opcode', attr: ['7']},
+  {bits: 5, name: 'rd', attr: ['5']},
+  {bits: 3, name: 'funct3', attr: ['3']},
+  {bits: 5, name: 'Addr. Offset', attr: ['5']},
+  {bits: 5, name: '0', attr: ['5']},
+  {bits: 7, name: '0', attr: ['7']},
 ], config: {bits: 32}}
 ....
 \ No newline at end of file
diff --git a/src/images/wavedrom/transformedstoreinst.edn b/src/images/wavedrom/transformedstoreinst.edn
index e807ad5..789a6e4 100644
--- a/src/images/wavedrom/transformedstoreinst.edn
+++ b/src/images/wavedrom/transformedstoreinst.edn
@@ -1,11 +1,11 @@
 [wavedrom, ,svg]
 ....
 {reg: [
-  {bits: 7, name: 'opcode', type: 8, attr: ['7']},
-  {bits: 5, name: '0', type: 2, attr: ['5']},
-  {bits: 3, name: 'funct3', type: 8, attr: ['3']},
-  {bits: 5, name: 'Addr. Offset', type: 4, attr: ['5']},
-  {bits: 5, name: 'rs2', type: 4, attr: ['5']},
-  {bits: 7, name: '0', type: 8, attr: ['7']},
+  {bits: 7, name: 'opcode', attr: ['7']},
+  {bits: 5, name: '0', attr: ['5']},
+  {bits: 3, name: 'funct3', attr: ['3']},
+  {bits: 5, name: 'Addr. Offset', attr: ['5']},
+  {bits: 5, name: 'rs2', attr: ['5']},
+  {bits: 7, name: '0', attr: ['7']},
 ], config: {bits: 32}}
 ....
 \ No newline at end of file
diff --git a/src/images/wavedrom/transformedvmaccessinst.edn b/src/images/wavedrom/transformedvmaccessinst.edn
index 9c7e9e3..65b6a1c 100644
--- a/src/images/wavedrom/transformedvmaccessinst.edn
+++ b/src/images/wavedrom/transformedvmaccessinst.edn
@@ -1,11 +1,11 @@
 [wavedrom, ,svg]
 ....
 {reg: [
-  {bits: 7, name: 'opcode', type: 8, attr: ['7']},
-  {bits: 5, name: 'rd', type: 2, attr: ['5']},
-  {bits: 3, name: 'funct3', type: 8, attr: ['3']},
-  {bits: 5, name: 'Addr. Offset', type: 4, attr: ['5']},
-  {bits: 5, name: 'rs2', type: 4, attr: ['5']},
-  {bits: 7, name: 'funct7', type: 8, attr: ['7']},
+  {bits: 7, name: 'opcode', attr: ['7']},
+  {bits: 5, name: 'rd', attr: ['5']},
+  {bits: 3, name: 'funct3', attr: ['3']},
+  {bits: 5, name: 'Addr. Offset', attr: ['5']},
+  {bits: 5, name: 'rs2', attr: ['5']},
+  {bits: 7, name: 'funct7', attr: ['7']},
 ], config: {bits: 32}}
 ....
 \ No newline at end of file
diff --git a/src/images/wavedrom/trap-return.adoc b/src/images/wavedrom/trap-return.adoc
deleted file mode 100644
index 1e15e2b..0000000
--- a/src/images/wavedrom/trap-return.adoc
+++ /dev/null
@@ -1,13 +0,0 @@
-//
-
-[wavedrom, ,svg]
-
-....
-{reg: [
-  {bits: 7, name: 'opcode', type: 8, attr: ['7','SYSTEM'],},
-  {bits: 5, name: 'rd', type: 2, attr: ['5','0'],},
-  {bits: 3, name: 'funct3', type: 8, attr: ['3','PRIV'],},
-  {bits: 5, name: 'rs1', type: 4, attr: ['5','0'],},
-  {bits: 12, name: 'funct12', type: 8, attr: ['12','MRET/SRET',]},
-], config: {bits: 32}}
-....
-\ No newline at end of file
diff --git a/src/images/wavedrom/trap-return.edn b/src/images/wavedrom/trap-return.edn
new file mode 100644
index 0000000..7467ad6
--- /dev/null
+++ b/src/images/wavedrom/trap-return.edn
@@ -0,0 +1,13 @@
+//
+
+[wavedrom, ,svg]
+
+....
+{reg: [
+  {bits: 7, name: 'opcode', attr: ['7','SYSTEM'],},
+  {bits: 5, name: 'rd', attr: ['5','0'],},
+  {bits: 3, name: 'funct3', attr: ['3','PRIV'],},
+  {bits: 5, name: 'rs1', attr: ['5','0'],},
+  {bits: 12, name: 'funct12', attr: ['12','MRET/SRET',]},
+], config: {bits: 32}}
+....
+\ No newline at end of file
diff --git a/src/images/wavedrom/u-immediate.edn b/src/images/wavedrom/u-immediate.edn
new file mode 100644
index 0000000..3b8ab61
--- /dev/null
+++ b/src/images/wavedrom/u-immediate.edn
@@ -0,0 +1,11 @@
+//#### U-immediate
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 12, name: '0'},
+  {bits: 8,  name: 'inst[19:12]'},
+  {bits: 11, name: 'inst[30:20]'},
+  {bits: 1,  name: '[31]'},
+], config:{fontsize: 12, label:{right: 'U-immediate'}}}
+....
+\ No newline at end of file
diff --git a/src/images/wavedrom/v-inst-table.adoc b/src/images/wavedrom/v-inst-table.edn
index 0c02220..0c02220 100644
--- a/src/images/wavedrom/v-inst-table.adoc
+++ b/src/images/wavedrom/v-inst-table.edn
diff --git a/src/images/wavedrom/valu-format.adoc b/src/images/wavedrom/valu-format.edn
index cdd3447..95732e7 100644
--- a/src/images/wavedrom/valu-format.adoc
+++ b/src/images/wavedrom/valu-format.edn
@@ -16,10 +16,10 @@ Formats for Vector Arithmetic Instructions under OP-V major opcode
 ....
 {reg: [
   {bits: 7, name: 0x57, attr: 'OPIVV'},
-  {bits: 5, name: 'vd', type: 2},
+  {bits: 5, name: 'vd'},
   {bits: 3, name: 0},
-  {bits: 5, name: 'vs1', type: 2},
-  {bits: 5, name: 'vs2', type: 2},
+  {bits: 5, name: 'vs1'},
+  {bits: 5, name: 'vs2'},
   {bits: 1, name: 'vm'},
   {bits: 6, name: 'funct6'},
 ]}
@@ -29,10 +29,10 @@ Formats for Vector Arithmetic Instructions under OP-V major opcode
 ....
 {reg: [
   {bits: 7, name: 0x57, attr: 'OPFVV'},
-  {bits: 5, name: 'vd / rd', type: 7},
+  {bits: 5, name: 'vd / rd'},
   {bits: 3, name: 1},
-  {bits: 5, name: 'vs1', type: 2},
-  {bits: 5, name: 'vs2', type: 2},
+  {bits: 5, name: 'vs1'},
+  {bits: 5, name: 'vs2'},
   {bits: 1, name: 'vm'},
   {bits: 6, name: 'funct6'},
 ]}
@@ -42,10 +42,10 @@ Formats for Vector Arithmetic Instructions under OP-V major opcode
 ....
 {reg: [
   {bits: 7, name: 0x57, attr: 'OPMVV'},
-  {bits: 5, name: 'vd / rd', type: 7},
+  {bits: 5, name: 'vd / rd'},
   {bits: 3, name: 2},
-  {bits: 5, name: 'vs1', type: 2},
-  {bits: 5, name: 'vs2', type: 2},
+  {bits: 5, name: 'vs1'},
+  {bits: 5, name: 'vs2'},
   {bits: 1, name: 'vm'},
   {bits: 6, name: 'funct6'},
 ]}
@@ -55,10 +55,10 @@ Formats for Vector Arithmetic Instructions under OP-V major opcode
 ....
 {reg: [
   {bits: 7, name: 0x57, attr: ['OPIVI']},
-  {bits: 5, name: 'vd', type: 2},
+  {bits: 5, name: 'vd'},
   {bits: 3, name: 3},
-  {bits: 5, name: 'imm[4:0]', type: 5},
-  {bits: 5, name: 'vs2', type: 2},
+  {bits: 5, name: 'imm[4:0]'},
+  {bits: 5, name: 'vs2'},
   {bits: 1, name: 'vm'},
   {bits: 6, name: 'funct6'},
 ]}
@@ -68,10 +68,10 @@ Formats for Vector Arithmetic Instructions under OP-V major opcode
 ....
 {reg: [
   {bits: 7, name: 0x57, attr: 'OPIVX'},
-  {bits: 5, name: 'vd', type: 2},
+  {bits: 5, name: 'vd'},
   {bits: 3, name: 4},
-  {bits: 5, name: 'rs1', type: 4},
-  {bits: 5, name: 'vs2', type: 2},
+  {bits: 5, name: 'rs1'},
+  {bits: 5, name: 'vs2'},
   {bits: 1, name: 'vm'},
   {bits: 6, name: 'funct6'},
 ]}
@@ -81,10 +81,10 @@ Formats for Vector Arithmetic Instructions under OP-V major opcode
 ....
 {reg: [
   {bits: 7, name: 0x57, attr: 'OPFVF'},
-  {bits: 5, name: 'vd', type: 2},
+  {bits: 5, name: 'vd'},
   {bits: 3, name: 5},
-  {bits: 5, name: 'rs1', type: 4},
-  {bits: 5, name: 'vs2', type: 2},
+  {bits: 5, name: 'rs1'},
+  {bits: 5, name: 'vs2'},
   {bits: 1, name: 'vm'},
   {bits: 6, name: 'funct6'},
 ]}
@@ -94,10 +94,10 @@ Formats for Vector Arithmetic Instructions under OP-V major opcode
 ....
 {reg: [
   {bits: 7, name: 0x57, attr: 'OPMVX'},
-  {bits: 5, name: 'vd / rd', type: 7},
+  {bits: 5, name: 'vd / rd'},
   {bits: 3, name: 6},
-  {bits: 5, name: 'rs1', type: 4},
-  {bits: 5, name: 'vs2', type: 2},
+  {bits: 5, name: 'rs1'},
+  {bits: 5, name: 'vs2'},
   {bits: 1, name: 'vm'},
   {bits: 6, name: 'funct6'},
 ]}
diff --git a/src/images/wavedrom/vcfg-format.adoc b/src/images/wavedrom/vcfg-format.edn
index ac0353c..0219e6b 100644
--- a/src/images/wavedrom/vcfg-format.adoc
+++ b/src/images/wavedrom/vcfg-format.edn
@@ -12,10 +12,10 @@ Formats for Vector Configuration Instructions under OP-V major opcode
 ....
 {reg: [
   {bits: 7,  name: 0x57, attr: 'vsetvli'},
-  {bits: 5,  name: 'rd', type: 4},
+  {bits: 5,  name: 'rd'},
   {bits: 3,  name: 7},
-  {bits: 5,  name: 'rs1', type: 4},
-  {bits: 11, name: 'vtypei[10:0]', type: 5},
+  {bits: 5,  name: 'rs1'},
+  {bits: 11, name: 'vtypei[10:0]'},
   {bits: 1,  name: '0'},
 ]}
 ....
@@ -24,10 +24,10 @@ Formats for Vector Configuration Instructions under OP-V major opcode
 ....
 {reg: [
   {bits: 7,  name: 0x57, attr: 'vsetivli'},
-  {bits: 5,  name: 'rd', type: 4},
+  {bits: 5,  name: 'rd'},
   {bits: 3,  name: 7},
-  {bits: 5,  name: 'uimm[4:0]', type: 5},
-  {bits: 10, name: 'vtypei[9:0]', type: 5},
+  {bits: 5,  name: 'uimm[4:0]'},
+  {bits: 10, name: 'vtypei[9:0]'},
   {bits: 1, name: '1'},
   {bits: 1,  name: '1'},
 ]}
@@ -37,10 +37,10 @@ Formats for Vector Configuration Instructions under OP-V major opcode
 ....
 {reg: [
   {bits: 7,  name: 0x57, attr: 'vsetvl'},
-  {bits: 5,  name: 'rd', type: 4},
+  {bits: 5,  name: 'rd'},
   {bits: 3,  name: 7},
-  {bits: 5,  name: 'rs1', type: 4},
-  {bits: 5,  name: 'rs2', type: 4},
+  {bits: 5,  name: 'rs1'},
+  {bits: 5,  name: 'rs2'},
   {bits: 6,  name: 0x00},
   {bits: 1,  name: 1},
 ]}
diff --git a/src/images/wavedrom/vfrec7.adoc b/src/images/wavedrom/vfrec7.edn
index d33f44e..d33f44e 100644
--- a/src/images/wavedrom/vfrec7.adoc
+++ b/src/images/wavedrom/vfrec7.edn
diff --git a/src/images/wavedrom/vfrsqrt7.adoc b/src/images/wavedrom/vfrsqrt7.edn
index 8ebc621..8ebc621 100644
--- a/src/images/wavedrom/vfrsqrt7.adoc
+++ b/src/images/wavedrom/vfrsqrt7.edn
diff --git a/src/images/wavedrom/vmem-format.adoc b/src/images/wavedrom/vmem-format.edn
index f9b25ee..58cc6bf 100644
--- a/src/images/wavedrom/vmem-format.adoc
+++ b/src/images/wavedrom/vmem-format.edn
@@ -12,9 +12,9 @@ Format for Vector Load Instructions under LOAD-FP major opcode
 ....
 {reg: [
   {bits: 7, name: 0x7, attr: 'VL* unit-stride'},
-  {bits: 5, name: 'vd', attr: 'destination of load', type: 2},
+  {bits: 5, name: 'vd', attr: 'destination of load'},
   {bits: 3, name: 'width'},
-  {bits: 5, name: 'rs1', attr: 'base address', type: 4},
+  {bits: 5, name: 'rs1', attr: 'base address'},
   {bits: 5, name: 'lumop'},
   {bits: 1, name: 'vm'},
   {bits: 2, name: 'mop'},
@@ -27,10 +27,10 @@ Format for Vector Load Instructions under LOAD-FP major opcode
 ....
 {reg: [
   {bits: 7, name: 0x7, attr: 'VLS* strided'},
-  {bits: 5, name: 'vd', attr: 'destination of load', type: 2},
+  {bits: 5, name: 'vd', attr: 'destination of load'},
   {bits: 3, name: 'width'},
-  {bits: 5, name: 'rs1', attr: 'base address', type: 4},
-  {bits: 5, name: 'rs2', attr: 'stride', type: 4},
+  {bits: 5, name: 'rs1', attr: 'base address'},
+  {bits: 5, name: 'rs2', attr: 'stride'},
   {bits: 1, name: 'vm'},
   {bits: 2, name: 'mop'},
   {bits: 1, name: 'mew'},
@@ -42,10 +42,10 @@ Format for Vector Load Instructions under LOAD-FP major opcode
 ....
 {reg: [
   {bits: 7, name: 0x7, attr: 'VLX* indexed'},
-  {bits: 5, name: 'vd', attr: 'destination of load', type: 2},
+  {bits: 5, name: 'vd', attr: 'destination of load'},
   {bits: 3, name: 'width'},
-  {bits: 5, name: 'rs1', attr: 'base address', type: 4},
-  {bits: 5, name: 'vs2', attr: 'address offsets', type: 2},
+  {bits: 5, name: 'rs1', attr: 'base address'},
+  {bits: 5, name: 'vs2', attr: 'address offsets'},
   {bits: 1, name: 'vm'},
   {bits: 2, name: 'mop'},
   {bits: 1, name: 'mew'},
@@ -66,9 +66,9 @@ Format for Vector Store Instructions under STORE-FP major opcode
 ....
 {reg: [
   {bits: 7, name: 0x27, attr: 'VS* unit-stride'},
-  {bits: 5, name: 'vs3', attr: 'store data', type: 2},
+  {bits: 5, name: 'vs3', attr: 'store data'},
   {bits: 3, name: 'width'},
-  {bits: 5, name: 'rs1', attr: 'base address', type: 4},
+  {bits: 5, name: 'rs1', attr: 'base address'},
   {bits: 5, name: 'sumop'},
   {bits: 1, name: 'vm'},
   {bits: 2, name: 'mop'},
@@ -81,10 +81,10 @@ Format for Vector Store Instructions under STORE-FP major opcode
 ....
 {reg: [
   {bits: 7, name: 0x27, attr: 'VSS* strided'},
-  {bits: 5, name: 'vs3', attr: 'store data', type: 2},
+  {bits: 5, name: 'vs3', attr: 'store data'},
   {bits: 3, name: 'width'},
-  {bits: 5, name: 'rs1', attr: 'base address', type: 4},
-  {bits: 5, name: 'rs2', attr: 'stride', type: 4},
+  {bits: 5, name: 'rs1', attr: 'base address'},
+  {bits: 5, name: 'rs2', attr: 'stride'},
   {bits: 1, name: 'vm'},
   {bits: 2, name: 'mop'},
   {bits: 1, name: 'mew'},
@@ -96,10 +96,10 @@ Format for Vector Store Instructions under STORE-FP major opcode
 ....
 {reg: [
   {bits: 7, name: 0x27, attr: 'VSX* indexed'},
-  {bits: 5, name: 'vs3', attr: 'store data', type: 2},
+  {bits: 5, name: 'vs3', attr: 'store data'},
   {bits: 3, name: 'width'},
-  {bits: 5, name: 'rs1', attr: 'base address', type: 4},
-  {bits: 5, name: 'vs2', attr: 'address offsets', type: 2},
+  {bits: 5, name: 'rs1', attr: 'base address'},
+  {bits: 5, name: 'vs2', attr: 'address offsets'},
   {bits: 1, name: 'vm'},
   {bits: 2, name: 'mop'},
   {bits: 1, name: 'mew'},
diff --git a/src/images/wavedrom/vtype-format.adoc b/src/images/wavedrom/vtype-format.edn
index 9e6ab34..9e6ab34 100644
--- a/src/images/wavedrom/vtype-format.adoc
+++ b/src/images/wavedrom/vtype-format.edn
diff --git a/src/images/wavedrom/wfi.adoc b/src/images/wavedrom/wfi.adoc
deleted file mode 100644
index 4447b9f..0000000
--- a/src/images/wavedrom/wfi.adoc
+++ /dev/null
@@ -1,13 +0,0 @@
-//
-
-[wavedrom, ,svg]
-
-....
-{reg: [
-  {bits: 7, name: 'opcode', type: 8, attr: ['7','SYSTEM'],},
-  {bits: 5, name: 'rd', type: 2, attr: ['5','0'],},
-  {bits: 3, name: 'funct3', type: 8, attr: ['3','PRIV'],},
-  {bits: 5, name: 'rs1', type: 4, attr: ['5','0'],},
-  {bits: 12, name: 'funct12', type: 8, attr: ['12','WFI',]},
-], config: {bits: 32}}
-....
-\ No newline at end of file
diff --git a/src/images/wavedrom/wfi.edn b/src/images/wavedrom/wfi.edn
new file mode 100644
index 0000000..870e2a1
--- /dev/null
+++ b/src/images/wavedrom/wfi.edn
@@ -0,0 +1,13 @@
+//
+
+[wavedrom, ,svg]
+
+....
+{reg: [
+  {bits: 7, name: 'opcode', attr: ['7','SYSTEM'],},
+  {bits: 5, name: 'rd', attr: ['5','0'],},
+  {bits: 3, name: 'funct3', attr: ['3','PRIV'],},
+  {bits: 5, name: 'rs1', attr: ['5','0'],},
+  {bits: 12, name: 'funct12', attr: ['12','WFI',]},
+], config: {bits: 32}} 
+....
+\ No newline at end of file
diff --git a/src/images/wavedrom/zifencei-fetch.adoc b/src/images/wavedrom/zifencei-fetch.adoc
deleted file mode 100644
index 42e0d6f..0000000
--- a/src/images/wavedrom/zifencei-fetch.adoc
+++ /dev/null
@@ -1,12 +0,0 @@
-//# 3 "Zifencei" Instruction-Fetch Fence, Version 2.0
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7,  name: 'opcode',    attr: 'MISC-MEM', type: 8},
-  {bits: 5,  name: 'rd',    attr: 0},
-  {bits: 3,  name: 'funct3', attr: 'FENCE.I', type: 8},
-  {bits: 5,  name: 'rs1',   attr: 0},
-  {bits: 12, name: 'func12', attr: 0},
-]}
-....
diff --git a/src/images/wavedrom/zifencei-ff.adoc b/src/images/wavedrom/zifencei-ff.adoc
deleted file mode 100644
index 5ccfae0..0000000
--- a/src/images/wavedrom/zifencei-ff.adoc
+++ /dev/null
@@ -1,12 +0,0 @@
-//# 3 "Zifencei" Instruction-Fetch Fence, Version 2.0
-
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits: 7,  name: 'opcode',    attr: ['7', 'MISC-MEM'], type: 8},
-  {bits: 5,  name: 'rd',    attr: ['5', '0'], type: 2},
-  {bits: 3,  name: 'funct3', attr: ['3', 'FENCE.I'], type: 8},
-  {bits: 5,  name: 'rs1',   attr: ['5', '0'], type: 4},
-  {bits: 12, name: 'funct12', attr: ['12', '0'], type: 8},
-]}
-....
diff --git a/src/images/wavedrom/zifencei-ff.edn b/src/images/wavedrom/zifencei-ff.edn
new file mode 100644
index 0000000..24cf87b
--- /dev/null
+++ b/src/images/wavedrom/zifencei-ff.edn
@@ -0,0 +1,12 @@
+//# 3 "Zifencei" Instruction-Fetch Fence, Version 2.0
+
+[wavedrom, ,svg]
+....
+{reg: [
+  {bits: 7,  name: 'opcode',    attr: ['7', 'MISC-MEM']},
+  {bits: 5,  name: 'rd',    attr: ['5', '0']},
+  {bits: 3,  name: 'funct3', attr: ['3', 'FENCE.I']},
+  {bits: 5,  name: 'rs1',   attr: ['5', '0']},
+  {bits: 12, name: 'funct12', attr: ['12', '0']},
+]}
+....
diff --git a/src/images/wavedrom/zihintpause-hint.adoc b/src/images/wavedrom/zihintpause-hint.edn
index 4c4a2ed..34c73a7 100644
--- a/src/images/wavedrom/zihintpause-hint.adoc
+++ b/src/images/wavedrom/zihintpause-hint.edn
@@ -3,9 +3,9 @@
 [wavedrom, ,svg]
 ....
 {reg: [
-  {bits: 7,  name: 'opcode',    attr: 'MISC-MEM', type: 8},
+  {bits: 7,  name: 'opcode',    attr: 'MISC-MEM'},
   {bits: 5,  name: 'rd', attr: 0},
-  {bits: 3,  name: 'funct3', attr: 'PAUSE', type: 8},
+  {bits: 3,  name: 'funct3', attr: 'PAUSE'},
   {bits: 5,  name: 'rs1', attr: 0},
   {bits: 1,  name: 'SW', attr: 0},
   {bits: 1,  name: 'SR', attr: 0},
diff --git a/src/intro.adoc b/src/intro.adoc
index 6fc871b..9b86442 100644
--- a/src/intro.adoc
+++ b/src/intro.adoc
@@ -33,7 +33,7 @@ efficiency.
 * An ISA that simplifies experiments with new privileged architecture
 designs.
 
-[TIP]
+[NOTE]
 ====
 Commentary on our design decisions is formatted as in this paragraph.
 This non-normative text can be skipped if the reader is only interested
@@ -64,7 +64,7 @@ volume provides the design of the first ("classic") privileged
 architecture. The manuals use IEC 80000-13:2008 conventions, with a byte
 of 8 bits.
 
-[TIP]
+[NOTE]
 ====
 In the unprivileged ISA design, we tried to remove any dependence on
 particular microarchitectural features, such as cache line size, or on
@@ -144,7 +144,7 @@ environments for guest operating systems.
 harts on an underlying x86 system, and which can provide either a
 user-level or a supervisor-level execution environment.
 
-[TIP]
+[NOTE]
 ====
 A bare hardware platform can be considered to define an EEI, where the
 accessible harts, memory, and other devices populate the environment,
@@ -176,7 +176,7 @@ constitute forward progress:
 * Any other event defined by an extension to constitute forward
 progress.
 
-[TIP]
+[NOTE]
 ====
 The term hart was introduced in the work on Lithe cite:[lithe-pan-hotpar09] and cite:[lithe-pan-pldi10] to provide a term to
 represent an abstract execution resource as opposed to a software thread
@@ -221,16 +221,16 @@ integer variants, RV32I and RV64I, described in
 <<rv32>> and <<rv64>>, which provide 32-bit
 or 64-bit address spaces respectively. We use the term XLEN to refer to
 the width of an integer register in bits (either 32 or 64).
-<<rv32e, Chapter 6>> describes the RV32E and RV64E subset variants of the
+<<rv32e>> describes the RV32E and RV64E subset variants of the
 RV32I or RV64I base instruction sets respectively, which have been added to support small
 microcontrollers, and which have half the number of integer registers.
-<<rv128, Chapter 8>> sketches a future RV128I variant of the
+<<rv128>> sketches a future RV128I variant of the
 base integer instruction set supporting a flat 128-bit address space
 (XLEN=128). The base integer instruction sets use a two's-complement
 representation for signed integer values.
 
 
-[TIP]
+[NOTE]
 ====
 Although 64-bit address spaces are a requirement for larger systems, we
 believe 32-bit address spaces will remain adequate for many embedded and
@@ -382,7 +382,7 @@ harts may be entirely the same, or entirely different, or may be partly
 different but sharing some subset of resources, mapped into the same or
 different address ranges.
 
-[TIP]
+[NOTE]
 ====
 For a purely "bare metal" environment, all harts may see an identical
 address space, accessed entirely by physical addresses. However, when
@@ -552,7 +552,7 @@ instructions. These instructions are considered to be of minimal length:
 bits. The encoding with bits [ILEN-1:0] all ones is also illegal; this
 instruction is considered to be ILEN bits long.
 
-[TIP]
+[NOTE]
 ====
 We consider it a feature that any length of instruction containing all
 zero bits is not legal, as this quickly traps erroneous jumps into
@@ -587,7 +587,7 @@ instruction specification.
 (((bi-endian)))
 (((endian, bi-)))
 
-[TIP]
+[NOTE]
 ====
 We originally chose little-endian byte ordering for the RISC-V memory
 system because little-endian systems are currently dominant commercially
diff --git a/src/m-st-ext.adoc b/src/m-st-ext.adoc
index fc08be2..1c036cb 100644
--- a/src/m-st-ext.adoc
+++ b/src/m-st-ext.adoc
@@ -5,7 +5,7 @@ This chapter describes the standard integer multiplication and division
 instruction extension, which is named "M" and contains instructions
 that multiply or divide values held in two integer registers.
 
-[TIP]
+[NOTE]
 ====
 We separate integer multiply and divide out from the base to simplify
 low-end implementations, or for applications where integer multiply and
@@ -15,7 +15,7 @@ accelerators.
 
 === Multiplication Operations
 
-include::images/wavedrom/m-st-ext-for-int-mult.adoc[]
+include::images/wavedrom/m-st-ext-for-int-mult.edn[]
 [[m-st-ext-for-int-mult]]
 //.Multiplication operation instructions
 (((MUL, MULH)))
@@ -52,7 +52,7 @@ to shift both arguments left by 32 bits, then use MULH[[S]U].
 
 === Division Operations
 
-include::images/wavedrom/division-op.adoc[]
+include::images/wavedrom/division-op.edn[]
 [[division-op]]
 //.Division operation instructions
 (((MUL, DIV)))
@@ -113,7 +113,7 @@ latexmath:[$-1$] |latexmath:[$2^{L}-1$] +
 //|Overflow (signed only) |latexmath:[$-2^{L-1}$] |latexmath:[$-1$] |– |– |latexmath:[$-2^{L-1}$] |0
 //|===
 
-[TIP]
+[NOTE]
 ====
 We considered raising exceptions on integer divide by zero, with these
 exceptions causing a trap in most execution environments. However, this
diff --git a/src/machine.adoc b/src/machine.adoc
index 8358279..2cb8454 100644
--- a/src/machine.adoc
+++ b/src/machine.adoc
@@ -368,93 +368,18 @@ S-level ISA.
 
 [[mstatusreg-rv32]]
 .Machine-mode status (`mstatus`) register for RV32
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits:  1, name: 'WPRI'},
-  {bits:  1, name: 'SIE'},
-  {bits:  1, name: 'WPRI'},
-  {bits:  1, name: 'MIE'},
-  {bits:  1, name: 'WPRI'},
-  {bits:  1, name: 'SPIE'},
-  {bits:  1, name: 'UBE'},
-  {bits:  1, name: 'MPIE'},
-  {bits:  1, name: 'SPP'},
-  {bits:  2, name: 'VS[1:0]'},
-  {bits:  2, name: 'MPP[1:0]'},
-  {bits:  2, name: 'FS[1:0]'},
-  {bits:  2, name: 'XS[1:0]'},
-  {bits:  1, name: 'MPRV'},
-  {bits:  1, name: 'SUM'},
-  {bits:  1, name: 'MXR'},
-  {bits:  1, name: 'TVM'},
-  {bits:  1, name: 'TW'},
-  {bits:  1, name: 'TSR'},
-  {bits:  1, name: 'SPELP'},
-  {bits:  7, name: 'WPRI'},
-  {bits:  1, name: 'SD'},
-], config:{lanes: 2, hspace:1024}}
-....
+include::images/wavedrom/mstatusreg-rv321.edn[]
 
 [[mstatusreg]]
 .Machine-mode status (`mstatus`) register for RV64
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits:  1, name: 'WPRI'},
-  {bits:  1, name: 'SIE'},
-  {bits:  1, name: 'WPRI'},
-  {bits:  1, name: 'MIE'},
-  {bits:  1, name: 'WPRI'},
-  {bits:  1, name: 'SPIE'},
-  {bits:  1, name: 'UBE'},
-  {bits:  1, name: 'MPIE'},
-  {bits:  1, name: 'SPP'},
-  {bits:  2, name: 'VS[1:0]'},
-  {bits:  2, name: 'MPP[1:0]'},
-  {bits:  2, name: 'FS[1:0]'},
-  {bits:  2, name: 'XS[1:0]'},
-  {bits:  1, name: 'MPRV'},
-  {bits:  1, name: 'SUM'},
-  {bits:  1, name: 'MXR'},
-  {bits:  1, name: 'TVM'},
-  {bits:  1, name: 'TW'},
-  {bits:  1, name: 'TSR'},
-  {bits:  1, name: 'SPELP'},
-  {bits:  8, name: 'WPRI'},
-  {bits:  2, name: 'UXL[1:0]'},
-  {bits:  2, name: 'SXL[1:0]'},
-  {bits:  1, name: 'SBE'},
-  {bits:  1, name: 'MBE'},
-  {bits:  1, name: 'GVA'},
-  {bits:  1, name: 'MPV'},
-  {bits:  1, name: 'WPRI'},
-  {bits:  1, name: 'MPELP'},
-  {bits:  1, name: 'MDT'},
-  {bits: 20, name: 'WPRI'},
-  {bits:  1, name: 'SD'},
-], config:{lanes: 4, hspace:1024}}
-....
+include::images/wavedrom/mstatusreg.edn[]
 
 For RV32 only, `mstatush` is a 32-bit read/write register formatted as
 shown in <<mstatushreg>>. Bits 30:4 of `mstatush` generally contain the same fields found in bits 62:36 of `mstatus` for RV64. Fields SD, SXL, and UXL do not exist in `mstatush`.
 
 [[mstatushreg]]
 .Additional machine-mode status (`mstatush`) register  for RV32.
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits:  4, name: 'WPRI'},
-  {bits:  1, name: 'SBE'},
-  {bits:  1, name: 'MBE'},
-  {bits:  1, name: 'GVA'},
-  {bits:  1, name: 'MPV'},
-  {bits:  1, name: 'WPRI'},
-  {bits:  1, name: 'MPELP'},
-  {bits:  1, name: 'MDT'},
-  {bits: 21, name: 'WPRI'},
-], config:{lanes: 2, hspace:1024}}
-....
+include::images/wavedrom/mstatushreg.edn[]
 
 [[privstack]]
 ===== Privilege and Global Interrupt-Enable Stack in `mstatus` register
@@ -573,9 +498,11 @@ by the same write (For RV32, the `MDT` bit is in `mstatush` and the `MIE` bit in
 
 When a trap is to be taken into M-mode, if the `MDT` bit is currently 0, it is
 then set to 1, and the trap is delivered as expected. However, if `MDT` is
-already set to 1, then this is an _unexpected trap_. Additionally, when the
-Smrnmi extension is implemented, a trap that occurs when executing in M-mode
-with the `mnstatus.NMIE` set to 0 is an _unexpected trap_.
+already set to 1, then this is an _unexpected trap_. When the Smrnmi extension
+is implemented, a trap caused by an RNMI is not considered an _unexpected trap_
+irrespective of the state of the `MDT` bit. A trap caused by an RNMI does not
+set the `MDT` bit. However, a trap that occurs when executing in M-mode with
+`mnstatus.NMIE` set to 0 is an _unexpected trap_.
 
 In the event of a _unexpected trap_, the handling is as follows:
 
@@ -612,6 +539,10 @@ The `MRET` and `SRET` instructions, when executed in M-mode, set the `MDT` bit
 to 0. If the new privilege mode is U, VS, or VU, then `sstatus.SDT` is also set
 to 0. Additionally, if it is VU, then `vsstatus.SDT` is also set to 0.
 
+The `MNRET` instruction, provided by the Smrnmi extension, sets the `MDT` bit to
+0 if the new privilege mode is not M. If it is U, VS, or VU, then `sstatus.SDT` is
+also set to 0. Additionally, if it is VU, then `vsstatus.SDT` is also set to 0.
+
 [[xlen-control]]
 ===== Base ISA Control in `mstatus` Register
 
@@ -656,6 +587,21 @@ always be a software bug, but machine operation is well-defined even in
 this case.
 ====
 
+Some HINT instructions are encoded as integer computational instructions that
+overwrite their destination register with its current value, e.g.,
+`c.addi x8, 0`.
+When such a HINT is executed with XLEN < MXLEN and bits MXLEN..XLEN of the
+destination register not all equal to bit XLEN-1, it is implementation-defined
+whether bits MXLEN..XLEN of the destination register are unchanged or are
+overwritten with copies of bit XLEN-1.
+
+NOTE: This definition allows implementations to elide register writeback for
+some HINTs, while allowing them to execute other HINTs in the same manner as
+other integer computational instructions.
+The implementation choice is observable only by privilege modes with an XLEN
+setting greater than the current XLEN; it is invisible to the current
+privilege mode.
+
 ===== Memory Privilege in `mstatus` Register
 
 The MPRV (Modify PRiVilege) bit modifies the _effective privilege mode_,
@@ -1629,9 +1575,9 @@ counters, the counters can be directly exposed to lower privilege modes.
 The `cycle`, `instret`, and `hpmcountern` CSRs are read-only shadows of
 `mcycle`, `minstret`, and `mhpmcounter n`, respectively. The `time` CSR
 is a read-only shadow of the memory-mapped `mtime` register.
-Analogously, on RV32I the `cycleh`, `instreth` and `hpmcounternh` CSRs
+Analogously, when XLEN=32, the `cycleh`, `instreth` and `hpmcounternh` CSRs
 are read-only shadows of `mcycleh`, `minstreth` and `mhpmcounternh`,
-respectively. On RV32I the `timeh` CSR is a read-only shadow of the
+respectively. When XLEN=32, the `timeh` CSR is a read-only shadow of the
 upper 32 bits of the memory-mapped `mtime` register, while `time`
 shadows only the lower 32 bits of `mtime`.
 
@@ -1867,6 +1813,9 @@ _Designated for platform use_
 0 +
 0 +
 0 +
+0 +
+0 +
+0 +
 0
 |0 +
 1 +
@@ -2152,28 +2101,10 @@ as shown in <<menvcfgreg>>, that controls
 certain characteristics of the execution environment for modes less
 privileged than M.
 
-[#menvcfgreg]
+[[menvcfgreg]]
 .Machine environment configuration (`menvcfg`) register.
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits:  1, name: 'FIOM'},
-  {bits:  1, name: 'WPRI'},
-  {bits:  1, name: 'LPE'},
-  {bits:  1, name: 'SSE'},
-  {bits:  2, name: 'CBIE'},
-  {bits:  1, name: 'CBCFE'},
-  {bits:  1, name: 'CBZE'},
-  {bits: 24, name: 'WPRI'},
-  {bits:  2, name: 'PMM'},
-  {bits: 25, name: 'WPRI'},
-  {bits:  1, name: 'DTE'},
-  {bits:  1, name: 'CDE'},
-  {bits:  1, name: 'ADUE'},
-  {bits:  1, name: 'PBMTE'},
-  {bits:  1, name: 'STCE'},
-], config:{lanes: 4, hspace:1024}}
-....
+include::images/wavedrom/menvcfgreg.edn[]
+
 
 If bit FIOM (Fence of I/O implies Memory) is set to one in `menvcfg`,
 FENCE instructions executed in modes less privileged than M are modified
@@ -2275,9 +2206,11 @@ the following rules apply to privilege modes that are less than M:
 * 32-bit Zicfiss instructions will revert to their behavior as defined by Zimop.
 * 16-bit Zicfiss instructions will revert to their behavior as defined by Zcmop.
 * The `pte.xwr=010b` encoding in VS/S-stage page tables becomes reserved.
-* The `henvcfg.SSE` and `senvcfg.SSE` fields will read as zero and are read-only.
 * `SSAMOSWAP.W/D` raises an illegal-instruction exception.
 
+When `menvcfg.SSE` is 0, the `henvcfg.SSE` and `senvcfg.SSE` fields are
+read-only zero.
+
 The Ssdbltrp extension adds the double-trap-enable (`DTE`) field in `menvcfg`.
 When `menvcfg.DTE` is zero, the implementation behaves as though Ssdbltrp is not
 implemented. When Ssdbltrp is not implemented `sstatus.SDT`, `vsstatus.SDT`, and
@@ -2297,19 +2230,7 @@ shown in <<mseccfg>>, that controls security features.
 
 [[mseccfg]]
 .Machine security configuration (`mseccfg`) register.
-[wavedrom, ,svg]
-....
-{reg: [
-  {bits:  1, name: 'MML'},
-  {bits:  1, name: 'MMWP'},
-  {bits:  1, name: 'RLB'},
-  {bits:  5, name: 'WPRI'},
-  {bits:  1, name: 'USEED'},
-  {bits:  1, name: 'SSEED'},
-  {bits:  1, name: 'MLPE'},
-  {bits: 53, name: 'WPRI'},
-], config:{lanes: 4, hspace:1024}}
-....
+include::images/wavedrom/mseccfg.edn[]
 
 The definitions of the SSEED and USEED fields will be furnished by the
 forthcoming entropy-source extension, Zkr. Their allocations within
@@ -2385,8 +2306,9 @@ Simple fixed-frequency systems can use a single clock for both cycle
 counting and wall-clock time.
 ====
 
-Writes to `mtime` and `mtimecmp` are guaranteed to be reflected in MTIP
-eventually, but not necessarily immediately.
+If the result of the comparison between `mtime` and `mtimecmp` changes, it is
+guaranteed to be reflected in MTIP eventually, but not necessarily
+immediately.
 
 [NOTE]
 ====
@@ -2417,13 +2339,19 @@ For RV64, naturally aligned 64-bit memory accesses to the `mtime` and
 ....
 
 
+The `time` CSR is a read-only shadow of the memory-mapped `mtime` register.
+When XLEN=32, the `timeh` CSR is a read-only shadow of the upper 32 bits of the
+memory-mapped `mtime` register, while `time` shadows only the lower 32 bits of
+`mtime`.
+When `mtime` changes, it is guaranteed to be reflected in `time` and `timeh`
+eventually, but not necessarily immediately.
 
 
 === Machine-Mode Privileged Instructions
 
 ==== Environment Call and Breakpoint
 
-include::images/wavedrom/mm-env-call.adoc[]
+include::images/wavedrom/mm-env-call.edn[]
 
 The ECALL instruction is used to make a request to the supporting
 execution environment. When executed in U-mode, S-mode, or M-mode, it
@@ -2463,7 +2391,7 @@ not increment the `minstret` CSR.
 Instructions to return from trap are encoded under the PRIV minor
 opcode.
 
-include::images/wavedrom/trap-return.adoc[]
+include::images/wavedrom/trap-return.edn[]
 
 To return after handling a trap, there are separate trap return
 instructions per privilege level, MRET and SRET. MRET is always
@@ -2500,7 +2428,7 @@ privileged modes, and optionally available to U-mode. This instruction
 may raise an illegal-instruction exception when TW=1 in `mstatus`, as
 described in <<virt-control>>.
 
-include::images/wavedrom/wfi.adoc[]
+include::images/wavedrom/wfi.edn[]
 
 If an enabled interrupt is present or later becomes present while the
 hart is stalled, the interrupt trap will be taken on the following
@@ -2594,7 +2522,9 @@ the platform mandates a different reset value for some PMP registers’ A
 and L fields. If the hypervisor extension is implemented, the
 `hgatp`.MODE and `vsatp`.MODE fields are reset to 0. If the Smrnmi
 extension is implemented, the `mnstatus`.NMIE field is reset to 0. No
- *WARL* field contains an illegal value. All other hart state is UNSPECIFIED.
+ *WARL* field contains an illegal value. If the Zicfilp extension is
+implemented, the `mseccfg`.MLPE field is reset to 0. All other hart
+state is UNSPECIFIED.
 
 The `mcause` values after reset have implementation-specific
 interpretation, but the value 0 should be returned on implementations
diff --git a/src/mm-formal.adoc b/src/mm-formal.adoc
index 9f2c942..58e35ee 100644
--- a/src/mm-formal.adoc
+++ b/src/mm-formal.adoc
@@ -597,7 +597,7 @@ continue executing.
 Transitions specific to `sc` instructions:
 
 [disc]
-* <<early_sc_fail, Early sc fail>>: This causes the `sc` to fail, either a spontaneous fail or becauset is not paired with a program-order-previous `lr`.
+* <<early_sc_fail, Early sc fail>>: This causes the `sc` to fail, either a spontaneous fail or because it is not paired with a program-order-previous `lr`.
 
 * <<paired_sc, Paired sc>>: This transition indicates the `sc` is paired with an `lr` and might
 succeed.
@@ -1049,10 +1049,10 @@ load is acquire-RCsc.
 ===== Satisfy memory load operation from memory
 
 For an instruction instance latexmath:[$i$] of a non-AMO load
-instruction or an AMO instruction in the context of the <<do_amo, Saitsfy, commit and propagate operations of an AMO>> transition,
+instruction or an AMO instruction in the context of the <<do_amo, Satisfy, commit and propagate operations of an AMO>> transition,
 any memory load operation latexmath:[$mlo$] in
 latexmath:[$i.\textit{mem\_loads}$] that has unsatisfied slices, can be
-satisfied from memory if all the conditions of <sat_by_forwarding, Saitsfy memory load operation by forwarding from unpropagated stores>> are satisfied. Action:
+satisfied from memory if all the conditions of <sat_by_forwarding, Satisfy memory load operation by forwarding from unpropagated stores>> are satisfied. Action:
 let latexmath:[$msoss$] be the memory store operation slices from memory
 covering the unsatisfied slices of latexmath:[$mlo$], and apply the
 action of <<do_amo, Satisfy memory operation by forwarding from unpropagates stores>>.
@@ -1259,7 +1259,7 @@ Plain(_store_continuation(false)_).
 For efficiency, the `rmem` tool allows this transition only when it is
 not possible to take the <<commit_sc, Commit and propagate store operation of an sc>> transition. This does not affect the set of
 allowed final states, but when explored interactively, if the `sc`
-should fail one should use the <<early_sc_fail, Eaarly sc fail>> transition instead of waiting for this transition.
+should fail one should use the <<early_sc_fail, Early sc fail>> transition instead of waiting for this transition.
 ====
 [[complete_stores]]
 ===== Complete store operations
diff --git a/src/naming.adoc b/src/naming.adoc
index 0aaa177..09c728b 100644
--- a/src/naming.adoc
+++ b/src/naming.adoc
@@ -88,7 +88,7 @@ closely related alphabetical extension category, IMAFDQLCBKJTPVH. For the
 indicates the extension is related to the "F" standard extension. If
 multiple "Z" extensions are named, they should be ordered first by
 category, then alphabetically within a category—for example,
-"Zicsr_Zifencei_Zam".
+"Zicsr_Zifencei_Ztso".
 
 All multi-letter extensions, including those with the "Z" prefix, must be
 separated from other multi-letter extensions by an underscore, e.g.,
@@ -115,7 +115,7 @@ with the letters "Sh".
 If multiple hypervisor-level extensions are listed, they should be ordered
 alphabetically.
 
-NOTE: Many augmentations to the hypervisor-level archtecture are more
+NOTE: Many augmentations to the hypervisor-level architecture are more
 naturally defined as supervisor-level extensions, following the scheme
 described in the previous section.
 The "Sh" prefix is used by the few hypervisor-level extensions that have no
diff --git a/src/priv-cfi.adoc b/src/priv-cfi.adoc
index 082ceb7..088a593 100644
--- a/src/priv-cfi.adoc
+++ b/src/priv-cfi.adoc
@@ -13,7 +13,7 @@ details on these CFI capabilities and the associated Unprivileged ISA.
 
 This section specifies the Privileged ISA for the Zicfilp extension.
 
-[[FCIFIACT]]
+[[FCFIACT]]
 ==== Landing-Pad-Enabled (LPE) State
 
 The term `xLPE` is used to determine if forward-edge CFI using landing pads
@@ -88,23 +88,19 @@ When a trap is taken into privilege mode `x`, the `__x__PELP` is set to `ELP`
 and `ELP` is set to `NO_LP_EXPECTED`.
 
 An `MRET` or `SRET` instruction is used to return from a trap in M-mode or
-S-mode, respectively.  When executing an `__x__RET` instruction, if `__x__PP`
-holds the value `y`, then `ELP` is set to the value of `__x__PELP` if `__y__LPE`
-is 1; otherwise, it is set to `NO_LP_EXPECTED`; `__x__PELP` is set to
-`NO_LP_EXPECTED`.
+S-mode, respectively.  When executing an `__x__RET` instruction, if the new
+privilege mode is `y`, then `ELP` is set to the value of `__x__PELP` if
+`__y__LPE` (see <<FCFIACT>>) is 1; otherwise, it is set to `NO_LP_EXPECTED`;
+`__x__PELP` is set to `NO_LP_EXPECTED`.
 
 Upon entry into Debug Mode, the `pelp` bit in `dcsr` is updated with the `ELP`
 at the privilege level the hart was previously in, and the `ELP` is set to
-`NO_LP_EXPECTED`. When a hart resumes from Debug Mode, if `dcsr.prv` holds the
-value `y`, then `ELP` is set to the value of `pelp` if `__y__LPE` is 1;
-otherwise, it is set to `NO_LP_EXPECTED`.
+`NO_LP_EXPECTED`. When a hart resumes from Debug Mode, if the new privilege mode
+is `y`, then `ELP` is set to the value of `pelp` if `__y__LPE` (see <<FCFIACT>>)
+is 1; otherwise, it is set to `NO_LP_EXPECTED`.
 
-When the Smrnmi extension is implemented, a `MNPELP` field (bit 9)
-is provided in the `mnstatus` CSR to hold the previous `ELP` state on a trap to
-the RNMI handler. When a RNMI trap is delivered, the `MNPELP` is set to `ELP`
-and `ELP` set to `NO_LP_EXPECTED`. Upon a `MNRET`, if the `mnstatus.MNPP` holds
-the value `y`, then `ELP` is set to the value of `MNPELP` if `yLPE` is 1;
-otherwise, it is set to `NO_LP_EXPECTED`.
+See also <<rnmi>> for semantics added to the RNMI trap and the MNRET instruction
+when this extension is implemented.
 
 [NOTE]
 ====
@@ -271,17 +267,6 @@ of as "store/AMO/SS" exceptions, indicating that the trapping instruction is
 either a store, an AMO, or a shadow stack instruction.
 ====
 
-[NOTE]
-====
-The H (hypervisor) extension specifies that when a guest-page fault is caused by
-an implicit memory access of VS-stage address translation, the reported
-exception is either a load or store/AMO guest-page fault based not on the
-original instruction type but rather on whether the memory access attempted for
-VS-stage translation was a read or a write of memory. VS-stage address
-translation can thus cause a shadow stack instruction to raise a load
-guest-page-fault exception.
-====
-
 Shadow stack instructions are restricted to accessing shadow stack
 (`pte.xwr=010b`) pages. Should a shadow stack instruction access a page that is
 not designated as a shadow stack page and is not marked as read-only
diff --git a/src/priv-preface.adoc b/src/priv-preface.adoc
index 25712c5..092b45d 100644
--- a/src/priv-preface.adoc
+++ b/src/priv-preface.adoc
@@ -1,10 +1,10 @@
 [colophon]
 = Preface
 
-[.big]*_Preface to Version 20240528_*
+[.big]*_Preface to Version 20240829_*
 
 This document describes the RISC-V privileged architecture. This
-release, version 20240528, contains the following versions of the RISC-V ISA
+release, version 20240829, contains the following versions of the RISC-V ISA
 modules:
 
 [%autowidth,float="center",align="center",cols="^,<,^",options="header",]
@@ -14,10 +14,10 @@ modules:
 *Smstateen Extension* +
 *Smcsrind/Sscsrind Extension* +
 *Smepmp* +
-**Smcntrpmf* +
+*Smcntrpmf* +
 *Smrnmi Extension* +
 *Smcdeleg* +
-_Smdbltrp_ +
+*Smdbltrp* +
 _Supervisor ISA_ +
 *Svade Extension* +
 *Svnapot Extension* + 
@@ -26,9 +26,10 @@ _Supervisor ISA_ +
 *Svadu Extension* +
 *Sstc* +
 *Sscofpmf* +
-_Ssdbltrp_ +
+*Ssdbltrp* +
 *Hypervisor ISA* +
-_Shlcofideleg_
+_Shlcofideleg_ +
+*Svvptc*
 
 |_1.13_ +
 *1.0* +
@@ -37,7 +38,7 @@ _Shlcofideleg_
 *1.0* +
 *1.0* +
 *1.0* +
-_1.0_ +
+*1.0* +
 _1.13_ +
 *1.0* +
 *1.0* +
@@ -46,29 +47,31 @@ _1.13_ +
 *1.0* +
 *1.0* +
 *1.0* +
-_1.0_ +
 *1.0* +
-_0.1_
+*1.0* +
+_0.1_ +
+*1.0*
 
-|_Draft_ +
+|_Frozen_ +
 *Ratified* +
 *Ratified* +
 *Ratified* +
 *Ratified* +
 *Ratified* +
 *Ratified* +
-_Draft_ +
-_Draft_ +
 *Ratified* +
+_Frozen_ +
 *Ratified* +
 *Ratified* +
 *Ratified* +
 *Ratified* +
 *Ratified* +
 *Ratified* +
-_Draft_ +
 *Ratified* +
-_Draft_
+*Ratified* +
+*Ratified* +
+_Draft_ +
+*Ratified*
 |===
 
 The following changes have been made since version 1.12 of the Machine and
@@ -92,9 +95,10 @@ implemented.
 * Defined hardware error and software check exception codes.
 * Specified synchronization requirements when changing the PBMTE fields
 in `menvcfg` and `henvcfg`.
-* Exposed count-overflow interrups to VS-mode via the Shlcofideleg extension.
+* Exposed count-overflow interrupts to VS-mode via the Shlcofideleg extension.
+* Relaxed behavior of some HINTs when MXLEN > XLEN.
 
-Finally, the following clarifications and document improvments have been made
+Finally, the following clarifications and document improvements have been made
 since the last document release:
 
 * Transliterated the document from LaTeX into AsciiDoc.
@@ -112,6 +116,9 @@ be set to a nonzero value but sometimes not.
 * Clarified exception behavior of unimplemented or inaccessible CSRs.
 * Clarified that Svpbmt allows implementations to override additional PMAs.
 * Replaced the concept of vacant memory regions with inaccessible memory or I/O regions.
+* Clarified that timer and count-overflow interrupts' arrival in
+  interrupt-pending registers is not immediate.
+* Clarified that MXR affects only explicit memory accesses.
 
 [.big]*_Preface to Version 20211203_*
 
diff --git a/src/q-st-ext.adoc b/src/q-st-ext.adoc
index 3940ea7..1cb969f 100644
--- a/src/q-st-ext.adoc
+++ b/src/q-st-ext.adoc
@@ -17,7 +17,7 @@ value.
 New 128-bit variants of LOAD-FP and STORE-FP instructions are added,
 encoded with a new value for the funct3 width field.
 
-include::images/wavedrom/quad-ls.adoc[]
+include::images/wavedrom/quad-ls.edn[]
 [[quad-ls]]
 //.Quad-precision load and store
 
@@ -47,7 +47,7 @@ The quad-precision floating-point computational instructions are defined
 analogously to their double-precision counterparts, but operate on
 quad-precision operands and produce quad-precision results.
 
-include::images/wavedrom/quad-compute.adoc[]
+include::images/wavedrom/quad-compute.edn[]
 [[quad-compute]]
 //.Quad-precision computational
 
@@ -64,7 +64,7 @@ FCVT.WU.Q, FCVT.LU.Q, FCVT.Q.WU, and FCVT.Q.LU variants convert to or
 from unsigned integer values. FCVT.L[U].Q and FCVT.Q.L[U] are RV64-only
 instructions. Note FCVT.Q.L[U] always produces an exact result and is unaffected by rounding mode.
 
-include::images/wavedrom/quad-cnvrt-mv.adoc[]
+include::images/wavedrom/quad-cnvrt-mv.edn[]
 [[quad-cnvrt-mv]]
 //.Quad-precision convert and move
 
@@ -76,7 +76,7 @@ single-precision floating-point number, or vice-versa, respectively.
 FCVT.D.Q or FCVT.Q.D converts a quad-precision floating-point number to
 a double-precision floating-point number, or vice-versa, respectively.
 
-include::images/wavedrom/quad-cnvt-interchange.adoc[]
+include::images/wavedrom/quad-cnvt-interchange.edn[]
 [[quad-convrt-interchange]]
 //.Quad-precision convert and move interchangeably
 
@@ -84,7 +84,7 @@ Floating-point to floating-point sign-injection instructions, FSGNJ.Q,
 FSGNJN.Q, and FSGNJX.Q are defined analogously to the double-precision
 sign-injection instruction.
 
-include::images/wavedrom/quad-cnvrt-intch-xqqx.adoc[]
+include::images/wavedrom/quad-cnvrt-intch-xqqx.edn[]
 [[quad-cnvrt-intch-xqqx]]
 //.Quad-precision convert and move interchangeably XQ-QX
 
@@ -103,7 +103,7 @@ The quad-precision floating-point compare instructions are defined
 analogously to their double-precision counterparts, but operate on
 quad-precision operands.
 
-include::images/wavedrom/quad-float-compare.adoc[]
+include::images/wavedrom/quad-float-compare.edn[]
 [[quad-float-compare]]
 //.Quad-precision floatinf-point compare
 
@@ -113,7 +113,7 @@ The quad-precision floating-point classify instruction, FCLASS.Q, is
 defined analogously to its double-precision counterpart, but operates on
 quad-precision operands.
 
-include::images/wavedrom/quad-float-clssfy.adoc[]
+include::images/wavedrom/quad-float-clssfy.edn[]
 [[quad-float-clssfy]]
 //.Quad-precision floating point classify
 
diff --git a/src/riscv-privileged.adoc b/src/riscv-privileged.adoc
index afe0883..6a83c54 100644
--- a/src/riscv-privileged.adoc
+++ b/src/riscv-privileged.adoc
@@ -2,7 +2,7 @@
 = The RISC-V Instruction Set Manual: Volume II: Privileged Architecture
 include::../docs-resources/global-config.adoc[]
 :description: Volume II - Privileged Architecture
-:revnumber: 20240528
+:revnumber: 20240829
 //:revremark: Pre-release version
 //development: assume everything can change
 //stable: assume everything could change
diff --git a/src/riscv-unprivileged.adoc b/src/riscv-unprivileged.adoc
index a755403..b71d372 100644
--- a/src/riscv-unprivileged.adoc
+++ b/src/riscv-unprivileged.adoc
@@ -27,15 +27,16 @@ include::../docs-resources/global-config.adoc[]
 :example-caption: Example
 :listing-caption: Listing
 :sectnums:
+:sectnumlevels: 5
 :toc: left
-:toclevels: 5
+:toclevels: 5 
 :source-highlighter: pygments
 ifdef::backend-pdf[]
 :source-highlighter: rouge
 endif::[]
 :table-caption: Table
 :figure-caption: Figure
-:xrefstyle: short
+:xrefstyle: short 
 :chapter-refsig: Chapter
 :section-refsig: Section
 :appendix-refsig: Appendix
diff --git a/src/rnmi.adoc b/src/rnmi.adoc
index aef8e9d..8d58199 100644
--- a/src/rnmi.adoc
+++ b/src/rnmi.adoc
@@ -1,11 +1,5 @@
 [[rnmi]]
-== "Smrnmi" Extension for Resumable Non-Maskable Interrupts, Version 0.5
-
-[WARNING]
-====
-*Warning! This frozen specification may change before being accepted as
-standard by RISC-V International.*
-====
+== "Smrnmi" Extension for Resumable Non-Maskable Interrupts, Version 1.0
 
 The base machine-level architecture supports only unresumable
 non-maskable interrupts (UNMIs), where the NMI jumps to a handler in
@@ -144,8 +138,8 @@ MNRET is an M-mode-only instruction that uses the values in `mnepc` and
 `mnstatus` to return to the program counter, privilege mode, and
 virtualization mode of the interrupted context. This instruction also
 sets `mnstatus`.NMIE.  If MNRET changes the privilege mode to a mode less privileged than M, it also sets `mstatus`.MPRV to 0.
-If the Zicfilp extension is implemented, then if `mnstatus`.MNPP holds the
-value __y__, MNRET sets `ELP` to the logical AND of __y__LPE and `mnstatus`.MNPELP.
+If the Zicfilp extension is implemented, then if the new privileged mode
+is __y__, MNRET sets `ELP` to the logical AND of __y__LPE (see <<FCFIACT>>) and `mnstatus`.MNPELP.
 
 === RNMI Operation
 
diff --git a/src/rv128.adoc b/src/rv128.adoc
index 62af109..9098dcb 100644
--- a/src/rv128.adoc
+++ b/src/rv128.adoc
@@ -11,7 +11,7 @@ flat 128-bit address space. The variant is a straightforward
 extrapolation of the existing RV32I and RV64I designs.
 (((RV128, design)))
 
-[TIP]
+[NOTE]
 ====
 The primary reason to extend integer register width is to support larger
 address spaces. It is not clear when a flat address space larger than 64
diff --git a/src/rv32.adoc b/src/rv32.adoc
index 9714df4..86f636e 100644
--- a/src/rv32.adoc
+++ b/src/rv32.adoc
@@ -3,7 +3,7 @@
 
 This chapter describes the RV32I base integer instruction set.
 
-[TIP]
+[NOTE]
 ====
 RV32I was designed to be sufficient to form a compiler target and to
 support modern operating system environments. The ISA was also designed
@@ -174,7 +174,7 @@ bits in the instruction and have been allocated to reduce hardware
 complexity. In particular, the sign bit for all immediates is always in
 bit 31 of the instruction to speed sign-extension circuitry.
 
-include::images/wavedrom/instruction_formats.adoc[]
+include::images/wavedrom/instruction-formats.edn[]
 [[base_instr,Base instruction formats]]
 RISC-V base instruction formats. Each immediate subfield is labeled with the bit position (imm[x]) in the immediate value being produced, rather than the bit position within the instruction's immediate field as is usually done.
 
@@ -201,7 +201,7 @@ to keep the ISA as simple as possible.
 There are a further two variants of the instruction formats (B/J) based
 on the handling of immediates, as shown in <<baseinstformatsimm>>.
 
-include::images/wavedrom/immediate_variants.adoc[]
+include::images/wavedrom/immediate-variants.edn[]
 [[baseinstformatsimm,Base instruction formats immediate variants.]]
 //.RISC-V base instruction formats showing immediate variants.
 
@@ -222,9 +222,19 @@ formats and with each other.
 <<immtypes>> shows the immediates produced by
 each of the base instruction formats, and is labeled to show which
 instruction bit (inst[_y_]) produces each bit of the immediate value.
+
 [[immtypes, Immediate types]]
-.Types of immediate produced by RISC-V instructions. 
-include::images/wavedrom/immediate.adoc[]
+include::images/wavedrom/i-immediate.edn[]
+
+include::images/wavedrom/s-immediate.edn[]
+
+include::images/wavedrom/b-immediate.edn[]
+
+include::images/wavedrom/u-immediate.edn[]
+
+.Types of immediate produced by RISC-V instructions.
+include::images/wavedrom/j-immediate.edn[]
+
 
 The fields are labeled with the instruction bits used to construct their value.  Sign extensions always uses inst[31].
 
@@ -258,7 +268,7 @@ destination is register _rd_ for both register-immediate and
 register-register instructions. No integer computational instructions
 cause arithmetic exceptions.
 
-[TIP]
+[NOTE]
 ====
 We did not include special instruction-set support for overflow checks
 on integer arithmetic operations in the base instruction set, as many
@@ -291,7 +301,7 @@ comparing the results of ADD and ADDW on the operands.
 
 ==== Integer Register-Immediate Instructions
 
-include::images/wavedrom/integer_computational.adoc[]
+include::images/wavedrom/integer-computational.edn[]
 //.Integer Computational Instructions
 
 ADDI adds the sign-extended 12-bit immediate to register _rs1_.
@@ -312,7 +322,7 @@ XOR on register _rs1_ and the sign-extended 12-bit immediate and place
 the result in _rd_. Note, XORI _rd, rs1, -1_ performs a bitwise logical
 inversion of register _rs1_ (assembler pseudoinstruction NOT _rd, rs_).
 
-include::images/wavedrom/int-comp-slli-srli-srai.adoc[]
+include::images/wavedrom/int-comp-slli-srli-srai.edn[]
 [[int-comp-slli-srli-srai]]
 //.Integer register-immediate, SLLI, SRLI, SRAI
 
@@ -324,7 +334,7 @@ shifted into the lower bits); SRLI is a logical right shift (zeros are
 shifted into the upper bits); and SRAI is an arithmetic right shift (the
 original sign bit is copied into the vacated upper bits).
 
-include::images/wavedrom/int-comp-lui-aiupc.adoc[]
+include::images/wavedrom/int-comp-lui-aiupc.edn[]
 [[int-comp-lui-aiupc]]
 //.Integer register-immediate, U-immediate
 
@@ -364,7 +374,7 @@ the _rs1_ and _rs2_ registers as source operands and write the result
 into register _rd_. The _funct7_ and _funct3_ fields select the type of
 operation.
 
-include::images/wavedrom/int_reg-reg.adoc[]
+include::images/wavedrom/int-reg-reg.edn[]
 [[int-reg-reg]]
 //.Integer register-register
 
@@ -383,7 +393,7 @@ the lower 5 bits of register _rs2_.
 
 ==== NOP Instruction
 
-include::images/wavedrom/nop.adoc[]
+include::images/wavedrom/nop.edn[]
 [[nop]]
 //.NOP instructions
 
@@ -444,7 +454,7 @@ than the regular link register.
 Plain unconditional jumps (assembler pseudoinstruction J) are encoded as
 a JAL with _rd_=`x0`.
 
-include::images/wavedrom/ct-unconditional.adoc[]
+include::images/wavedrom/ct-unconditional.edn[]
 [[ct-unconditional]]
 //.The unconditional-jump instruction, JAL
 
@@ -456,7 +466,13 @@ instruction following the jump (`pc`+4) is written to register _rd_.
 Register `x0` can be used as the destination if the result is not
 required.
 
-include::images/wavedrom/ct-unconditional-2.adoc[]
+Plain unconditional indirect jumps (assembler pseudoinstruction JR) are
+encoded as a JALR with _rd_=`x0`.
+Procedure returns in the standard calling convention (assembler
+pseudoinstruction RET) are encoded as a JALR with _rd_=`x0`, _rs1_=`x1`, and
+_imm_=0.
+
+include::images/wavedrom/ct-unconditional-2.edn[]
 [[ct-unconditional-2]]
 //.The indirect unconditional-jump instruction, JALR
 
@@ -550,7 +566,7 @@ is sign-extended and added to the address of the branch instruction to
 give the target address. The conditional branch range is
 &#177;4 KiB.
 
-include::images/wavedrom/ct-conditional.adoc[]
+include::images/wavedrom/ct-conditional.edn[]
 [[ct-conditional]]
 //.Conditional branches
 
@@ -581,7 +597,7 @@ a conditional branch instruction with an always-true condition. RISC-V
 jumps are also PC-relative and support a much wider offset range than
 branches, and will not pollute conditional-branch prediction tables.
 
-[TIP]
+[NOTE]
 ====
 The conditional branches were designed to include arithmetic comparison
 operations between two registers (as also done in PA-RISC, Xtensa, and
@@ -666,7 +682,7 @@ even though the load value is discarded.
 The EEI will define whether the memory system is little-endian or
 big-endian. In RISC-V, endianness is byte-address invariant.
 
-[TIP]
+[NOTE]
 ====
 In a system for which endianness is byte-address invariant, the
 following property holds: if a byte is stored to memory at some address
@@ -686,7 +702,7 @@ significance. Loads similarly transfer the contents of the greater
 memory byte addresses to the less-significant register bytes.
 ====
 
-include::images/wavedrom/load_store.adoc[]
+include::images/wavedrom/load-store.edn[]
 [[load-store,load and store]]
 //.Load and store instructions
 
@@ -731,7 +747,7 @@ by address misalignment result in a contained trap (allowing software
 running inside the execution environment to handle the trap) or a fatal
 trap (terminating execution).
 
-[TIP]
+[NOTE]
 ====
 Misaligned accesses are occasionally required when porting legacy code,
 and help performance on applications when using any form of packed-SIMD
@@ -775,7 +791,7 @@ are aligned.
 [[fence]]
 === Memory Ordering Instructions
 
-include::images/wavedrom/mem_order.adoc[]
+include::images/wavedrom/mem-order.edn[]
 [[mem-order]]
 //.Memory ordering instructions
 
@@ -853,7 +869,7 @@ Base implementations shall treat all such reserved configurations as
 normal fences with _fm_=0000, and standard software shall use only
 non-reserved configurations.
 
-[TIP]
+[NOTE]
 ====
 We chose a relaxed memory model to allow high performance from simple
 machine implementations and from likely future coprocessor or
@@ -865,6 +881,7 @@ ignore the _predecessor_ and _successor_ fields and always execute a
 conservative fence on all operations.
 ====
 
+[[ecall-ebreak]]
 === Environment Call and Breakpoints
 `SYSTEM` instructions are used to access system functionality that might
 require privileged access and are encoded using the I-type instruction
@@ -875,7 +892,7 @@ described in <<csrinsts>>, and the base
 unprivileged instructions are described in the following section.
 
 
-[TIP]
+[NOTE]
 ====
 The SYSTEM instructions are defined to allow simpler implementations to
 always trap to a single software trap handler. More sophisticated
@@ -883,7 +900,7 @@ implementations might execute more of each system instruction in
 hardware.
 ====
 
-include::images/wavedrom/env_call-breakpoint.adoc[]
+include::images/wavedrom/env-call-breakpoint.edn[]
 [[env-call]]
 //.Environment call and breakpoint instructions
 
@@ -906,7 +923,7 @@ to reflect that they can be used more generally than to call a
 supervisor-level operating system or debugger.
 ====
 
-[TIP]
+[NOTE]
 ====
 EBREAK was primarily designed to be used by a debugger to cause
 execution to stop and fall back into the debugger. EBREAK is also used
@@ -924,7 +941,7 @@ to distinguish a semihosting EBREAK from a debugger inserted EBREAK.
 ....
     slli x0, x0, 0x1f   # Entry NOP
     ebreak              # Break to debugger
-    srai x0, x0, 7      # NOP encoding the semihosting call number 7
+    srai x0, x0, 7      # Exit NOP
 ....
 
 Note that these three instructions must be 32-bit-wide instructions,
@@ -986,7 +1003,7 @@ HINT space is reserved for standard HINTs. The remainder of the HINT
 space is designated for custom HINTs: no standard HINTs will ever be
 defined in this subspace.
 
-[TIP]
+[NOTE]
 ====
 We anticipate standard hints to eventually include memory-system spatial
 and temporal locality hints, branch prediction hints, thread-scheduling
@@ -1063,3 +1080,5 @@ hints, security tags, and instrumentation flags for simulation/emulation.
 |SLTU |_rd_=`x0` |latexmath:[$2^{10}$]
 |===
 
+TIP: When allocating `slli x0, x0, 0x1f` or `srai x0, x0, 7` as custom HINTs,
+take note of their use in semihosting calls, as described in <<ecall-ebreak>>.
diff --git a/src/rv32e.adoc b/src/rv32e.adoc
index c30b598..35c996f 100644
--- a/src/rv32e.adoc
+++ b/src/rv32e.adoc
@@ -22,7 +22,7 @@ RV64I are also compatible with RV32E and RV64E, respectively.
 RV32E and RV64E reduce the integer register count to 16 general-purpose
 registers, (`x0-x15`), where `x0` is a dedicated zero register.
 
-[TIP]
+[NOTE]
 ====
 We have found that in the small RV32I core implementations, the upper 16
 registers consume around one quarter of the total area of the core
diff --git a/src/rv64.adoc b/src/rv64.adoc
index 531158a..8e3b60b 100644
--- a/src/rv64.adoc
+++ b/src/rv64.adoc
@@ -39,7 +39,7 @@ ensure reasonable performance for 32-bit values.
 
 ==== Integer Register-Immediate Instructions
 
-include::images/wavedrom/rv64i-base-int.adoc[]
+include::images/wavedrom/rv64i-base-int.edn[]
 [[rv64i-base-int]]
 //.RV64I register-immediate instructions
 
@@ -50,7 +50,7 @@ immediate to register _rs1_ and produces the proper sign extension of a
 writes the sign extension of the lower 32 bits of register _rs1_ into
 register _rd_ (assembler pseudoinstruction SEXT.W).
 
-include::images/wavedrom/rv64i-slli.adoc[]
+include::images/wavedrom/rv64i-slli.edn[]
 [[rv64i-slli]]
 //.RV64I register-immediate (descr ADDIW) instructions
 
@@ -67,7 +67,7 @@ copied into the vacated upper bits).
 (((RV64I, SRLIW)))
 (((RV64I, RV64I-only)))
 
-include::images/wavedrom/rv64i-slliw.adoc[]
+include::images/wavedrom/rv64i-slliw.edn[]
 [[rv64i-slliw]]
 
 SLLIW, SRLIW, and SRAIW are RV64I-only instructions that are analogously
@@ -82,7 +82,7 @@ were defined to cause illegal-instruction exceptions, whereas now they
 are marked as reserved. This is a backwards-compatible change.
 ====
 
-include::images/wavedrom/rv64_lui-auipc.adoc[]
+include::images/wavedrom/rv64-lui-auipc.edn[]
 [[rv64_lui-auipc]]
 //.RV64I register-immediate (descr) instructions
 
@@ -108,7 +108,7 @@ with LD, AUIPC with JALR, etc. in RV64I is
 ==== Integer Register-Register Operations
 
 //this diagramdoesn't match the tex specification
-include::images/wavedrom/rv64i_int-reg-reg.adoc[]
+include::images/wavedrom/rv64i-int-reg-reg.edn[]
 [[int_reg-reg]]
 //.RV64I integer register-register instructions
 
@@ -136,7 +136,7 @@ results to 64 bits. The shift amount is given by _rs2[4:0]_.
 RV64I extends the address space to 64 bits. The execution environment
 will define what portions of the address space are legal to access.
 
-include::images/wavedrom/load_store.adoc[]
+include::images/wavedrom/load-store.edn[]
 [[load_store]]
 //.Load and store instructions
 
diff --git a/src/scalar-crypto.adoc b/src/scalar-crypto.adoc
index b3de74a..59dec79 100644
--- a/src/scalar-crypto.adoc
+++ b/src/scalar-crypto.adoc
@@ -33,12 +33,6 @@ This is found in <<crypto_scalar_es>>.
 It also contains a mechanism allowing core implementers to provide
 _"Constant Time Execution"_ guarantees in <<crypto_scalar_zkt>>.
 
-A companion document _Volume II: Vector Instructions_, describes
-instruction proposals which build on the RISC-V Vector Extension.
-The Vector Cryptography extension is currently a work in progress
-waiting for the base Vector extension to stabilise.
-We expect to pick up this work in earnest in Q4-2021 or Q1-2022.
-
 [[crypto_scalar_audience]]
 ==== Intended Audience
 
@@ -211,118 +205,28 @@ protocols, while ShangMi ciphers are required for use in China.
 ==== `Zbkb` - Bitmanip instructions for Cryptography
 
 These are a subset of the Bitmanipulation Extension `Zbb` which are
-particularly useful for Cryptography.
-
-NOTE: Some of these instructions are defined in the first Bitmanip
-ratification package, and some are not (
-<<insns-pack-sc,pack>>,
-<<insns-packh-sc,packh>>,
-<<insns-packw-sc,packw>>,
-<<insns-brev8,brev8>>,
-<<insns-zip-sc,zip>>,
-<<insns-unzip-sc,unzip>>).
-All of the instructions in <<zbkb-sc>> have their complete specification included
-in this document, including those _not_ present in the initial
-Bitmanip ratification package.
-This is to make the present specification complete as a standalone document.
-Inevitably there might be small divergences between the Bitmanip and
-Scalar Cryptography specification documents as they move at different
-paces.
-When this happens, assume that the Bitmanip specification has the
-most up-to-date version of Bitmanip instructions.
-This is an unfortunate but necessary stop-gap while Scalar Cryptography
-and Bitmanip are being rapidly iterated on prior to public review.
-
-[%header,cols="^1,^1,4,8"]
-|===
-|RV32
-|RV64
-|Mnemonic
-|Instruction
-
-| &#10003; | &#10003; |  ror         | <<insns-ror-sc>>
-| &#10003; | &#10003; |  rol         | <<insns-rol-sc>>
-| &#10003; | &#10003; |  rori        | <<insns-rori-sc>>
-|          | &#10003; |  rorw        | <<insns-rorw-sc>>
-|          | &#10003; |  rolw        | <<insns-rolw-sc>>
-|          | &#10003; |  roriw       | <<insns-roriw-sc>>
-| &#10003; | &#10003; |  andn        | <<insns-andn-sc>>
-| &#10003; | &#10003; |  orn         | <<insns-orn-sc>>
-| &#10003; | &#10003; |  xnor        | <<insns-xnor-sc>>
-| &#10003; | &#10003; |  pack        | <<insns-pack-sc>>
-| &#10003; | &#10003; |  packh       | <<insns-packh-sc>>
-|          | &#10003; |  packw       | <<insns-packw-sc>>
-| &#10003; | &#10003; |  brev8       | <<insns-brev8>>
-| &#10003; | &#10003; |  rev8        | <<insns-rev8-sc>>
-| &#10003; |          |  zip         | <<insns-zip-sc>>
-| &#10003; |          |  unzip       | <<insns-unzip-sc>>
-|===
+particularly useful for Cryptography. Please refer to <<b-st-ext.adoc#zbkb>>.
 
 [[zbkc-sc,Zbkc-sc]]
 ==== `Zbkc` - Carry-less multiply instructions
 
 Constant time carry-less multiply for Galois/Counter Mode.
-These are separated from the <<zbkb-sc>> because they
+These are separated from the <<b-st-ext.adoc#zbkb>> because they
 have a considerable implementation overhead which cannot be amortised
 across other instructions.
 
-NOTE: These instructions are defined in the first Bitmanip
-ratification package for the `Zbc` extension.
-All of the instructions in <<zbkc-sc>> have their complete specification included
-in this document, including those _not_ present in the initial
-Bitmanip ratification package.
-This is to make the present specification complete as a standalone document.
-Inevitably there might be small divergences between the Bitmanip and
-Scalar Cryptography specification documents as they move at different
-paces.
-When this happens, assume that the Bitmanip specification has the
-most up-to-date version of Bitmanip instructions.
-This is an unfortunate but necessary stop-gap while Scalar Cryptography
-and Bitmanip are being rapidly iterated on prior to public review.
-
-[%header,cols="^1,^1,4,8"]
-|===
-|RV32
-|RV64
-|Mnemonic
-|Instruction
-
-| &#10003; | &#10003; |  clmul       | <<insns-clmul>>
-| &#10003; | &#10003; |  clmulh      | <<insns-clmulh-sc>>
-|===
+Please refer to <<b-st-ext.adoc#zbkc>>.
 
 [[zbkx-sc,Zbkx-sc]]
 ==== `Zbkx` - Crossbar permutation instructions
 
 These instructions are useful for implementing SBoxes in constant time, and
 potentially with DPA protections.
-These are separated from the <<zbkb-sc>> because they
+These are separated from the <<b-st-ext.adoc#zbkbc>> because they
 have an implementation overhead which cannot be amortised
 across other instructions.
 
-NOTE: All of these instructions are missing from the first Bitmanip
-ratification package.
-Hence,  all of the instructions in <<zbkx-sc>> have their complete specification
-included in this document.
-This is to make the present specification complete as a standalone document.
-Inevitably there might be small divergences between the Bitmanip and
-Scalar Cryptography specification documents as they move at different
-paces.
-When this happens, assume that the Bitmanip specification has the
-most up-to-date version of Bitmanip instructions.
-This is an unfortunate but necessary stop-gap while Scalar Cryptography
-and Bitmanip are being rapidly iterated on prior to public review.
-
-[%header,cols="^1,^1,4,8"]
-|===
-|RV32
-|RV64
-|Mnemonic
-|Instruction
-
-| &#10003; | &#10003; |  xperm8      | <<insns-xperm8>>
-| &#10003; | &#10003; |  xperm4      | <<insns-xperm4>>
-|===
+Please refer to <<b-st-ext.adoc#zbkx>>.
 
 [[zknd,Zknd]]
 ==== `Zknd` - NIST Suite: AES Decryption
@@ -1321,14 +1225,14 @@ Included in::
 
 <<<
 
-[#insns-brev8,reftext="Reverse bits in bytes"]
+[#insns-brev8-sc,reftext="Reverse bits in bytes"]
 ==== brev8
 
 Synopsis::
 Reverse the bits in each byte of a source register.
 
 Mnemonic::
-brev8, _rd_, _rs_
+brev8 _rd_, _rs_
 
 Encoding::
 [wavedrom, , svg]
@@ -1336,29 +1240,21 @@ Encoding::
 {reg:[
     { bits:  7, name: 0x13, attr: ['OP-IMM'] },
     { bits:  5, name: 'rd' },
-    { bits:  3, name: 0x65 },
+    { bits:  3, name: 0x5 },
     { bits:  5, name: 'rs' },
-    { bits:  12, name: 0x687 },
+    { bits: 12, name: 0x687 }
 ]}
 ....
 
 Description:: 
 This instruction reverses the order of the bits in every byte of a register.
 
-[NOTE]
-====
-This instruction is a specific encoding of a more generic instruction which was originally
-proposed as part of the RISC-V Bitmanip extension (grevi). Eventually, the more generic
-instruction may be standardised. Until then, only the most common instances of it, such as
-this, are being included in specifications.
-====
-
 Operation::
 [source,sail]
 --
 result : xlenbits = EXTZ(0b0);
 foreach (i from 0 to sizeof(xlen) by 8) {
-result[i+7..i] = reverse_bits_in_byte(X(rs1)[i+7..i]);
+    result[i+7..i] = reverse_bits_in_byte(X(rs1)[i+7..i]);
 };
 X(rd) = result;
 --
@@ -2411,7 +2307,7 @@ are each represented by two 32-bit registers.
 This instruction must _always_ be implemented such that its execution
 latency does not depend on the data being operated on.
 
-[TIP]
+[NOTE]
 .Note to software developers
 ====
 The entire Sigma0 transform for SHA2-512 may be computed on RV32
@@ -2485,7 +2381,7 @@ are each represented by two 32-bit registers.
 This instruction must _always_ be implemented such that its execution
 latency does not depend on the data being operated on.
 
-[TIP]
+[NOTE]
 .Note to software developers
 ====
 The entire Sigma0 transform for SHA2-512 may be computed on RV32
@@ -2559,7 +2455,7 @@ are each represented by two 32-bit registers.
 This instruction must _always_ be implemented such that its execution
 latency does not depend on the data being operated on.
 
-[TIP]
+[NOTE]
 .Note to software developers
 ====
 The entire Sigma1 transform for SHA2-512 may be computed on RV32
@@ -2633,7 +2529,7 @@ are each represented by two 32-bit registers.
 This instruction must _always_ be implemented such that its execution
 latency does not depend on the data being operated on.
 
-[TIP]
+[NOTE]
 .Note to software developers
 ====
 The entire Sigma1 transform for SHA2-512 may be computed on RV32
@@ -2706,7 +2602,7 @@ is represented by two 32-bit registers.
 This instruction must _always_ be implemented such that its execution
 latency does not depend on the data being operated on.
 
-[TIP]
+[NOTE]
 .Note to software developers
 ====
 The entire Sum0 transform for SHA2-512 may be computed on RV32
@@ -2780,7 +2676,7 @@ is represented by two 32-bit registers.
 This instruction must _always_ be implemented such that its execution
 latency does not depend on the data being operated on.
 
-[TIP]
+[NOTE]
 .Note to software developers
 ====
 The entire Sum1 transform for SHA2-512 may be computed on RV32
@@ -3331,7 +3227,8 @@ Included in::
 ==== unzip
 
 Synopsis::
-Implements the inverse of the zip instruction.
+Place odd and even bits of the source register into upper and lower halves of
+the destination register, respectively.
 
 Mnemonic::
 unzip _rd_, _rs_
@@ -3345,14 +3242,14 @@ Encoding::
 {bits: 5, name: 'rd'},
 {bits: 3, name: 0x5},
 {bits: 5, name: 'rs1'},
-{bits: 5, name: 0x1f},
+{bits: 5, name: 0xf},
 {bits: 7, name: 0x4},
 ]}
 ....
 
 Description:: 
-This instruction gathers bits from the high and low halves of the source
-word into odd/even bit positions in the destination word.
+This instruction scatters all of the odd and even bits of a source word into
+the high and low halves of a destination word.
 It is the inverse of the <<insns-zip-sc,zip>> instruction.
 This instruction is available only on RV32.
 
@@ -3436,48 +3333,51 @@ Included in::
 |===
 
 <<<
-[#insns-xperm8,reftext="Crossbar permutation (bytes)"]
+[#insns-xperm8-sc,reftext="Crossbar permutation (bytes)"]
 ==== xperm8
 
 Synopsis::
-Byte-wise lookup of indicies into a vector.
+Byte-wise lookup of indices into a vector in registers.
 
 Mnemonic::
-xprem8 _rd_, _rs1_, _rs2_
+xperm8 _rd_, _rs1_, _rs2_
 
 Encoding::
 [wavedrom, , svg]
 ....
 {reg:[
-    { bits:  2, name: 0x3 },
-    { bits:  5, name: 0xC },
-    { bits:  5, name: 'rd'},
-    { bits:  3, name: 0x4 },
-    { bits:  5, name: 'rs1' },
-    { bits:  5, name: 'rs2' },
-    { bits:  7, name: 0x14 },
+{bits: 2, name: 0x3},
+{bits: 5, name: 0xc},
+{bits: 5, name: 'rd'},
+{bits: 3, name: 0x4},
+{bits: 5, name: 'rs1'},
+{bits: 5, name: 'rs2'},
+{bits: 7, name: 0x14},
 ]}
 ....
 
 Description:: 
-The xperm8 instruction operates on bytes. The rs1 register contains a vector of XLEN/8 8-bit elements. The
-rs2 register contains a vector of XLEN/8 8-bit indexes. The result is each element in rs2 replaced by the
-indexed element in rs1, or zero if the index into rs2 is out of bounds.
+The xperm8 instruction operates on bytes.
+The _rs1_ register contains a vector of XLEN/8 8-bit elements.
+The _rs2_ register contains a vector of XLEN/8 8-bit indexes.
+The result is each element in _rs2_ replaced by the indexed element in _rs1_,
+or zero if the index into _rs2_ is out of bounds.
 
 Operation::
 [source,sail]
 --
 val xperm8_lookup : (bits(8), xlenbits) -> bits(8)
 function xperm8_lookup (idx, lut) = {
-(lut >> (idx @ 0b000))[7..0]
+    (lut >> (idx @ 0b000))[7..0]
 }
-function clause execute ( XPERM_8 (rs2,rs1,rd)) = {
-result : xlenbits = EXTZ(0b0);
-foreach(i from 0 to xlen by 8) {
-result[i+7..i] = xperm8_lookup(X(rs2)[i+7..i], X(rs1));
-};
-X(rd) = result;
-RETIRE_SUCCESS
+
+function clause execute ( XPERM8 (rs2,rs1,rd)) = {
+    result : xlenbits = EXTZ(0b0);
+    foreach(i from 0 to xlen by 8) {
+        result[i+7..i] = xperm8_lookup(X(rs2)[i+7..i], X(rs1));
+    };
+    X(rd) = result;
+    RETIRE_SUCCESS
 }
 --
 
@@ -3488,18 +3388,18 @@ Included in::
 |Minimum version
 |Lifecycle state
 
-|Zbkx (<<#zbkx-sc>>)
-|v1.0.0-rc4
+|Zbkx (<<#zbkx>>)
+|v1.0
 |Ratified
 |===
 
 <<<
 
-[#insns-xperm4,reftext="Crossbar permutation (nibbles)"]
+[#insns-xperm4-sc,reftext="Crossbar permutation (nibbles)"]
 ==== xperm4
 
 Synopsis::
-Nibble-wise lookup of indicies into a vector.
+Nibble-wise lookup of indices into a vector.
 
 Mnemonic::
 xperm4 _rd_, _rs1_, _rs2_
@@ -3508,35 +3408,38 @@ Encoding::
 [wavedrom, , svg]
 ....
 {reg:[
-    { bits:  2, name: 0x3 },
-    { bits:  5, name: 0xC },
-    { bits:  5, name: 'rd'},
-    { bits:  3, name: 0x2 },
-    { bits:  5, name: 'rs1' },
-    { bits:  5, name: 'rs2' },
-    { bits:  7, name: 0x14 },
+{bits: 2, name: 0x3},
+{bits: 5, name: 0xc},
+{bits: 5, name: 'rd'},
+{bits: 3, name: 0x2},
+{bits: 5, name: 'rs1'},
+{bits: 5, name: 'rs2'},
+{bits: 7, name: 0x14},
 ]}
 ....
 
 Description:: 
-The xperm4 instruction operates on nibbles. The rs1 register contains a vector of XLEN/4 4-bit elements.
-The rs2 register contains a vector of XLEN/4 4-bit indexes. The result is each element in rs2 replaced by the
-indexed element in rs1, or zero if the index into rs2 is out of bounds.
+The xperm4 instruction operates on nibbles.
+The _rs1_ register contains a vector of XLEN/4 4-bit elements.
+The _rs2_ register contains a vector of XLEN/4 4-bit indexes.
+The result is each element in _rs2_ replaced by the indexed element in _rs1_,
+or zero if the index into _rs2_ is out of bounds.
 
 Operation::
 [source,sail]
 --
 val xperm4_lookup : (bits(4), xlenbits) -> bits(4)
 function xperm4_lookup (idx, lut) = {
-(lut >> (idx @ 0b00))[3..0]
+    (lut >> (idx @ 0b00))[3..0]
 }
-function clause execute ( XPERM_4 (rs2,rs1,rd)) = {
-result : xlenbits = EXTZ(0b0);
-foreach(i from 0 to xlen by 4) {
-result[i+3..i] = xperm4_lookup(X(rs2)[i+3..i], X(rs1));
-};
-X(rd) = result;
-RETIRE_SUCCESS
+
+function clause execute ( XPERM4 (rs2,rs1,rd)) = {
+    result : xlenbits = EXTZ(0b0);
+    foreach(i from 0 to xlen by 4) {
+        result[i+3..i] = xperm4_lookup(X(rs2)[i+3..i], X(rs1));
+    };
+    X(rd) = result;
+    RETIRE_SUCCESS
 }
 --
 
@@ -3547,8 +3450,8 @@ Included in::
 |Minimum version
 |Lifecycle state
 
-|Zbkx (<<#zbkx-sc>>)
-|v1.0.0-rc4
+|Zbkx (<<#zbkx>>)
+|v1.0
 |Ratified
 |===
 
@@ -3558,8 +3461,8 @@ Included in::
 ==== zip
 
 Synopsis::
-Gather odd and even bits of the source word into upper/lower halves of the
-destination.
+Interleave upper and lower halves of the source register into odd and even
+bits of the destination register, respectivley.
 
 Mnemonic::
 zip _rd_, _rs_
@@ -3573,14 +3476,14 @@ Encoding::
 {bits: 5, name: 'rd'},
 {bits: 3, name: 0x1},
 {bits: 5, name: 'rs1'},
-{bits: 5, name: 0x1e},
+{bits: 5, name: 0xf},
 {bits: 7, name: 0x4},
 ]}
 ....
 
 Description:: 
-This instruction scatters all of the odd and even bits of a source word into
-the high and low halves of a destination word.
+This instruction gathers bits from the high and low halves of the source
+word into odd/even bit positions in the destination word.
 It is the inverse of the <<insns-unzip-sc,unzip>> instruction.
 This instruction is available only on RV32.
 
@@ -3654,15 +3557,15 @@ The 32-bit contents of `seed` are as follows:
 |`15: 0` |`entropy` |16 bits of randomness, only when `OPST=ES16`.
 |=======================================================================
 
-The `seed` CSR must be accessed with a read-write instruction. A read-only
-instruction such as `CSRRS/CSRRC` with `rs1=x0` or `CSRRSI/CSRRCI` with
-`uimm=0` will raise an illegal instruction exception.
+Attempts to access the `seed` CSR using a read-only CSR-access instruction
+(`CSRRS`/`CSRRC` with `rs1=x0` or `CSRRSI`/`CSRRCI` with `uimm=0`) raise an
+illegal instruction exception; any other CSR-access instruction may be used
+to access `seed`.
 The write value (in `rs1` or `uimm`) must be ignored by implementations.
 The purpose of the write is to signal polling and flushing.
 
-The instruction `csrrw rd, seed, x0` can be used for fetching seed status
-and entropy values. It is available on both RV32 and RV64 base architectures
-and will zero-extend the 32-bit word to XLEN bits.
+Software normally uses the instruction `csrrw rd, seed, x0` to read the `seed`
+CSR.
 
 Encoding::
 [wavedrom, , svg]
@@ -4269,8 +4172,8 @@ specific instances of `grevi`, `shfli` and `unshfli` respectively.
 
 | &#10003; | &#10003; |  clmul       | <<insns-clmul-sc>>
 | &#10003; | &#10003; |  clmulh      | <<insns-clmulh-sc>>
-| &#10003; | &#10003; |  xperm4      | <<insns-xperm4>>
-| &#10003; | &#10003; |  xperm8      | <<insns-xperm8>>
+| &#10003; | &#10003; |  xperm4      | <<insns-xperm4-sc>>
+| &#10003; | &#10003; |  xperm8      | <<insns-xperm8-sc>>
 | &#10003; | &#10003; |  ror         | <<insns-ror-sc>>
 | &#10003; | &#10003; |  rol         | <<insns-rol-sc>>
 | &#10003; | &#10003; |  rori        | <<insns-rori-sc>>
@@ -4283,7 +4186,7 @@ specific instances of `grevi`, `shfli` and `unshfli` respectively.
 | &#10003; | &#10003; |  pack        | <<insns-pack-sc>>
 | &#10003; | &#10003; |  packh       | <<insns-packh-sc>>
 |          | &#10003; |  packw       | <<insns-packw-sc>>
-| &#10003; | &#10003; |  brev8       | <<insns-brev8>>
+| &#10003; | &#10003; |  brev8       | <<insns-brev8-sc>>
 | &#10003; | &#10003; |  rev8        | <<insns-rev8-sc>>
 | &#10003; |          |  zip         | <<insns-zip-sc>>
 | &#10003; |          |  unzip       | <<insns-unzip-sc>>
@@ -4731,7 +4634,9 @@ refreshed (reseeded) for forward and backward security.
 
 ==== Specific Rationale and Considerations
 
-===== (<<crypto_scalar_seed_csr>>) The `seed` CSR 
+=====  The `seed` CSR 
+
+See <<crypto_scalar_seed_csr>>.
 
 The interface was designed to be simple so that a vendor- and
 device-independent driver component (e.g., in Linux kernel,
@@ -4751,7 +4656,7 @@ a write operation on this particular CSR.
 A blocking instruction may have been easier to use, but most users should
 be querying a (D)RBG instead of an entropy source.
 Without a polling-style mechanism, the entropy source could hang for
-thousands of cycles under some circumstances. A `wfi` ot `pause`
+thousands of cycles under some circumstances. A `wfi` or `pause`
 mechanism (at least potentially) allows energy-saving sleep on MCUs
 and context switching on higher-end CPUs.
 
@@ -4767,7 +4672,9 @@ conditioning discussed in <<crypto_scalar_appx_es_crypto-cond>>),
 and the desire to have all of the bits "in the same place" on
 both RV32 and RV64 architectures for programming convenience.
 
-===== (<<crypto_scalar_es_req_90b>>) NIST SP 800-90B
+===== NIST SP 800-90B
+
+See <<crypto_scalar_es_req_90b>>.
 
 SP 800-90C cite:[BaKeRo:21] states that each conditioned block of n bits
 is required to have n+64 bits of input entropy to attain full entropy.
@@ -4798,7 +4705,9 @@ Section 4.4 of cite:[TuBaKe:18]: the repetition count test and adaptive
 proportion test, or show that the same flaws will be detected
 by vendor-defined tests.
 
-===== (<<crypto_scalar_es_req_ptg2>>) BSI AIS-31
+===== BSI AIS-31
+
+See <<crypto_scalar_es_req_ptg2>>.
 
 PTG.2 is one of the security and functionality classes defined in
 BSI AIS 20/31 cite:[KiSc11]. The PTG.2 source requirements work as a
@@ -4831,7 +4740,9 @@ PTG.2 modules built and certified to the AIS-31 standard can also meet the
 "full entropy" condition after 2:1 cryptographic conditioning, but not
 necessarily so. The technical validation process is somewhat different.
 
-===== (<<crypto_scalar_es_req_virt>>) Virtual Sources
+===== Virtual Sources
+
+<<crypto_scalar_es_req_virt>>.
 
 All sources that are not direct physical sources (meeting the SP 800-90B
 or the AIS-31 PTG.2 requirements) need to meet the security requirements
@@ -4847,7 +4758,9 @@ standards and applications. The 256-bit requirement maps to
 in Suite B and the newer U.S. Government CNSA Suite cite:[NS15].
 
 [[crypto_scalar_appx_es_access]]
-===== (<<crypto_scalar_es_access>>) Security Considerations for Direct Hardware Access
+===== Security Considerations for Direct Hardware Access
+
+<<crypto_scalar_es_access>>.
 
 The ISA implementation and system design must try to ensure that the
 hardware-software interface minimizes avenues for adversarial
@@ -4855,7 +4768,7 @@ information flow even if not explicitly forbidden in the specification.
 
 For security, virtualization requires both conditioning and DRBG processing
 of physical entropy output. It is recommended if a single physical entropy
-source is shared between multiple different virtual machnies or if the 
+source is shared between multiple different virtual machines or if the 
 guest OS is untrusted. A virtual entropy source is significantly more
 resistant to depletion attacks and also lessens the risk from covert channels.
 
@@ -5031,7 +4944,7 @@ operational at the same time.
 The noise source state shall be protected from adversarial
 knowledge or influence to the greatest extent possible. The methods
 used for this shall be documented, including a description of the
-(conceptual) security boundarys role in protecting the noise source
+(conceptual) security boundary's role in protecting the noise source
 from adversarial observation or influence.
 
 An entropy source is a singular resource, subject to depletion
diff --git a/src/smcdeleg.adoc b/src/smcdeleg.adoc
index fd0be2a..1b8caaa 100644
--- a/src/smcdeleg.adoc
+++ b/src/smcdeleg.adoc
@@ -130,7 +130,7 @@ raise a virtual instruction exception.
 === Virtualizing `scountovf`
 
 For implementations that support Smcdeleg/Ssccfg, Sscofpmf, and the H
-extension, when `menvcfg`.CDE=1, attempts to access `scountovf` from VS-mode
+extension, when `menvcfg`.CDE=1, attempts to read `scountovf` from VS-mode
 or VU-mode raise a virtual instruction exception.
 
 === Virtualizing Local Counter Overflow Interrupts 
diff --git a/src/smcntrpmf.adoc b/src/smcntrpmf.adoc
index ca87901..c47402f 100644
--- a/src/smcntrpmf.adoc
+++ b/src/smcntrpmf.adoc
@@ -34,7 +34,7 @@ mcyclecfg and minstretcfg are 64-bit registers that configure privilege mode fil
 
 When all __x__INH bits are zero, event counting is enabled in all modes.
 
-For each bit in 61:58, if the associated privilege mode is not implemented, the bit is read-only zero.  Bits 57:56 are reserved for possible future modes.  
+For each bit in 61:58, if the associated privilege mode is not implemented, the bit is read-only zero.
 
 For RV32, bits 63:32 of mcyclecfg can be accessed via the mcyclecfgh CSR, and bits 63:32 of minstretcfg can be accessed via the minstretcfgh CSR.
 
diff --git a/src/smepmp.adoc b/src/smepmp.adoc
index 0f602c5..7bffde7 100644
--- a/src/smepmp.adoc
+++ b/src/smepmp.adoc
@@ -118,7 +118,7 @@ Also when ``mseccfg.MML`` is set, according to 4b it’s not possible to add a _
 +
 [NOTE]
 ====
-If ``mseccfg.RLB`` is not used and left unset, it wil be locked as soon as a PMP rule/entry with the ``pmpcfg.L`` bit set is configured.
+If ``mseccfg.RLB`` is not used and left unset, it will be locked as soon as a PMP rule/entry with the ``pmpcfg.L`` bit set is configured.
 ====
 +
 [IMPORTANT]
@@ -151,7 +151,7 @@ To make sure that shared data regions can’t be executed and shared code region
 +
 [NOTE]
 ====
-For adding _Shared-region_ rules with executable privileges to share code segments between M-mode and S/U-mode, ``mseccfg.RLB`` needs to be implemented, or else such rules can only be added together with ``mseccfg.MML`` being set on *PMP Reset*. That's because the reserved encoding ``pmpcfg.RW=01`` being used for _Shared-region_ rules is only defined when ``mseccfg.MML`` is set, and 4b prevents the adition of rules with executable privileges on M-mode after ``mseccfg.MML`` is set unless ``mseccfg.RLB`` is also set.
+For adding _Shared-region_ rules with executable privileges to share code segments between M-mode and S/U-mode, ``mseccfg.RLB`` needs to be implemented, or else such rules can only be added together with ``mseccfg.MML`` being set on *PMP Reset*. That's because the reserved encoding ``pmpcfg.RW=01`` being used for _Shared-region_ rules is only defined when ``mseccfg.MML`` is set, and 4b prevents the addition of rules with executable privileges on M-mode after ``mseccfg.MML`` is set unless ``mseccfg.RLB`` is also set.
 ====
 +
 [NOTE]
diff --git a/src/sscofpmf.adoc b/src/sscofpmf.adoc
index 7e67a25..84f1a09 100644
--- a/src/sscofpmf.adoc
+++ b/src/sscofpmf.adoc
@@ -71,17 +71,20 @@ count overflow interrupt disable for the associated hpmcounter.
 Count overflow never results from writes to the mhpmcounter__n__ or
 mhpmevent__n__ registers, only from hardware increments of counter registers.
 
-This "count overflow interrupt request" signal is treated as a standard local
-interrupt that corresponds to bit 13 in the mip/mie/sip/sie registers. The
-mip/sip LCOFIP and mie/sie LCOFIE bits are respectively the interrupt-pending
-and interrupt-enable bits for this interrupt. ('LCOFI' represents 'Local Count
-Overflow Interrupt'.)
-
-Generation of a "count overflow interrupt request" by an hpmcounter sets the
-LCOFIP bit in the mip/sip registers and sets the associated OF bit. The mideleg
-register controls the delegation of this interrupt to S-mode versus M-mode. The
-LCOFIP bit is cleared by software before servicing the count overflow interrupt
-resulting from one or more count overflows.
+This count-overflow-interrupt-request signal is treated as a standard local
+interrupt that corresponds to bit 13 in the `mip`/`mie`/`sip`/`sie` registers.
+The `mip`/`sip` LCOFIP and `mie`/`sie` LCOFIE bits are, respectively, the
+interrupt-pending and interrupt-enable bits for this interrupt.
+('LCOFI' represents 'Local Count Overflow Interrupt'.)
+
+Generation of a count-overflow-interrupt request by an `hpmcounter` sets the
+associated OF bit.
+When an OF bit is set, it eventually, but not necessarily immediately, sets
+the LCOFIP bit in the `mip`/`sip` registers.
+The LCOFIP bit is cleared by software before servicing the count overflow
+interrupt resulting from one or more count overflows.
+The `mideleg` register controls the delegation of this interrupt to S-mode
+versus M-mode.
 
 [NOTE]
 ====
diff --git a/src/ssdbltrp.adoc b/src/ssdbltrp.adoc
index e2b1127..83a98bd 100644
--- a/src/ssdbltrp.adoc
+++ b/src/ssdbltrp.adoc
@@ -10,6 +10,6 @@ S/HS-mode.
 The Ssdbltrp extension adds the `menvcfg`.DTE (See <<sec:menvcfg>>) and the
 `sstatus`.SDT fields (See <<sstatus>>). If the hypervisor extension is
 additionally implemented, then the extension adds the `henvcfg`.DTE (See
-<<sec:henvcfg>>) and the `vstatus`.SDT fields (See <<vstatus>>).
+<<sec:henvcfg>>) and the `vsstatus`.SDT fields (See <<vsstatus>>).
 
 See <<supv-double-trap>> for the operational details.
diff --git a/src/sstc.adoc b/src/sstc.adoc
index 8198349..49be41a 100644
--- a/src/sstc.adoc
+++ b/src/sstc.adoc
@@ -38,13 +38,15 @@ bits, while accesses to the `stimecmph` CSR access the high 32 bits of `stimecmp
 The CSR numbers for `stimecmp` / `stimecmph` are 0x14D / 0x15D (within the
 Supervisor Trap Setup block of CSRs).
 
-A supervisor timer interrupt becomes pending - as reflected in the STIP bit in
-the mip and sip registers - whenever time contains a value greater than or
-equal to stimecmp, treating the values as unsigned integers. Writes to stimecmp
-are guaranteed to be reflected in STIP eventually, but not necessarily
-immediately. The interrupt remains posted until stimecmp becomes greater than
-time - typically as a result of writing stimecmp. The interrupt will be taken
-based on the standard interrupt enable and delegation rules.
+A supervisor timer interrupt becomes pending, as reflected in the STIP bit in
+the `mip` and `sip` registers whenever `time` contains a value greater than or
+equal to `stimecmp`, treating the values as unsigned integers.
+If the result of this comparison changes, it is guaranteed to be reflected in
+STIP eventually, but not necessarily immediately.
+The interrupt remains posted until `stimecmp` becomes greater than `time`,
+typically as a result of writing `stimecmp`.
+The interrupt will be taken based on the standard interrupt enable and
+delegation rules.
 
 [NOTE]
 ====
@@ -122,14 +124,16 @@ The proposed CSR numbers for `vstimecmp` / `vstimecmph` are 0x24D / 0x25D (withi
 the Virtual Supervisor Registers block of CSRs, and mirroring the CSR numbers
 for stimecmp/stimecmph).
 
-A virtual supervisor timer interrupt becomes pending - as reflected in the
-VSTIP bit in the `hip` register - whenever (`time` + `htimedelta`), truncated to 64
-bits, contains a value greater than or equal to `vstimecmp`, treating the values
-as unsigned integers. Writes to `vstimecmp` and `htimedelta` are guaranteed to be
-reflected in VSTIP eventually, but not necessarily immediately. The interrupt
-remains posted until `vstimecmp` becomes greater than (`time` + `htimedelta`) -
-typically as a result of writing `vstimecmp`. The interrupt will be taken based
-on the standard interrupt enable and delegation rules while V=1.
+A virtual supervisor timer interrupt becomes pending, as reflected in the
+VSTIP bit in the `hip` register, whenever (`time` + `htimedelta`), truncated
+to 64 bits, contains a value greater than or equal to `vstimecmp`, treating
+the values as unsigned integers.
+If the result of this comparison changes, it is guaranteed to be reflected in
+VSTIP eventually, but not necessarily immediately.
+The interrupt remains posted until `vstimecmp` becomes greater than (`time`
++ `htimedelta`), typically as a result of writing `vstimecmp`.
+The interrupt will be taken based on the standard interrupt enable and
+delegation rules while V=1.
 
 [NOTE]
 ====
diff --git a/src/supervisor.adoc b/src/supervisor.adoc
index daecbc2..fee952f 100644
--- a/src/supervisor.adoc
+++ b/src/supervisor.adoc
@@ -149,6 +149,20 @@ and load and store effective addresses are taken modulo
 latexmath:[$2^{\text{UXLEN}}$]. For example, when UXLEN=32 and SXLEN=64,
 user-mode memory accesses reference the lowest 4 GiB of the address space.
 
+Some HINT instructions are encoded as integer computational instructions that
+overwrite their destination register with its current value, e.g.,
+`c.addi x8, 0`.
+When such a HINT is executed with XLEN < SXLEN and bits SXLEN..XLEN of the
+destination register not all equal to bit XLEN-1, it is implementation-defined
+whether bits SXLEN..XLEN of the destination register are unchanged or are
+overwritten with copies of bit XLEN-1.
+
+NOTE: This definition allows implementations to elide register writeback for
+some HINTs, while allowing them to execute other HINTs in the same manner as
+other integer computational instructions.
+The implementation choice is observable only by S-mode with SXLEN > UXLEN; it
+is invisible to U-mode.
+
 [[sum]]
 ===== Memory Privilege in `sstatus` Register
 
@@ -697,6 +711,7 @@ instruction bits is implemented, `stval` must also be able to hold all
 values less than latexmath:[$2^N$], where latexmath:[$N$] is the smaller
 of SXLEN and ILEN.
 
+[[sec:senvcfg]]
 ==== Supervisor Environment Configuration (`senvcfg`) Register 
 
 The `senvcfg` CSR is an SXLEN-bit read/write register, formatted as
@@ -1096,13 +1111,6 @@ If the value held in _rs1_ is not a valid virtual address, then the
 SFENCE.VMA instruction has no effect. No exception is raised in this
 case.
 
-When __rs2__&#8800;``x0``, bits SXLEN-1:ASIDMAX of the value held
-in _rs2_ are reserved for future standard use. Until their use is
-defined by a standard extension, they should be zeroed by software and
-ignored by current implementations. Furthermore, if
-ASIDLEN<ASIDMAX, the implementation shall ignore bits
-ASIDMAX-1:ASIDLEN of the value held in _rs2_.
-
 [NOTE]
 ====
 It is always legal to over-fence, e.g., by fencing only based on a
@@ -1114,6 +1122,13 @@ choice not to raise an exception when an invalid virtual address is held
 in _rs1_ facilitates this type of simplification.
 ====
 
+When __rs2__&#8800;``x0``, bits SXLEN-1:ASIDMAX of the value held
+in _rs2_ are reserved for future standard use. Until their use is
+defined by a standard extension, they should be zeroed by software and
+ignored by current implementations. Furthermore, if
+ASIDLEN<ASIDMAX, the implementation shall ignore bits
+ASIDMAX-1:ASIDLEN of the value held in _rs2_.
+
 An implicit read of the memory-management data structures may return any
 translation for an address that was valid at any time since the most
 recent SFENCE.VMA that subsumes that address. The ordering implied by
@@ -1169,7 +1184,7 @@ without the need to execute an SFENCE.VMA instruction. Changing
 immediately, without the need to execute an SFENCE.VMA instruction.
 Likewise, changes to `satp`.ASID take effect immediately.
 
-[TIP]
+[NOTE]
 ====
 The following common situations typically require executing an
 SFENCE.VMA instruction:
@@ -2227,29 +2242,32 @@ exceptions when A/D bits need be set, instead takes effect.
 The Svade extension is also defined in <<translation>>.
 
 [[sec:svvptc]]
-== "Svvptc" Extension for Eliding Memory-Management Fences on Making PTEs Valid, Version 1.0
+== "Svvptc" Extension for Obviating Memory-Management Instructions after Marking PTEs Valid, Version 1.0
 
-When the Svvptc extension is implemented, explicit stores that update the Valid
-bit of leaf and/or non-leaf PTEs from 0 to 1 and are visible to a hart will
-eventually become visible within a bounded timeframe to subsequent implicit
+When the Svvptc extension is implemented, explicit stores by a hart that update
+the Valid bit of leaf and/or non-leaf PTEs from 0 to 1 and are visible to a hart
+will eventually become visible within a bounded timeframe to subsequent implicit
 accesses by that hart to such PTEs.
 
 [NOTE]
 ====
-Typically, PTEs are marked as Valid by the operating system following a
-page-fault exception or during system calls for memory mapping. In such cases,
-the trap handler commonly employs an `SRET` instruction to return from the trap.
-When Svvptc is implemented, the stores it executes to change the Valid bit
-of the PTEs from 0 to 1 then become visible to implicit references to those PTEs
-within a bounded timeframe. This visibility pertains to the instructions like
-the one causing the page fault or those accessing new memory regions. A
-memory-management fence can be used to force immediate visibility of these PTE
-updates to all implicit references associated with instructions following the
-memory-management fence. However, when Svvptc is implemented, visibility (in a
-bounded amount of time) is guaranteed and use of a memory-management fence is
-not required in these scenarios. While this approach might lead to an occasional
-gratuitous page-fault, the performance benefit of omitting the memory-management
-fence instructions outweighs the occasional cost of a gratuitous page fault.
+Svvptc relieves an operating system from executing certain memory-management
+instructions, such as `SFENCE.VMA` or `SINVAL.VMA`, which would normally be used
+to synchronize the hart's address-translation caches when a memory-resident PTE
+is changed from Invalid to Valid. Synchronizing the hart's address-translation
+caches with other forms of updates to a memory-resident PTE, including when a
+PTE is changed from Valid to Invalid, requires the use of suitable
+memory-management instructions. Svvptc guarantees that a change to a PTE from
+Invalid to Valid is made visible within a bounded time, thereby making the
+execution of these memory-management instructions redundant. The performance
+benefit of eliding these instructions outweighs the cost of an occasional
+gratuitous additional page fault that may occur.
+
+Depending on the microarchitecture, some possible ways to facilitate
+implementation of Svvptc include: not having any address-translation caches, not
+storing Invalid PTEs in the address-translation caches, automatically evicting
+Invalid PTEs using a bounded timer, or making address-translation caches
+coherent with store instructions that modify PTEs.
 ====
 
 ////
diff --git a/src/unpriv-cfi.adoc b/src/unpriv-cfi.adoc
index 1615d62..ed17e74 100644
--- a/src/unpriv-cfi.adoc
+++ b/src/unpriv-cfi.adoc
@@ -554,7 +554,8 @@ that uses shadow stacks is as follows:
          :
         ld x1,(sp)     # pop link register x1 from regular stack
         addi sp,sp,8
-        sspopchk x1    # fault if x1 not equal to shadow return address
+        sspopchk x1    # fault if x1 not equal to shadow
+                       # return address
         ret
 ----
 
@@ -772,7 +773,7 @@ data values.
 ----
   if privilege_mode != M && menvcfg.SSE == 0
       raise illegal-instruction exception
-  if S-mode not implemented
+  else if S-mode not implemented
       raise illegal-instruction exception
   else if privilege_mode == U && senvcfg.SSE == 0
       raise illegal-instruction exception
@@ -796,7 +797,7 @@ address in `rs1`.
 ----
   if privilege_mode != M && menvcfg.SSE == 0
       raise illegal-instruction exception
-  if S-mode not implemented
+  else if S-mode not implemented
       raise illegal-instruction exception
   else if privilege_mode == U && senvcfg.SSE == 0
       raise illegal-instruction exception
diff --git a/src/v-st-ext.adoc b/src/v-st-ext.adoc
index b8cd859..30e44dc 100644
--- a/src/v-st-ext.adoc
+++ b/src/v-st-ext.adoc
@@ -156,7 +156,7 @@ The `vtype` register has five fields, `vill`, `vma`, `vta`,
 `vsew[2:0]`, and `vlmul[2:0]`.  Bits `vtype[XLEN-2:8]` should be
 written with zero, and non-zero values in this field are reserved.
 
-include::images/wavedrom/vtype-format.adoc[]
+include::images/wavedrom/vtype-format.edn[]
 
 NOTE: A small implementation supporting ELEN=32 requires only seven
 bits of state in `vtype`: two bits for `ma` and `ta`, two bits for
@@ -878,11 +878,11 @@ floating-point load/store 12-bit immediate field to provide further
 vector instruction encoding, with bit 25 holding the standard vector
 mask bit (see <<sec-vector-mask-encoding>>).
 
-include::images/wavedrom/vmem-format.adoc[]
+include::images/wavedrom/vmem-format.edn[]
 
-include::images/wavedrom/valu-format.adoc[]
+include::images/wavedrom/valu-format.edn[]
 
-include::images/wavedrom/vcfg-format.adoc[]
+include::images/wavedrom/vcfg-format.edn[]
 
 Vector instructions can have scalar or vector source operands and
 produce scalar or vector results, and most vector instructions can be
@@ -1143,11 +1143,11 @@ their arguments, and write the new value of `vl` into `rd`.
  vsetvl  rd, rs1, rs2      # rd = new vl, rs1 = AVL, rs2 = new vtype value
 ----
 
-include::images/wavedrom/vcfg-format.adoc[]
+include::images/wavedrom/vcfg-format.edn[]
 
 ==== `vtype` encoding
 
-include::images/wavedrom/vtype-format.adoc[]
+include::images/wavedrom/vtype-format.edn[]
 
 The new `vtype` value is encoded in the immediate fields of `vsetvli`
 and `vsetivli`, and in the `rs2` register for `vsetvl`.
@@ -1163,13 +1163,13 @@ and `vsetivli`, and in the `rs2` register for `vsetvl`.
  mf8  # LMUL=1/8
  mf4  # LMUL=1/4
  mf2  # LMUL=1/2
- m1   # LMUL=1, assumed if m setting absent
+ m1   # LMUL=1
  m2   # LMUL=2
  m4   # LMUL=4
  m8   # LMUL=8
 
 Examples:
-    vsetvli t0, a0, e8, ta, ma          # SEW= 8, LMUL=1
+    vsetvli t0, a0, e8, m1, ta, ma      # SEW= 8, LMUL=1
     vsetvli t0, a0, e8, m2, ta, ma      # SEW= 8, LMUL=2
     vsetvli t0, a0, e32, mf2, ta, ma    # SEW=32, LMUL=1/2
 ----
@@ -1345,7 +1345,7 @@ floating-point load/store 12-bit immediate field to provide further
 vector instruction encoding, with bit 25 holding the standard vector
 mask bit (see <<sec-vector-mask-encoding>>).
 
-include::images/wavedrom/vmem-format.adoc[]
+include::images/wavedrom/vmem-format.edn[]
 
 [cols="4,12"]
 |===
@@ -1549,19 +1549,19 @@ currently reserved.
 ==== Vector Unit-Stride Instructions
 
 ----
-    # Vector unit-stride loads and stores
+# Vector unit-stride loads and stores
 
-    # vd destination, rs1 base address, vm is mask encoding (v0.t or <missing>)
-    vle8.v    vd, (rs1), vm  #    8-bit unit-stride load
-    vle16.v   vd, (rs1), vm  #   16-bit unit-stride load
-    vle32.v   vd, (rs1), vm  #   32-bit unit-stride load
-    vle64.v   vd, (rs1), vm  #   64-bit unit-stride load
+# vd destination, rs1 base address, vm is mask encoding (v0.t or <missing>)
+vle8.v    vd, (rs1), vm  #    8-bit unit-stride load
+vle16.v   vd, (rs1), vm  #   16-bit unit-stride load
+vle32.v   vd, (rs1), vm  #   32-bit unit-stride load
+vle64.v   vd, (rs1), vm  #   64-bit unit-stride load
 
-    # vs3 store data, rs1 base address, vm is mask encoding (v0.t or <missing>)
-    vse8.v    vs3, (rs1), vm  #    8-bit unit-stride store
-    vse16.v   vs3, (rs1), vm  #   16-bit unit-stride store
-    vse32.v   vs3, (rs1), vm  #   32-bit unit-stride store
-    vse64.v   vs3, (rs1), vm  #   64-bit unit-stride store
+# vs3 store data, rs1 base address, vm is mask encoding (v0.t or <missing>)
+vse8.v    vs3, (rs1), vm  #    8-bit unit-stride store
+vse16.v   vs3, (rs1), vm  #   16-bit unit-stride store
+vse32.v   vs3, (rs1), vm  #   32-bit unit-stride store
+vse64.v   vs3, (rs1), vm  #   64-bit unit-stride store
 ----
 
 Additional unit-stride mask load and store instructions are
@@ -1572,11 +1572,11 @@ and the destination register is always written with a tail-agnostic
 policy.
 
 ----
-    # Vector unit-stride mask load
-    vlm.v vd, (rs1)   #  Load byte vector of length ceil(vl/8)
+# Vector unit-stride mask load
+vlm.v vd, (rs1)   #  Load byte vector of length ceil(vl/8)
 
-    # Vector unit-stride mask store
-    vsm.v vs3, (rs1)  #  Store byte vector of length ceil(vl/8)
+# Vector unit-stride mask store
+vsm.v vs3, (rs1)  #  Store byte vector of length ceil(vl/8)
 ----
 
 `vlm.v` and `vsm.v` are encoded with the same `width[2:0]`=0 encoding as
@@ -1602,19 +1602,19 @@ and also reduce the cost of mask spill/fill by reducing need to change
 ==== Vector Strided Instructions
 
 ----
-    # Vector strided loads and stores
+# Vector strided loads and stores
 
-    # vd destination, rs1 base address, rs2 byte stride
-    vlse8.v    vd, (rs1), rs2, vm  #    8-bit strided load
-    vlse16.v   vd, (rs1), rs2, vm  #   16-bit strided load
-    vlse32.v   vd, (rs1), rs2, vm  #   32-bit strided load
-    vlse64.v   vd, (rs1), rs2, vm  #   64-bit strided load
+# vd destination, rs1 base address, rs2 byte stride
+vlse8.v    vd, (rs1), rs2, vm  #    8-bit strided load
+vlse16.v   vd, (rs1), rs2, vm  #   16-bit strided load
+vlse32.v   vd, (rs1), rs2, vm  #   32-bit strided load
+vlse64.v   vd, (rs1), rs2, vm  #   64-bit strided load
 
-    # vs3 store data, rs1 base address, rs2 byte stride
-    vsse8.v    vs3, (rs1), rs2, vm  #    8-bit strided store
-    vsse16.v   vs3, (rs1), rs2, vm  #   16-bit strided store
-    vsse32.v   vs3, (rs1), rs2, vm  #   32-bit strided store
-    vsse64.v   vs3, (rs1), rs2, vm  #   64-bit strided store
+# vs3 store data, rs1 base address, rs2 byte stride
+vsse8.v    vs3, (rs1), rs2, vm  #    8-bit strided store
+vsse16.v   vs3, (rs1), rs2, vm  #   16-bit strided store
+vsse32.v   vs3, (rs1), rs2, vm  #   32-bit strided store
+vsse64.v   vs3, (rs1), rs2, vm  #   64-bit strided store
 ----
 
 Negative and zero strides are supported.
@@ -1648,36 +1648,35 @@ address are required, then an ordered indexed operation can be used.
 ==== Vector Indexed Instructions
 
 ----
-    # Vector indexed loads and stores
+# Vector indexed loads and stores
 
-    # Vector indexed-unordered load instructions
-    # vd destination, rs1 base address, vs2 byte offsets
-    vluxei8.v    vd, (rs1), vs2, vm  # unordered  8-bit indexed load of SEW data
-    vluxei16.v   vd, (rs1), vs2, vm  # unordered 16-bit indexed load of SEW data
-    vluxei32.v   vd, (rs1), vs2, vm  # unordered 32-bit indexed load of SEW data
-    vluxei64.v   vd, (rs1), vs2, vm  # unordered 64-bit indexed load of SEW data
+# Vector indexed-unordered load instructions
+# vd destination, rs1 base address, vs2 byte offsets
+vluxei8.v    vd, (rs1), vs2, vm  # unordered  8-bit indexed load of SEW data
+vluxei16.v   vd, (rs1), vs2, vm  # unordered 16-bit indexed load of SEW data
+vluxei32.v   vd, (rs1), vs2, vm  # unordered 32-bit indexed load of SEW data
+vluxei64.v   vd, (rs1), vs2, vm  # unordered 64-bit indexed load of SEW data
 
-    # Vector indexed-ordered load instructions
-    # vd destination, rs1 base address, vs2 byte offsets
-    vloxei8.v    vd, (rs1), vs2, vm  # ordered  8-bit indexed load of SEW data
-    vloxei16.v   vd, (rs1), vs2, vm  # ordered 16-bit indexed load of SEW data
-    vloxei32.v   vd, (rs1), vs2, vm  # ordered 32-bit indexed load of SEW data
-    vloxei64.v   vd, (rs1), vs2, vm  # ordered 64-bit indexed load of SEW data
+# Vector indexed-ordered load instructions
+# vd destination, rs1 base address, vs2 byte offsets
+vloxei8.v    vd, (rs1), vs2, vm  # ordered  8-bit indexed load of SEW data
+vloxei16.v   vd, (rs1), vs2, vm  # ordered 16-bit indexed load of SEW data
+vloxei32.v   vd, (rs1), vs2, vm  # ordered 32-bit indexed load of SEW data
+vloxei64.v   vd, (rs1), vs2, vm  # ordered 64-bit indexed load of SEW data
 
-    # Vector indexed-unordered store instructions
-    # vs3 store data, rs1 base address, vs2 byte offsets
-    vsuxei8.v   vs3, (rs1), vs2, vm # unordered  8-bit indexed store of SEW data
-    vsuxei16.v  vs3, (rs1), vs2, vm # unordered 16-bit indexed store of SEW data
-    vsuxei32.v  vs3, (rs1), vs2, vm # unordered 32-bit indexed store of SEW data
-    vsuxei64.v  vs3, (rs1), vs2, vm # unordered 64-bit indexed store of SEW data
-
-    # Vector indexed-ordered store instructions
-    # vs3 store data, rs1 base address, vs2 byte offsets
-    vsoxei8.v    vs3, (rs1), vs2, vm  # ordered  8-bit indexed store of SEW data
-    vsoxei16.v   vs3, (rs1), vs2, vm  # ordered 16-bit indexed store of SEW data
-    vsoxei32.v   vs3, (rs1), vs2, vm  # ordered 32-bit indexed store of SEW data
-    vsoxei64.v   vs3, (rs1), vs2, vm  # ordered 64-bit indexed store of SEW data
+# Vector indexed-unordered store instructions
+# vs3 store data, rs1 base address, vs2 byte offsets
+vsuxei8.v   vs3, (rs1), vs2, vm # unordered  8-bit indexed store of SEW data
+vsuxei16.v  vs3, (rs1), vs2, vm # unordered 16-bit indexed store of SEW data
+vsuxei32.v  vs3, (rs1), vs2, vm # unordered 32-bit indexed store of SEW data
+vsuxei64.v  vs3, (rs1), vs2, vm # unordered 64-bit indexed store of SEW data
 
+# Vector indexed-ordered store instructions
+# vs3 store data, rs1 base address, vs2 byte offsets
+vsoxei8.v    vs3, (rs1), vs2, vm  # ordered  8-bit indexed store of SEW data
+vsoxei16.v   vs3, (rs1), vs2, vm  # ordered 16-bit indexed store of SEW data
+vsoxei32.v   vs3, (rs1), vs2, vm  # ordered 32-bit indexed store of SEW data
+vsoxei64.v   vs3, (rs1), vs2, vm  # ordered 64-bit indexed store of SEW data
 ----
 
 NOTE: The assembler syntax for indexed loads and stores uses
@@ -1714,13 +1713,13 @@ operation will not be restarted due to a trap or vector-length
 trimming.
 
 ----
-    # Vector unit-stride fault-only-first loads
+# Vector unit-stride fault-only-first loads
 
-    # vd destination, rs1 base address, vm is mask encoding (v0.t or <missing>)
-    vle8ff.v    vd, (rs1), vm  #    8-bit unit-stride fault-only-first load
-    vle16ff.v   vd, (rs1), vm  #   16-bit unit-stride fault-only-first load
-    vle32ff.v   vd, (rs1), vm  #   32-bit unit-stride fault-only-first load
-    vle64ff.v   vd, (rs1), vm  #   64-bit unit-stride fault-only-first load
+# vd destination, rs1 base address, vm is mask encoding (v0.t or <missing>)
+vle8ff.v    vd, (rs1), vm  #    8-bit unit-stride fault-only-first load
+vle16ff.v   vd, (rs1), vm  #   16-bit unit-stride fault-only-first load
+vle32ff.v   vd, (rs1), vm  #   32-bit unit-stride fault-only-first load
+vle64ff.v   vd, (rs1), vm  #   64-bit unit-stride fault-only-first load
 ----
 
 ----
@@ -1837,14 +1836,14 @@ The assembler prefixes `vlseg`/`vsseg` are used for unit-stride
 segment loads and stores respectively.
 
 ----
-    # Format
-    vlseg<nf>e<eew>.v vd, (rs1), vm      # Unit-stride segment load template
-    vsseg<nf>e<eew>.v vs3, (rs1), vm     # Unit-stride segment store template
+# Format
+vlseg<nf>e<eew>.v vd, (rs1), vm      # Unit-stride segment load template
+vsseg<nf>e<eew>.v vs3, (rs1), vm     # Unit-stride segment store template
 
-    # Examples
-    vlseg8e8.v vd, (rs1), vm   # Load eight vector registers with eight byte fields.
+# Examples
+vlseg8e8.v vd, (rs1), vm   # Load eight vector registers with eight byte fields.
 
-    vsseg3e32.v vs3, (rs1), vm  # Store packed vector of 3*4-byte segments from vs3,vs3+1,vs3+2 to memory
+vsseg3e32.v vs3, (rs1), vm  # Store packed vector of 3*4-byte segments from vs3,vs3+1,vs3+2 to memory
 ----
 
 For loads, the `vd` register will hold the first field loaded from the
@@ -1852,27 +1851,27 @@ segment.  For stores, the `vs3` register is read to provide the first
 field to be stored to each segment.
 
 ----
-    # Example 1
-    # Memory structure holds packed RGB pixels (24-bit data structure, 8bpp)
-    vsetvli a1, t0, e8, ta, ma
-    vlseg3e8.v v8, (a0), vm
-    # v8 holds the red pixels
-    # v9 holds the green pixels
-    # v10 holds the blue pixels
+# Example 1
+# Memory structure holds packed RGB pixels (24-bit data structure, 8bpp)
+vsetvli a1, t0, e8, m1, ta, ma
+vlseg3e8.v v8, (a0), vm
+# v8 holds the red pixels
+# v9 holds the green pixels
+# v10 holds the blue pixels
 
-    # Example 2
-    # Memory structure holds complex values, 32b for real and 32b for imaginary
-    vsetvli a1, t0, e32, ta, ma
-    vlseg2e32.v v8, (a0), vm
-    # v8 holds real
-    # v9 holds imaginary
+# Example 2
+# Memory structure holds complex values, 32b for real and 32b for imaginary
+vsetvli a1, t0, e32, m1, ta, ma
+vlseg2e32.v v8, (a0), vm
+# v8 holds real
+# v9 holds imaginary
 ----
 
 There are also fault-only-first versions of the unit-stride instructions.
 
 ----
-    # Template for vector fault-only-first unit-stride segment loads.
-    vlseg<nf>e<eew>ff.v vd, (rs1),  vm    # Unit-stride fault-only-first segment loads
+# Template for vector fault-only-first unit-stride segment loads.
+vlseg<nf>e<eew>ff.v vd, (rs1),  vm    # Unit-stride fault-only-first segment loads
 ----
 
 For fault-only-first segment loads, if an exception is detected partway
@@ -1892,20 +1891,20 @@ GPR argument.
 NOTE: Negative and zero strides are supported.
 
 ----
-    # Format
-    vlsseg<nf>e<eew>.v vd, (rs1), rs2, vm          # Strided segment loads
-    vssseg<nf>e<eew>.v vs3, (rs1), rs2, vm         # Strided segment stores
+# Format
+vlsseg<nf>e<eew>.v vd, (rs1), rs2, vm          # Strided segment loads
+vssseg<nf>e<eew>.v vs3, (rs1), rs2, vm         # Strided segment stores
 
-    # Examples
-    vsetvli a1, t0, e8, ta, ma
-    vlsseg3e8.v v4, (x5), x6   # Load bytes at addresses x5+i*x6   into v4[i],
-                              #  and bytes at addresses x5+i*x6+1 into v5[i],
-                              #  and bytes at addresses x5+i*x6+2 into v6[i].
+# Examples
+vsetvli a1, t0, e8, m1, ta, ma
+vlsseg3e8.v v4, (x5), x6   # Load bytes at addresses x5+i*x6   into v4[i],
+                            #  and bytes at addresses x5+i*x6+1 into v5[i],
+                            #  and bytes at addresses x5+i*x6+2 into v6[i].
 
-    # Examples
-    vsetvli a1, t0, e32, ta, ma
-    vssseg2e32.v v2, (x5), x6   # Store words from v2[i] to address x5+i*x6
-                                #   and words from v3[i] to address x5+i*x6+4
+# Examples
+vsetvli a1, t0, e32, m1, ta, ma
+vssseg2e32.v v2, (x5), x6   # Store words from v2[i] to address x5+i*x6
+                            #   and words from v3[i] to address x5+i*x6+4
 ----
 
 Accesses to the fields within each segment can occur in any order,
@@ -1928,22 +1927,22 @@ EMUL=(EEW/SEW)*LMUL.
 The EMUL * NFIELDS {le} 8 constraint applies to the data vector register group.
 
 ----
-    # Format
-    vluxseg<nf>ei<eew>.v vd, (rs1), vs2, vm   # Indexed-unordered segment loads
-    vloxseg<nf>ei<eew>.v vd, (rs1), vs2, vm   # Indexed-ordered segment loads
-    vsuxseg<nf>ei<eew>.v vs3, (rs1), vs2, vm  # Indexed-unordered segment stores
-    vsoxseg<nf>ei<eew>.v vs3, (rs1), vs2, vm  # Indexed-ordered segment stores
+# Format
+vluxseg<nf>ei<eew>.v vd, (rs1), vs2, vm   # Indexed-unordered segment loads
+vloxseg<nf>ei<eew>.v vd, (rs1), vs2, vm   # Indexed-ordered segment loads
+vsuxseg<nf>ei<eew>.v vs3, (rs1), vs2, vm  # Indexed-unordered segment stores
+vsoxseg<nf>ei<eew>.v vs3, (rs1), vs2, vm  # Indexed-ordered segment stores
 
-    # Examples
-    vsetvli a1, t0, e8, ta, ma
-    vluxseg3ei8.v v4, (x5), v3   # Load bytes at addresses x5+v3[i]   into v4[i],
-                                 #  and bytes at addresses x5+v3[i]+1 into v5[i],
-                                 #  and bytes at addresses x5+v3[i]+2 into v6[i].
+# Examples
+vsetvli a1, t0, e8, m1, ta, ma
+vluxseg3ei8.v v4, (x5), v3   # Load bytes at addresses x5+v3[i]   into v4[i],
+                                #  and bytes at addresses x5+v3[i]+1 into v5[i],
+                                #  and bytes at addresses x5+v3[i]+2 into v6[i].
 
-    # Examples
-    vsetvli a1, t0, e32, ta, ma
-    vsuxseg2ei32.v v2, (x5), v5   # Store words from v2[i] to address x5+v5[i]
-                                  #   and words from v3[i] to address x5+v5[i]+4
+# Examples
+vsetvli a1, t0, e32, m1, ta, ma
+vsuxseg2ei32.v v2, (x5), v5   # Store words from v2[i] to address x5+v5[i]
+                                #   and words from v3[i] to address x5+v5[i]+4
 ----
 
 For vector indexed segment loads, the destination vector register
@@ -2060,39 +2059,39 @@ environments can mandate the minimum alignment requirements to support
 an ABI.
 
 ----
-   # Format of whole register load and store instructions.
-   vl1r.v v3, (a0)       # Pseudoinstruction equal to vl1re8.v
+# Format of whole register load and store instructions.
+vl1r.v v3, (a0)       # Pseudoinstruction equal to vl1re8.v
 
-   vl1re8.v    v3, (a0)  # Load v3 with VLEN/8 bytes held at address in a0
-   vl1re16.v   v3, (a0)  # Load v3 with VLEN/16 halfwords held at address in a0
-   vl1re32.v   v3, (a0)  # Load v3 with VLEN/32 words held at address in a0
-   vl1re64.v   v3, (a0)  # Load v3 with VLEN/64 doublewords held at address in a0
+vl1re8.v    v3, (a0)  # Load v3 with VLEN/8 bytes held at address in a0
+vl1re16.v   v3, (a0)  # Load v3 with VLEN/16 halfwords held at address in a0
+vl1re32.v   v3, (a0)  # Load v3 with VLEN/32 words held at address in a0
+vl1re64.v   v3, (a0)  # Load v3 with VLEN/64 doublewords held at address in a0
 
-   vl2r.v v2, (a0)       # Pseudoinstruction equal to vl2re8.v
+vl2r.v v2, (a0)       # Pseudoinstruction equal to vl2re8.v
 
-   vl2re8.v    v2, (a0)  # Load v2-v3 with 2*VLEN/8 bytes from address in a0
-   vl2re16.v   v2, (a0)  # Load v2-v3 with 2*VLEN/16 halfwords held at address in a0
-   vl2re32.v   v2, (a0)  # Load v2-v3 with 2*VLEN/32 words held at address in a0
-   vl2re64.v   v2, (a0)  # Load v2-v3 with 2*VLEN/64 doublewords held at address in a0
+vl2re8.v    v2, (a0)  # Load v2-v3 with 2*VLEN/8 bytes from address in a0
+vl2re16.v   v2, (a0)  # Load v2-v3 with 2*VLEN/16 halfwords held at address in a0
+vl2re32.v   v2, (a0)  # Load v2-v3 with 2*VLEN/32 words held at address in a0
+vl2re64.v   v2, (a0)  # Load v2-v3 with 2*VLEN/64 doublewords held at address in a0
 
-   vl4r.v v4, (a0)       # Pseudoinstruction equal to vl4re8.v
+vl4r.v v4, (a0)       # Pseudoinstruction equal to vl4re8.v
 
-   vl4re8.v    v4, (a0)  # Load v4-v7 with 4*VLEN/8 bytes from address in a0
-   vl4re16.v   v4, (a0)
-   vl4re32.v   v4, (a0)
-   vl4re64.v   v4, (a0)
+vl4re8.v    v4, (a0)  # Load v4-v7 with 4*VLEN/8 bytes from address in a0
+vl4re16.v   v4, (a0)
+vl4re32.v   v4, (a0)
+vl4re64.v   v4, (a0)
 
-   vl8r.v v8, (a0)       # Pseudoinstruction equal to vl8re8.v
+vl8r.v v8, (a0)       # Pseudoinstruction equal to vl8re8.v
 
-   vl8re8.v    v8, (a0)  # Load v8-v15 with 8*VLEN/8 bytes from address in a0
-   vl8re16.v   v8, (a0)
-   vl8re32.v   v8, (a0)
-   vl8re64.v   v8, (a0)
+vl8re8.v    v8, (a0)  # Load v8-v15 with 8*VLEN/8 bytes from address in a0
+vl8re16.v   v8, (a0)
+vl8re32.v   v8, (a0)
+vl8re64.v   v8, (a0)
 
-   vs1r.v v3, (a1)      # Store v3 to address in a1
-   vs2r.v v2, (a1)      # Store v2-v3 to address in a1
-   vs4r.v v4, (a1)      # Store v4-v7 to address in a1
-   vs8r.v v8, (a1)      # Store v8-v15 to address in a1
+vs1r.v v3, (a1)      # Store v3 to address in a1
+vs2r.v v2, (a1)      # Store v2-v3 to address in a1
+vs4r.v v4, (a1)      # Store v4-v7 to address in a1
+vs8r.v v8, (a1)      # Store v8-v15 to address in a1
 ----
 
 NOTE: Implementations should raise illegal instruction exceptions on
@@ -2109,10 +2108,10 @@ following vector instruction needs a new SEW/LMUL. So, in best case
 only two instructions (of which only one performs vector operations) are needed to synthesize the effect of the
 dedicated instruction:
 ----
-  csrr t0, vl                        # Save current vl (potentially not needed)
-  vsetvli t1, x0, e8, m8, ta, ma     # Maximum VLMAX
-  vlm.v v0, (a0)                     # Load mask register
-  vsetvli x0, t0, <new type>         # Restore vl (potentially already present)
+csrr t0, vl                        # Save current vl (potentially not needed)
+vsetvli t1, x0, e8, m8, ta, ma     # Maximum VLMAX
+vlm.v v0, (a0)                     # Load mask register
+vsetvli x0, t0, <new type>         # Restore vl (potentially already present)
 ----
 
 === Vector Memory Alignment Constraints
@@ -2172,7 +2171,7 @@ The vector arithmetic instructions use a new major opcode (OP-V =
 1010111~2~) which neighbors OP-FP.  The three-bit `funct3` field is
 used to define sub-categories of vector instructions.
 
-include::images/wavedrom/valu-format.adoc[]
+include::images/wavedrom/valu-format.edn[]
 
 [[sec-arithmetic-encoding]]
 ==== Vector Arithmetic Instruction encoding
@@ -2306,7 +2305,7 @@ The first vector register group operand can be either single or
 double-width.
 
 ----
-Assembly syntax pattern for vector widening arithmetic instructions
+# Assembly syntax pattern for vector widening arithmetic instructions
 
 # Double-width result, two single-width sources: 2*SEW = SEW op SEW
 vwop.vv  vd, vs2, vs1, vm  # integer vector-vector      vd[i] = vs2[i] op vs1[i]
@@ -2526,10 +2525,10 @@ instructions with unchanged inputs, destructive accumulations will
 require an additional move to obtain correct results.
 
 ----
-  # Example multi-word arithmetic sequence, accumulating into v4
-  vmadc.vvm v1, v4, v8, v0  # Get carry into temp register v1
-  vadc.vvm v4, v4, v8, v0   # Calc new sum
-  vmmv.m v0, v1             # Move temp carry into v0 for next word
+# Example multi-word arithmetic sequence, accumulating into v4
+vmadc.vvm v1, v4, v8, v0  # Get carry into temp register v1
+vadc.vvm v4, v4, v8, v0   # Calc new sum
+vmmv.m v0, v1             # Move temp carry into v0 for next word
 ----
 
 The subtract with borrow instruction `vsbc` performs the equivalent
@@ -2537,27 +2536,27 @@ function to support long word arithmetic for subtraction.  There are
 no subtract with immediate instructions.
 
 ----
- # Produce difference with borrow.
+# Produce difference with borrow.
 
- # vd[i] = vs2[i] - vs1[i] - v0.mask[i]
- vsbc.vvm   vd, vs2, vs1, v0  # Vector-vector
+# vd[i] = vs2[i] - vs1[i] - v0.mask[i]
+vsbc.vvm   vd, vs2, vs1, v0  # Vector-vector
 
- # vd[i] = vs2[i] - x[rs1] - v0.mask[i]
- vsbc.vxm   vd, vs2, rs1, v0  # Vector-scalar
+# vd[i] = vs2[i] - x[rs1] - v0.mask[i]
+vsbc.vxm   vd, vs2, rs1, v0  # Vector-scalar
 
- # Produce borrow out in mask register format
+# Produce borrow out in mask register format
 
- # vd.mask[i] = borrow_out(vs2[i] - vs1[i] - v0.mask[i])
- vmsbc.vvm   vd, vs2, vs1, v0  # Vector-vector
+# vd.mask[i] = borrow_out(vs2[i] - vs1[i] - v0.mask[i])
+vmsbc.vvm   vd, vs2, vs1, v0  # Vector-vector
 
- # vd.mask[i] = borrow_out(vs2[i] - x[rs1] - v0.mask[i])
- vmsbc.vxm   vd, vs2, rs1, v0  # Vector-scalar
+# vd.mask[i] = borrow_out(vs2[i] - x[rs1] - v0.mask[i])
+vmsbc.vxm   vd, vs2, rs1, v0  # Vector-scalar
 
- # vd.mask[i] = borrow_out(vs2[i] - vs1[i])
- vmsbc.vv    vd, vs2, vs1      # Vector-vector, no borrow-in
+# vd.mask[i] = borrow_out(vs2[i] - vs1[i])
+vmsbc.vv    vd, vs2, vs1      # Vector-vector, no borrow-in
 
- # vd.mask[i] = borrow_out(vs2[i] - x[rs1])
- vmsbc.vx    vd, vs2, rs1      # Vector-scalar, no borrow-in
+# vd.mask[i] = borrow_out(vs2[i] - x[rs1])
+vmsbc.vx    vd, vs2, rs1      # Vector-scalar, no borrow-in
 ----
 
 For `vmsbc`, the borrow is defined to be 1 iff the difference, prior to
@@ -2807,9 +2806,9 @@ masked va >= x, any vd
 Compares effectively AND in the mask under a mask-undisturbed policy if the destination register is `v0`, e.g.,
 
 ----
-    # (a < b) && (b < c) in two instructions when mask-undisturbed
-    vmslt.vv    v0, va, vb        # All body elements written
-    vmslt.vv    v0, vb, vc, v0.t  # Only update at set mask
+# (a < b) && (b < c) in two instructions when mask-undisturbed
+vmslt.vv    v0, va, vb        # All body elements written
+vmslt.vv    v0, vb, vc, v0.t  # Only update at set mask
 ----
 
 Compares write mask registers, and so always operate under a
@@ -2883,21 +2882,21 @@ standard scalar integer multiply/divides, with the same results for
 extreme inputs.
 
 ----
-    # Unsigned divide.
-    vdivu.vv vd, vs2, vs1, vm   # Vector-vector
-    vdivu.vx vd, vs2, rs1, vm   # vector-scalar
+# Unsigned divide.
+vdivu.vv vd, vs2, vs1, vm   # Vector-vector
+vdivu.vx vd, vs2, rs1, vm   # vector-scalar
 
-    # Signed divide
-    vdiv.vv vd, vs2, vs1, vm   # Vector-vector
-    vdiv.vx vd, vs2, rs1, vm   # vector-scalar
+# Signed divide
+vdiv.vv vd, vs2, vs1, vm   # Vector-vector
+vdiv.vx vd, vs2, rs1, vm   # vector-scalar
 
-    # Unsigned remainder
-    vremu.vv vd, vs2, vs1, vm   # Vector-vector
-    vremu.vx vd, vs2, rs1, vm   # vector-scalar
+# Unsigned remainder
+vremu.vv vd, vs2, vs1, vm   # Vector-vector
+vremu.vx vd, vs2, rs1, vm   # vector-scalar
 
-    # Signed remainder
-    vrem.vv vd, vs2, vs1, vm   # Vector-vector
-    vrem.vx vd, vs2, rs1, vm   # vector-scalar
+# Signed remainder
+vrem.vv vd, vs2, vs1, vm   # Vector-vector
+vrem.vx vd, vs2, rs1, vm   # vector-scalar
 ----
 
 NOTE: The decision to include integer divide and remainder was
@@ -3188,14 +3187,14 @@ used to control the right shift amount, which provides the scaling.
 ----
 # Narrowing unsigned clip
 #                                SEW                            2*SEW   SEW
- vnclipu.wv vd, vs2, vs1, vm  # vd[i] = clip(roundoff_unsigned(vs2[i], vs1[i]))
- vnclipu.wx vd, vs2, rs1, vm  # vd[i] = clip(roundoff_unsigned(vs2[i], x[rs1]))
- vnclipu.wi vd, vs2, uimm, vm # vd[i] = clip(roundoff_unsigned(vs2[i], uimm))
+vnclipu.wv vd, vs2, vs1, vm  # vd[i] = clip(roundoff_unsigned(vs2[i], vs1[i]))
+vnclipu.wx vd, vs2, rs1, vm  # vd[i] = clip(roundoff_unsigned(vs2[i], x[rs1]))
+vnclipu.wi vd, vs2, uimm, vm # vd[i] = clip(roundoff_unsigned(vs2[i], uimm))
 
 # Narrowing signed clip
- vnclip.wv vd, vs2, vs1, vm   # vd[i] = clip(roundoff_signed(vs2[i], vs1[i]))
- vnclip.wx vd, vs2, rs1, vm   # vd[i] = clip(roundoff_signed(vs2[i], x[rs1]))
- vnclip.wi vd, vs2, uimm, vm  # vd[i] = clip(roundoff_signed(vs2[i], uimm))
+vnclip.wv vd, vs2, vs1, vm   # vd[i] = clip(roundoff_signed(vs2[i], vs1[i]))
+vnclip.wx vd, vs2, rs1, vm   # vd[i] = clip(roundoff_signed(vs2[i], x[rs1]))
+vnclip.wi vd, vs2, uimm, vm  # vd[i] = clip(roundoff_signed(vs2[i], uimm))
 ----
 
 For `vnclipu`/`vnclip`, the rounding mode is specified in the `vxrm`
@@ -3273,14 +3272,14 @@ elements do not set FP exception flags.
 ==== Vector Single-Width Floating-Point Add/Subtract Instructions
 
 ----
-    # Floating-point add
-    vfadd.vv vd, vs2, vs1, vm   # Vector-vector
-    vfadd.vf vd, vs2, rs1, vm   # vector-scalar
+# Floating-point add
+vfadd.vv vd, vs2, vs1, vm   # Vector-vector
+vfadd.vf vd, vs2, rs1, vm   # vector-scalar
 
-    # Floating-point subtract
-    vfsub.vv vd, vs2, vs1, vm   # Vector-vector
-    vfsub.vf vd, vs2, rs1, vm   # Vector-scalar vd[i] = vs2[i] - f[rs1]
-    vfrsub.vf vd, vs2, rs1, vm  # Scalar-vector vd[i] = f[rs1] - vs2[i]
+# Floating-point subtract
+vfsub.vv vd, vs2, vs1, vm   # Vector-vector
+vfsub.vf vd, vs2, rs1, vm   # Vector-scalar vd[i] = vs2[i] - f[rs1]
+vfrsub.vf vd, vs2, rs1, vm  # Scalar-vector vd[i] = f[rs1] - vs2[i]
 ----
 
 ==== Vector Widening Floating-Point Add/Subtract Instructions
@@ -3302,16 +3301,16 @@ vfwsub.wf  vd, vs2, rs1, vm  # vector-scalar
 ==== Vector Single-Width Floating-Point Multiply/Divide Instructions
 
 ----
-    # Floating-point multiply
-    vfmul.vv vd, vs2, vs1, vm   # Vector-vector
-    vfmul.vf vd, vs2, rs1, vm   # vector-scalar
+# Floating-point multiply
+vfmul.vv vd, vs2, vs1, vm   # Vector-vector
+vfmul.vf vd, vs2, rs1, vm   # vector-scalar
 
-    # Floating-point divide
-    vfdiv.vv vd, vs2, vs1, vm   # Vector-vector
-    vfdiv.vf vd, vs2, rs1, vm   # vector-scalar
+# Floating-point divide
+vfdiv.vv vd, vs2, vs1, vm   # Vector-vector
+vfdiv.vf vd, vs2, rs1, vm   # vector-scalar
 
-    # Reverse floating-point divide vector = scalar / vector
-    vfrdiv.vf vd, vs2, rs1, vm  # scalar-vector, vd[i] = f[rs1]/vs2[i]
+# Reverse floating-point divide vector = scalar / vector
+vfrdiv.vf vd, vs2, rs1, vm  # scalar-vector, vd[i] = f[rs1]/vs2[i]
 ----
 
 ==== Vector Widening Floating-Point Multiply
@@ -3396,15 +3395,15 @@ vfwnmsac.vf vd, rs1, vs2, vm   # vd[i] = -(f[rs1] * vs2[i]) + vd[i]
 This is a unary vector-vector instruction.
 
 ----
-    # Floating-point square root
-    vfsqrt.v vd, vs2, vm   # Vector-vector square root
+# Floating-point square root
+vfsqrt.v vd, vs2, vm   # Vector-vector square root
 ----
 
 ==== Vector Floating-Point Reciprocal Square-Root Estimate Instruction
 
 ----
-    # Floating-point reciprocal square-root estimate to 7 bits.
-    vfrsqrt7.v vd, vs2, vm
+# Floating-point reciprocal square-root estimate to 7 bits.
+vfrsqrt7.v vd, vs2, vm
 ----
 
 This is a unary vector-vector instruction that returns an estimate of
@@ -3460,7 +3459,7 @@ The following table gives the seven MSBs of the output significand as a
 function of the LSB of the normalized input exponent and the six MSBs of the
 normalized input significand; the other bits of the output significand are zero.
 
-include::images/wavedrom/vfrsqrt7.adoc[]
+include::images/wavedrom/vfrsqrt7.edn[]
 
 NOTE: For example, when SEW=32, vfrsqrt7(0x00718abc ({approx} 1.043e-38)) = 0x5f080000 ({approx} 9.800e18), and vfrsqrt7(0x7f765432 ({approx} 3.274e38)) = 0x1f820000 ({approx} 5.506e-20).
 
@@ -3472,8 +3471,8 @@ with greater estimate accuracy.
 ==== Vector Floating-Point Reciprocal Estimate Instruction
 
 ----
-    # Floating-point reciprocal estimate to 7 bits.
-    vfrec7.v vd, vs2, vm
+# Floating-point reciprocal estimate to 7 bits.
+vfrec7.v vd, vs2, vm
 ----
 
 NOTE: An earlier draft version had used the assembler name `vfrece7`
@@ -3547,7 +3546,7 @@ The following table gives the seven MSBs of the normalized output significand
 as a function of the seven MSBs of the normalized input significand; the other
 bits of the normalized output significand are zero.
 
-include::images/wavedrom/vfrec7.adoc[]
+include::images/wavedrom/vfrec7.edn[]
 
 If the normalized output exponent is 0 or -1, the result is subnormal: the
 output exponent is 0, and the output significand is given by concatenating
@@ -3572,13 +3571,13 @@ in version 2.2 of the RISC-V F/D/Q extension: they perform the `minimumNumber`
 or `maximumNumber` operation on active elements.
 
 ----
-    # Floating-point minimum
-    vfmin.vv vd, vs2, vs1, vm   # Vector-vector
-    vfmin.vf vd, vs2, rs1, vm   # vector-scalar
+# Floating-point minimum
+vfmin.vv vd, vs2, vs1, vm   # Vector-vector
+vfmin.vf vd, vs2, rs1, vm   # vector-scalar
 
-    # Floating-point maximum
-    vfmax.vv vd, vs2, vs1, vm   # Vector-vector
-    vfmax.vf vd, vs2, rs1, vm   # vector-scalar
+# Floating-point maximum
+vfmax.vv vd, vs2, vs1, vm   # Vector-vector
+vfmax.vf vd, vs2, rs1, vm   # vector-scalar
 ----
 
 ==== Vector Floating-Point Sign-Injection Instructions
@@ -3587,14 +3586,14 @@ Vector versions of the scalar sign-injection instructions.  The result
 takes all bits except the sign bit from the vector `vs2` operands.
 
 ----
-    vfsgnj.vv vd, vs2, vs1, vm   # Vector-vector
-    vfsgnj.vf vd, vs2, rs1, vm   # vector-scalar
+vfsgnj.vv vd, vs2, vs1, vm   # Vector-vector
+vfsgnj.vf vd, vs2, rs1, vm   # vector-scalar
 
-    vfsgnjn.vv vd, vs2, vs1, vm  # Vector-vector
-    vfsgnjn.vf vd, vs2, rs1, vm  # vector-scalar
+vfsgnjn.vv vd, vs2, vs1, vm  # Vector-vector
+vfsgnjn.vf vd, vs2, rs1, vm  # vector-scalar
 
-    vfsgnjx.vv vd, vs2, vs1, vm  # Vector-vector
-    vfsgnjx.vf vd, vs2, rs1, vm  # vector-scalar
+vfsgnjx.vv vd, vs2, vs1, vm  # Vector-vector
+vfsgnjx.vf vd, vs2, rs1, vm  # vector-scalar
 ----
 
 NOTE: A vector of floating-point values can be negated using a
@@ -3626,27 +3625,27 @@ operand is NaN, whereas the other compares write 0 when either operand
 is NaN.
 
 ----
-    # Compare equal
-    vmfeq.vv vd, vs2, vs1, vm  # Vector-vector
-    vmfeq.vf vd, vs2, rs1, vm  # vector-scalar
+# Compare equal
+vmfeq.vv vd, vs2, vs1, vm  # Vector-vector
+vmfeq.vf vd, vs2, rs1, vm  # vector-scalar
 
-    # Compare not equal
-    vmfne.vv vd, vs2, vs1, vm  # Vector-vector
-    vmfne.vf vd, vs2, rs1, vm  # vector-scalar
+# Compare not equal
+vmfne.vv vd, vs2, vs1, vm  # Vector-vector
+vmfne.vf vd, vs2, rs1, vm  # vector-scalar
 
-    # Compare less than
-    vmflt.vv vd, vs2, vs1, vm  # Vector-vector
-    vmflt.vf vd, vs2, rs1, vm  # vector-scalar
+# Compare less than
+vmflt.vv vd, vs2, vs1, vm  # Vector-vector
+vmflt.vf vd, vs2, rs1, vm  # vector-scalar
 
-    # Compare less than or equal
-    vmfle.vv vd, vs2, vs1, vm  # Vector-vector
-    vmfle.vf vd, vs2, rs1, vm  # vector-scalar
+# Compare less than or equal
+vmfle.vv vd, vs2, vs1, vm  # Vector-vector
+vmfle.vf vd, vs2, rs1, vm  # vector-scalar
 
-    # Compare greater than
-    vmfgt.vf vd, vs2, rs1, vm  # vector-scalar
+# Compare greater than
+vmfgt.vf vd, vs2, rs1, vm  # vector-scalar
 
-    # Compare greater than or equal
-    vmfge.vf vd, vs2, rs1, vm  # vector-scalar
+# Compare greater than or equal
+vmfge.vf vd, vs2, rs1, vm  # vector-scalar
 ----
 
 ----
@@ -3675,11 +3674,11 @@ the comparand is a non-NaN constant, the middle two instructions can be
 omitted.
 
 ----
-    # Example of implementing isgreater()
-    vmfeq.vv v0, va, va        # Only set where A is not NaN.
-    vmfeq.vv v1, vb, vb        # Only set where B is not NaN.
-    vmand.mm v0, v0, v1        # Only set where A and B are ordered,
-    vmfgt.vv v0, va, vb, v0.t  #  so only set flags on ordered values.
+# Example of implementing isgreater()
+vmfeq.vv v0, va, va        # Only set where A is not NaN.
+vmfeq.vv v1, vb, vb        # Only set where B is not NaN.
+vmand.mm v0, v0, v1        # Only set where A and B are ordered,
+vmfgt.vv v0, va, vb, v0.t  #  so only set flags on ordered values.
 ----
 
 NOTE: In the above sequence, it is tempting to mask the second `vmfeq`
@@ -3694,7 +3693,7 @@ This is a unary vector-vector instruction that operates in the same
 way as the scalar classify instruction.
 
 ----
-    vfclass.v vd, vs2, vm   # Vector-vector
+vfclass.v vd, vs2, vm   # Vector-vector
 ----
 
 The 10-bit mask produced by this instruction is placed in the
@@ -3885,15 +3884,15 @@ All operands and results of single-width reduction instructions have
 the same SEW width.  Overflows wrap around on arithmetic sums.
 
 ----
-    # Simple reductions, where [*] denotes all active elements:
-    vredsum.vs  vd, vs2, vs1, vm   # vd[0] =  sum( vs1[0] , vs2[*] )
-    vredmaxu.vs vd, vs2, vs1, vm   # vd[0] = maxu( vs1[0] , vs2[*] )
-    vredmax.vs  vd, vs2, vs1, vm   # vd[0] =  max( vs1[0] , vs2[*] )
-    vredminu.vs vd, vs2, vs1, vm   # vd[0] = minu( vs1[0] , vs2[*] )
-    vredmin.vs  vd, vs2, vs1, vm   # vd[0] =  min( vs1[0] , vs2[*] )
-    vredand.vs  vd, vs2, vs1, vm   # vd[0] =  and( vs1[0] , vs2[*] )
-    vredor.vs   vd, vs2, vs1, vm   # vd[0] =   or( vs1[0] , vs2[*] )
-    vredxor.vs  vd, vs2, vs1, vm   # vd[0] =  xor( vs1[0] , vs2[*] )
+# Simple reductions, where [*] denotes all active elements:
+vredsum.vs  vd, vs2, vs1, vm   # vd[0] =  sum( vs1[0] , vs2[*] )
+vredmaxu.vs vd, vs2, vs1, vm   # vd[0] = maxu( vs1[0] , vs2[*] )
+vredmax.vs  vd, vs2, vs1, vm   # vd[0] =  max( vs1[0] , vs2[*] )
+vredminu.vs vd, vs2, vs1, vm   # vd[0] = minu( vs1[0] , vs2[*] )
+vredmin.vs  vd, vs2, vs1, vm   # vd[0] =  min( vs1[0] , vs2[*] )
+vredand.vs  vd, vs2, vs1, vm   # vd[0] =  and( vs1[0] , vs2[*] )
+vredor.vs   vd, vs2, vs1, vm   # vd[0] =   or( vs1[0] , vs2[*] )
+vredxor.vs  vd, vs2, vs1, vm   # vd[0] =  xor( vs1[0] , vs2[*] )
 ----
 
 [[sec-vector-integer-reduce-widen]]
@@ -3909,23 +3908,22 @@ elements before summing them.
 For both `vwredsumu.vs` and `vwredsum.vs`, overflows wrap around.
 
 ----
-    # Unsigned sum reduction into double-width accumulator
-    vwredsumu.vs vd, vs2, vs1, vm   # 2*SEW = 2*SEW + sum(zero-extend(SEW))
+# Unsigned sum reduction into double-width accumulator
+vwredsumu.vs vd, vs2, vs1, vm   # 2*SEW = 2*SEW + sum(zero-extend(SEW))
 
-    # Signed sum reduction into double-width accumulator
-    vwredsum.vs  vd, vs2, vs1, vm   # 2*SEW = 2*SEW + sum(sign-extend(SEW))
+# Signed sum reduction into double-width accumulator
+vwredsum.vs  vd, vs2, vs1, vm   # 2*SEW = 2*SEW + sum(sign-extend(SEW))
 ----
 
 [[sec-vector-float-reduce]]
 ==== Vector Single-Width Floating-Point Reduction Instructions
 
 ----
-    # Simple reductions.
-    vfredosum.vs vd, vs2, vs1, vm # Ordered sum
-    vfredusum.vs vd, vs2, vs1, vm # Unordered sum
-    vfredmax.vs  vd, vs2, vs1, vm # Maximum value
-    vfredmin.vs  vd, vs2, vs1, vm # Minimum value
-
+# Simple reductions.
+vfredosum.vs vd, vs2, vs1, vm # Ordered sum
+vfredusum.vs vd, vs2, vs1, vm # Unordered sum
+vfredmax.vs  vd, vs2, vs1, vm # Maximum value
+vfredmin.vs  vd, vs2, vs1, vm # Minimum value
 ----
 
 NOTE: Older assembler mnemonic `vfredsum` is retained as alias for `vfredusum`.
@@ -4058,14 +4056,14 @@ Mask elements past `vl`, the tail elements, are
 always updated with a tail-agnostic policy.
 
 ----
-    vmand.mm vd, vs2, vs1   # vd.mask[i] =   vs2.mask[i] &&  vs1.mask[i]
-    vmnand.mm vd, vs2, vs1  # vd.mask[i] = !(vs2.mask[i] &&  vs1.mask[i])
-    vmandn.mm vd, vs2, vs1  # vd.mask[i] =   vs2.mask[i] && !vs1.mask[i]
-    vmxor.mm  vd, vs2, vs1  # vd.mask[i] =   vs2.mask[i] ^^  vs1.mask[i]
-    vmor.mm  vd, vs2, vs1   # vd.mask[i] =   vs2.mask[i] ||  vs1.mask[i]
-    vmnor.mm  vd, vs2, vs1  # vd.mask[i] = !(vs2.mask[i] ||  vs1.mask[i])
-    vmorn.mm  vd, vs2, vs1  # vd.mask[i] =   vs2.mask[i] || !vs1.mask[i]
-    vmxnor.mm vd, vs2, vs1  # vd.mask[i] = !(vs2.mask[i] ^^  vs1.mask[i])
+vmand.mm vd, vs2, vs1   # vd.mask[i] =   vs2.mask[i] &&  vs1.mask[i]
+vmnand.mm vd, vs2, vs1  # vd.mask[i] = !(vs2.mask[i] &&  vs1.mask[i])
+vmandn.mm vd, vs2, vs1  # vd.mask[i] =   vs2.mask[i] && !vs1.mask[i]
+vmxor.mm  vd, vs2, vs1  # vd.mask[i] =   vs2.mask[i] ^^  vs1.mask[i]
+vmor.mm  vd, vs2, vs1   # vd.mask[i] =   vs2.mask[i] ||  vs1.mask[i]
+vmnor.mm  vd, vs2, vs1  # vd.mask[i] = !(vs2.mask[i] ||  vs1.mask[i])
+vmorn.mm  vd, vs2, vs1  # vd.mask[i] =   vs2.mask[i] || !vs1.mask[i]
+vmxnor.mm vd, vs2, vs1  # vd.mask[i] = !(vs2.mask[i] ^^  vs1.mask[i])
 ----
 
 NOTE: The previous assembler mnemonics `vmandnot` and `vmornot` have
@@ -4076,10 +4074,10 @@ mnemonics can be retained as assembler aliases for compatibility.
 Several assembler pseudoinstructions are defined as shorthand for
 common uses of mask logical operations:
 ----
-    vmmv.m vd, vs  => vmand.mm vd, vs, vs   # Copy mask register
-    vmclr.m vd     => vmxor.mm vd, vd, vd   # Clear mask register
-    vmset.m vd     => vmxnor.mm vd, vd, vd  # Set mask register
-    vmnot.m vd, vs => vmnand.mm vd, vs, vs  # Invert bits
+vmmv.m vd, vs  => vmand.mm vd, vs, vs   # Copy mask register
+vmclr.m vd     => vmxor.mm vd, vd, vd   # Clear mask register
+vmset.m vd     => vmxnor.mm vd, vd, vd  # Set mask register
+vmnot.m vd, vs => vmnand.mm vd, vs, vs  # Invert bits
 ----
 
 NOTE: The `vmmv.m` instruction was previously called `vmcpy.m`, but
@@ -4132,7 +4130,7 @@ use.
 ==== Vector count population in mask `vcpop.m`
 
 ----
-    vcpop.m rd, vs2, vm
+vcpop.m rd, vs2, vm
 ----
 
 NOTE: This instruction previously had the assembler mnemonic `vpopc.m`
@@ -4151,7 +4149,7 @@ The operation can be performed under a mask, in which case only the
 masked elements are counted.
 
 ----
- vcpop.m rd, vs2, v0.t # x[rd] = sum_i ( vs2.mask[i] && v0.mask[i] )
+vcpop.m rd, vs2, v0.t # x[rd] = sum_i ( vs2.mask[i] && v0.mask[i] )
 ----
 
 The `vcpop.m` instruction writes `x[rd]` even if `vl`=0 (with the
@@ -4164,7 +4162,7 @@ Traps on `vcpop.m` are always reported with a `vstart` of 0.  The
 ==== `vfirst` find-first-set mask bit
 
 ----
-    vfirst.m rd, vs2, vm
+vfirst.m rd, vs2, vm
 ----
 
 The `vfirst` instruction finds the lowest-numbered active element of
@@ -4356,27 +4354,27 @@ The `viota.m` instruction can be combined with memory scatter
 instructions (indexed stores) to perform vector compress functions.
 
 ----
-    # Compact non-zero elements from input memory array to output memory array
-    #
-    # size_t compact_non_zero(size_t n, const int* in, int* out)
-    # {
-    #   size_t i;
-    #   size_t count = 0;
-    #   int *p = out;
-    #
-    #   for (i=0; i<n; i++)
-    #   {
-    #       const int v = *in++;
-    #       if (v != 0)
-    #           *p++ = v;
-    #   }
-    #
-    #   return (size_t) (p - out);
-    # }
-    #
-    # a0 = n
-    # a1 = &in
-    # a2 = &out
+# Compact non-zero elements from input memory array to output memory array
+#
+# size_t compact_non_zero(size_t n, const int* in, int* out)
+# {
+#   size_t i;
+#   size_t count = 0;
+#   int *p = out;
+#
+#   for (i=0; i<n; i++)
+#   {
+#       const int v = *in++;
+#       if (v != 0)
+#           *p++ = v;
+#   }
+#
+#   return (size_t) (p - out);
+# }
+#
+# a0 = n
+# a1 = &in
+# a2 = &out
 
 compact_non_zero:
     li a6, 0                      # Clear count of non-zero elements
@@ -4406,7 +4404,7 @@ The `vid.v` instruction writes each element's index to the
 destination vector register group, from 0 to `vl`-1.
 
 ----
-    vid.v vd, vm  # Write element ID to destination.
+vid.v vd, vm  # Write element ID to destination.
 ----
 
 The instruction can be masked.  Masking does not change the
@@ -4516,8 +4514,8 @@ undisturbed/agnostic policy is followed for inactive elements.
 ===== Vector Slideup Instructions
 
 ----
- vslideup.vx vd, vs2, rs1, vm        # vd[i+x[rs1]] = vs2[i]
- vslideup.vi vd, vs2, uimm, vm       # vd[i+uimm] = vs2[i]
+vslideup.vx vd, vs2, rs1, vm        # vd[i+x[rs1]] = vs2[i]
+vslideup.vi vd, vs2, uimm, vm       # vd[i+uimm] = vs2[i]
 ----
 
 For `vslideup`, the value in `vl` specifies the maximum number of destination
@@ -4529,13 +4527,13 @@ Destination elements _OFFSET_ through `vl`-1 are written if unmasked and
 if _OFFSET_ < `vl`.
 
 ----
-   vslideup behavior for destination elements (`vstart` < `vl`)
+vslideup behavior for destination elements (`vstart` < `vl`)
 
-   OFFSET is amount to slideup, either from x register or a 5-bit immediate
+OFFSET is amount to slideup, either from x register or a 5-bit immediate
 
-                    0 <= i < min(vl, max(vstart, OFFSET))  Unchanged
-  max(vstart, OFFSET) <= i < vl                            vd[i] = vs2[i-OFFSET] if v0.mask[i] enabled
-                   vl <= i < VLMAX                         Follow tail policy
+                  0 <= i < min(vl, max(vstart, OFFSET))  Unchanged
+max(vstart, OFFSET) <= i < vl                            vd[i] = vs2[i-OFFSET] if v0.mask[i] enabled
+                 vl <= i < VLMAX                         Follow tail policy
 ----
 
 The destination vector register group for `vslideup` cannot overlap
@@ -4549,8 +4547,8 @@ input vectors during execution, and enables restart with non-zero
 ===== Vector Slidedown Instructions
 
 ----
- vslidedown.vx vd, vs2, rs1, vm       # vd[i] = vs2[i+x[rs1]]
- vslidedown.vi vd, vs2, uimm, vm      # vd[i] = vs2[i+uimm]
+vslidedown.vx vd, vs2, rs1, vm       # vd[i] = vs2[i+x[rs1]]
+vslidedown.vi vd, vs2, uimm, vm      # vd[i] = vs2[i+uimm]
 ----
 
 For `vslidedown`, the value in `vl` specifies the maximum number of
@@ -4564,15 +4562,14 @@ using an unsigned integer in the `x` register specified by `rs1`, or a
 If XLEN > SEW, _OFFSET_ is _not_ truncated to SEW bits.
 
 ----
-  vslidedown behavior for source elements for element i in slide (`vstart` < `vl`)
-                   0 <= i+OFFSET < VLMAX   src[i] = vs2[i+OFFSET]
-               VLMAX <= i+OFFSET           src[i] = 0
-
-  vslidedown behavior for destination element i in slide (`vstart` < `vl`)
-                   0 <= i < vstart         Unchanged
-              vstart <= i < vl             vd[i] = src[i] if v0.mask[i] enabled
-                  vl <= i < VLMAX          Follow tail policy
+vslidedown behavior for source elements for element i in slide (`vstart` < `vl`)
+                0 <= i+OFFSET < VLMAX   src[i] = vs2[i+OFFSET]
+            VLMAX <= i+OFFSET           src[i] = 0
 
+vslidedown behavior for destination element i in slide (`vstart` < `vl`)
+                 0 <= i < vstart         Unchanged
+            vstart <= i < vl             vd[i] = src[i] if v0.mask[i] enabled
+                vl <= i < VLMAX          Follow tail policy
 ----
 
 ===== Vector Slide1up
@@ -4582,7 +4579,7 @@ also allow a scalar integer value to be inserted at the vacated
 element position.
 
 ----
- vslide1up.vx  vd, vs2, rs1, vm        # vd[0]=x[rs1], vd[i+1] = vs2[i]
+vslide1up.vx  vd, vs2, rs1, vm        # vd[0]=x[rs1], vd[i+1] = vs2[i]
 ----
 
 The `vslide1up` instruction places the `x` register argument at
@@ -4603,12 +4600,12 @@ past `vl` are handled according to the current tail policy (Section
 
 
 ----
-   vslide1up behavior when vl > 0
+vslide1up behavior when vl > 0
 
-                    i < vstart  unchanged
-                0 = i = vstart  vd[i] = x[rs1] if v0.mask[i] enabled
-  max(vstart, 1) <= i < vl      vd[i] = vs2[i-1] if v0.mask[i] enabled
-              vl <= i < VLMAX   Follow tail policy
+                  i < vstart  unchanged
+              0 = i = vstart  vd[i] = x[rs1] if v0.mask[i] enabled
+max(vstart, 1) <= i < vl      vd[i] = vs2[i-1] if v0.mask[i] enabled
+            vl <= i < VLMAX   Follow tail policy
 ----
 
 The `vslide1up` instruction requires that the destination vector
@@ -4619,7 +4616,7 @@ Otherwise, the instruction encoding is reserved.
 ===== Vector Floating-Point Slide1up Instruction
 
 ----
- vfslide1up.vf vd, vs2, rs1, vm        # vd[0]=f[rs1], vd[i+1] = vs2[i]
+vfslide1up.vf vd, vs2, rs1, vm        # vd[0]=f[rs1], vd[i+1] = vs2[i]
 ----
 
 The `vfslide1up` instruction is defined analogously to `vslide1up`,
@@ -4637,7 +4634,7 @@ past `vl` are handled according to the current tail policy (Section
 <<sec-agnostic>>).
 
 ----
- vslide1down.vx  vd, vs2, rs1, vm      # vd[i] = vs2[i+1], vd[vl-1]=x[rs1]
+vslide1down.vx  vd, vs2, rs1, vm      # vd[i] = vs2[i+1], vd[vl-1]=x[rs1]
 ----
 
 The `vslide1down` instruction places the `x` register argument at
@@ -4649,12 +4646,12 @@ XLEN > SEW, the least-significant bits are copied over and the high
 SEW-XLEN bits are ignored.
 
 ----
-   vslide1down behavior
+vslide1down behavior
 
-                       i < vstart  unchanged
-             vstart <= i < vl-1    vd[i] = vs2[i+1] if v0.mask[i] enabled
-             vstart <= i = vl-1    vd[vl-1] = x[rs1] if v0.mask[i] enabled
-                 vl <= i < VLMAX   Follow tail policy
+          i < vstart  unchanged
+vstart <= i < vl-1    vd[i] = vs2[i+1] if v0.mask[i] enabled
+vstart <= i = vl-1    vd[vl-1] = x[rs1] if v0.mask[i] enabled
+    vl <= i < VLMAX   Follow tail policy
 ----
 
 NOTE: The `vslide1down` instruction can be used to load values into a
@@ -4667,7 +4664,7 @@ contents of a vector register, albeit slowly, with multiple repeated
 ===== Vector Floating-Point Slide1down Instruction
 
 ----
- vfslide1down.vf vd, vs2, rs1, vm      # vd[i] = vs2[i+1], vd[vl-1]=f[rs1]
+vfslide1down.vf vd, vs2, rs1, vm      # vd[i] = vs2[i+1], vd[vl-1]=f[rs1]
 ----
 
 The `vfslide1down` instruction is defined analogously to `vslide1down`,
@@ -4729,7 +4726,7 @@ contiguous elements at the start of the destination vector register
 group.
 
 ----
-  vcompress.vm vd, vs2, vs1  # Compress into vd elements of vs2 where vs1 is enabled
+vcompress.vm vd, vs2, vs1  # Compress into vd elements of vs2 where vs1 is enabled
 ----
 
 The vector mask register specified by `vs1` indicates which of the
@@ -4740,16 +4737,16 @@ elements according to the current tail policy (Section
 <<sec-agnostic>>).
 
 ----
-    Example use of vcompress instruction
+Example use of vcompress instruction
 
-        8 7 6 5 4 3 2 1 0   Element number
+8 7 6 5 4 3 2 1 0   Element number
 
-        1 1 0 1 0 0 1 0 1   v0
-        8 7 6 5 4 3 2 1 0   v1
-        1 2 3 4 5 6 7 8 9   v2
-                                vsetivli     t0, 9, e8, m1, tu, ma
-                                vcompress.vm v2, v1, v0
-        1 2 3 4 8 7 5 2 0   v2
+1 1 0 1 0 0 1 0 1   v0
+8 7 6 5 4 3 2 1 0   v1
+1 2 3 4 5 6 7 8 9   v2
+                        vsetivli     t0, 9, e8, m1, tu, ma
+                        vcompress.vm v2, v1, v0
+1 2 3 4 8 7 5 2 0   v2
 ----
 
 `vcompress` is encoded as an unmasked instruction (`vm=1`). The equivalent
@@ -4775,30 +4772,30 @@ There is no inverse `vdecompress` provided, as this operation can be
 readily synthesized using iota and a masked vrgather:
 
 ----
-    Desired functionality of 'vdecompress'
-      7 6 5 4 3 2 1 0     # vid
+Desired functionality of 'vdecompress'
+7 6 5 4 3 2 1 0     # vid
 
-            e d c b a     # packed vector of 5 elements
-      1 0 0 1 1 1 0 1     # mask vector of 8 elements
-      p q r s t u v w     # destination register before vdecompress
+      e d c b a     # packed vector of 5 elements
+1 0 0 1 1 1 0 1     # mask vector of 8 elements
+p q r s t u v w     # destination register before vdecompress
 
-      e q r d c b v a     # result of vdecompress
+e q r d c b v a     # result of vdecompress
 ----
 
 ----
-     # v0 holds mask
-     # v1 holds packed data
-     # v11 holds input expanded vector and result
-     viota.m v10, v0                 # Calc iota from mask in v0
-     vrgather.vv v11, v1, v10, v0.t  # Expand into destination
+# v0 holds mask
+# v1 holds packed data
+# v11 holds input expanded vector and result
+viota.m v10, v0                 # Calc iota from mask in v0
+vrgather.vv v11, v1, v10, v0.t  # Expand into destination
 ----
 ----
-   p q r s t u v w    # v11 destination register
-         e d c b a    # v1 source vector
-   1 0 0 1 1 1 0 1    # v0 mask vector
+p q r s t u v w    # v11 destination register
+      e d c b a    # v1 source vector
+1 0 0 1 1 1 0 1    # v0 mask vector
 
-   4 4 4 3 2 1 1 0    # v10 result of viota.m
-   e q r d c b v a    # v11 destination after vrgather using viota.m under mask
+4 4 4 3 2 1 1 0    # v10 result of viota.m
+e q r d c b v a    # v11 destination after vrgather using viota.m under mask
 ----
 
 ==== Whole Vector Register Move
@@ -4838,12 +4835,12 @@ related `vmerge` encoding, and it is unlikely the `vsmul` instruction
 would benefit from an immediate form.
 
 ----
-    vmv<nr>r.v vd, vs2  # General form
+vmv<nr>r.v vd, vs2  # General form
 
-    vmv1r.v v1, v2   #  Copy v1=v2
-    vmv2r.v v10, v12 #  Copy v10=v12; v11=v13
-    vmv4r.v v4, v8   #  Copy v4=v8; v5=v9; v6=v10; v7=v11
-    vmv8r.v v0, v8   #  Copy v0=v8; v1=v9; ...;  v7=v15
+vmv1r.v v1, v2   #  Copy v1=v2
+vmv2r.v v10, v12 #  Copy v10=v12; v11=v13
+vmv4r.v v4, v8   #  Copy v4=v8; v5=v9; v6=v10; v7=v11
+vmv8r.v v0, v8   #  Copy v0=v8; v1=v9; ...;  v7=v15
 ----
 
 The source and destination vector register numbers must be aligned
@@ -5248,7 +5245,7 @@ this constraint is backwards-compatible.
 
 NOTE: This constraint prevents element groups being broken across
 stripmining iterations in vector-length-agnostic code when a
-VLMAX-size vector would otherwise be able to accomodate a whole number
+VLMAX-size vector would otherwise be able to accommodate a whole number
 of element groups.
 
 NOTE: If EEW is encoded statically in the instruction, or if an
@@ -5325,5 +5322,5 @@ the mask element group is set).
 
 === Vector Instruction Listing
 
-include::images/wavedrom/v-inst-table.adoc[]
+include::images/wavedrom/v-inst-table.edn[]
 
diff --git a/src/vector-crypto.adoc b/src/vector-crypto.adoc
index 695a46a..8c422e1 100644
--- a/src/vector-crypto.adoc
+++ b/src/vector-crypto.adoc
@@ -559,7 +559,7 @@ efficiently.
 [NOTE]
 ====
 This Zvkb extension is a proper subset of the Zvbb extension.
-Zvkb allows for vector crypto implementations without incuring
+Zvkb allows for vector crypto implementations without incurring
 the the cost of implementing the additional bitmanip instructions
 in the Zvbb extension: vbrev.v, vclz.v, vctz.v, vcpop.v, and vwsll.[vv,vx,vi].
 ====
@@ -1107,7 +1107,7 @@ proper subset of <<Zvbb>>
 - vmerge.v[ivx]m
 
 ===== permute
-In the `.vv` and `.xv` forms of the `vragather[ei16]` instructions,
+In the `.vv` and `.xv` forms of the `vrgather[ei16]` instructions,
 the values in `vs1` and `rs1` are used for control and therefore are exempt from DIEL.
 
 - vrgather.v[ivx]
@@ -3190,7 +3190,7 @@ next state.
 // output is the new values of _a, b, e_ and _f_ after performing 2 rounds of the hash
 // computation. The new values, _c_, _d_, _g_, and _h_, are equal to the input values for _a_, _b_, // _e_, _f_ respectively.
 
-// [TIP]
+// [NOTE]
 // .Note to software developers
 // ====
 // The MessageSchedplus constant input to this instruction is generated by Software
@@ -3198,7 +3198,7 @@ next state.
 // round constant as defined in the NIST specification (see <<zvknh>>).
 // ====
 
-[TIP]
+[NOTE]
 .Note to software developers
 ====
 The NIST standard (see <<zvknh>>) requires the final hash to be in big-endian byte ordering
@@ -3217,7 +3217,7 @@ Having a high and low version of this instruction typically improves performance
 interleaving independent hashing operations (i.e., when hashing several files at once).
 ====
 
-// [TIP]
+// [NOTE]
 // .Note to software developers
 // ====
 // These instructions take in two SEW words _W1_ and _W0_ which are the next two words of the message
@@ -3378,7 +3378,7 @@ Eleven of the last 16 `SEW`-sized message-schedule words from `vd` (oldest), `vs
 and `vs1` (most recent) are processed to produce the
 next 4 message-schedule words.
 
-[TIP]
+[NOTE]
 .Note to software developers
 ====
 The first 16 SEW-sized words of the message schedule come from the _message block_
@@ -3389,7 +3389,7 @@ All of the subsequent message schedule words are produced by this instruction an
 therefore do not require an endian swap.
 ====
 
-[TIP]
+[NOTE]
 .Note to software developers
 ====
 Software is required to pack the words into element groups
@@ -3419,7 +3419,7 @@ lower indices indicating older words.
 // {W~11~, W~10~, W~9~, W~4~} +
 // {W~15~, W~14~, W~13~, W~12~}`
 
-[TIP]
+[NOTE]
 .Note to software developers
 ====
 The {W~11~, W~10~, W~9~, W~4~} element group can easily be formed by using a vector
diff --git a/src/zabha.adoc b/src/zabha.adoc
index 26529a5..932aacf 100644
--- a/src/zabha.adoc
+++ b/src/zabha.adoc
@@ -1,4 +1,4 @@
-== "Zabha" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0.0
+== "Zabha" Extension for Byte and Halfword Atomic Memory Operations, Version 1.0
 
 The A-extension offers atomic memory operation (AMO) instructions for _words_,
 _doublewords_, and _quadwords_ (only for `AMOCAS`). The absence of atomic
diff --git a/src/zfa.adoc b/src/zfa.adoc
index 942aeef..20223d8 100644
--- a/src/zfa.adoc
+++ b/src/zfa.adoc
@@ -57,13 +57,13 @@ like FMV.W.X, but with _rs2_=1.
 |31 |_Canonical NaN_ |`0` |`11111111` |`100...000`
 |===
 
-[TIP]
+[NOTE]
 ====
 The preferred assembly syntax for entries 1, 30, and 31 is `min`, `inf`,
 and `nan`, respectively. For entries 0 through 29 (including entry 1),
 the assembler will accept decimal constants in C-like syntax.
 ====
-[TIP]
+[NOTE]
 ====
 The set of 32 constants was chosen by examining floating-point
 libraries, including the C standard math library, and to optimize
@@ -170,7 +170,7 @@ FCVT.W.D with the same input operand.
 This instruction is only provided if the D extension is implemented. It
 is encoded like FCVT.W.D, but with the rs2 field set to 8 and the _rm_
 field set to 1 (RTZ). Other _rm_ values are _reserved_.
-[TIP]
+[NOTE]
 ====
 The assembly syntax requires the RTZ rounding mode to be explicitly
 specified, i.e., `fcvtmod.w.d rd, rs1, rtz`.
diff --git a/src/zfh.adoc b/src/zfh.adoc
index ab30e3d..e363a1c 100644
--- a/src/zfh.adoc
+++ b/src/zfh.adoc
@@ -27,7 +27,7 @@ halflatexmath:[$+$]singlelatexmath:[$\rightarrow$]half.
 New 16-bit variants of LOAD-FP and STORE-FP instructions are added,
 encoded with a new value for the funct3 width field.
 
-include::images/wavedrom/sp-load-store.adoc[]
+include::images/wavedrom/sp-load-store.edn[]
 [[sp-load-store]]
 //.Half-precision load and store instructions
 
@@ -58,9 +58,9 @@ The half-precision floating-point computational instructions are defined
 analogously to their single-precision counterparts, but operate on
 half-precision operands and produce half-precision results.
 
-include::images/wavedrom/spfloat-zfh.adoc[]
+include::images/wavedrom/spfloat-zfh.edn[]
 
-include::images/wavedrom/spfloat2-zfh.adoc[]
+include::images/wavedrom/spfloat2-zfh.edn[]
 
 === Half-Precision Conversion and Move Instructions
 
@@ -75,7 +75,7 @@ FCVT.WU.H, FCVT.LU.H, FCVT.H.WU, and FCVT.H.LU variants convert to or
 from unsigned integer values. FCVT.L[U].H and FCVT.H.L[U] are RV64-only
 instructions.
 
-include::images/wavedrom/half-prec-conv-and-mv.adoc[]
+include::images/wavedrom/half-prec-conv-and-mv.edn[]
 [[half-prec-conv-and-mv]]
 
 New floating-point-to-floating-point conversion instructions are added.
@@ -90,14 +90,14 @@ is present, FCVT.Q.H or FCVT.H.Q converts a half-precision
 floating-point number to a quad-precision floating-point number, or
 vice-versa, respectively.
 
-include::images/wavedrom/half-prec-flpt-to-flpt-conv.adoc[]
+include::images/wavedrom/half-prec-flpt-to-flpt-conv.edn[]
 [[half-prec-flpt-to-flpt-conv]]
 
 Floating-point to floating-point sign-injection instructions, FSGNJ.H,
 FSGNJN.H, and FSGNJX.H are defined analogously to the single-precision
 sign-injection instruction.
 
-include::images/wavedrom/flt-to-flt-sgn-inj-instr.adoc[]
+include::images/wavedrom/flt-to-flt-sgn-inj-instr.edn[]
 [[flt-to-flt-sgn-inj-instr]]
 
 Instructions are provided to move bit patterns between the
@@ -113,7 +113,7 @@ floating-point register _rd_, NaN-boxing the result.
 FMV.X.H and FMV.H.X do not modify the bits being transferred; in
 particular, the payloads of non-canonical NaNs are preserved.
 
-include::images/wavedrom/flt-pt-to-int-move.adoc[]
+include::images/wavedrom/flt-pt-to-int-move.edn[]
 [[flt-pt-to-int-move]]
 
 === Half-Precision Floating-Point Compare Instructions
@@ -122,7 +122,7 @@ The half-precision floating-point compare instructions are defined
 analogously to their single-precision counterparts, but operate on
 half-precision operands.
 
-include::images/wavedrom/half-pr-flt-pt-compare.adoc[]
+include::images/wavedrom/half-pr-flt-pt-compare.edn[]
 [[half-pr-flt-pt-compare]]
 
 === Half-Precision Floating-Point Classify Instruction
@@ -131,7 +131,7 @@ The half-precision floating-point classify instruction, FCLASS.H, is
 defined analogously to its single-precision counterpart, but operates on
 half-precision operands.
 
-include::images/wavedrom/half-pr-flt-pt-class.adoc[]
+include::images/wavedrom/half-pr-flt-pt-class.edn[]
 [[half-pr-flt-class]]
 
 === "Zfhmin" Standard Extension for Minimal Half-Precision Floating-Point
diff --git a/src/zfinx.adoc b/src/zfinx.adoc
index 035222d..aae57fe 100644
--- a/src/zfinx.adoc
+++ b/src/zfinx.adoc
@@ -64,7 +64,7 @@ registers is compatible with the existing RV64 calling conventions, which leave
 === Zdinx
 
 The Zdinx extension provides analogous double-precision floating-point
-instructions. The Zdinx extension requires the Zfinx extension.
+instructions. The Zdinx extension depends upon the Zfinx extension.
 
 The Zdinx extension adds all of the instructions that the D extension
 adds, _except_ for the transfer instructions FLD, FSD, FMV.D.X, FMV.X.D,
@@ -105,7 +105,7 @@ however.
 === Zhinx
 
 The Zhinx extension provides analogous half-precision floating-point
-instructions. The Zhinx extension requires the Zfinx extension.
+instructions. The Zhinx extension depends upon the Zfinx extension.
 
 The Zhinx extension adds all of the instructions that the Zfh extension
 adds, _except_ for the transfer instructions FLH, FSH, FMV.H.X, and
@@ -120,7 +120,7 @@ number.
 
 The Zhinxmin extension provides minimal support for 16-bit
 half-precision floating-point instructions that operate on the `x`
-registers. The Zhinxmin extension requires the Zfinx extension.
+registers. The Zhinxmin extension depends upon the Zfinx extension.
 
 The Zhinxmin extension includes the following instructions from the
 Zhinx extension: FCVT.S.H and FCVT.H.S. If the Zdinx extension is
diff --git a/src/zicsr.adoc b/src/zicsr.adoc
index 0e16de4..8d3db68 100644
--- a/src/zicsr.adoc
+++ b/src/zicsr.adoc
@@ -24,7 +24,7 @@ CSR specifier is encoded in the 12-bit _csr_ field of the instruction
 held in bits 31-20. The immediate forms use a 5-bit zero-extended
 immediate encoded in the _rs1_ field.
 
-include::images/wavedrom/csr-instr.adoc[]
+include::images/wavedrom/csr-instr.edn[]
 
 The CSRRW (Atomic Read/Write CSR) instruction atomically swaps values in
 the CSRs and integer registers. CSRRW reads the old value of the CSR,
diff --git a/src/zifencei.adoc b/src/zifencei.adoc
index 666effb..a234c67 100644
--- a/src/zifencei.adoc
+++ b/src/zifencei.adoc
@@ -17,7 +17,7 @@ snooping/invalidation overhead by writing translated instructions to
 memory regions that are known not to reside in the I-cache.
 ====
 '''
-[TIP]
+[NOTE]
 ====
 The FENCE.I instruction was designed to support a wide variety of
 implementations. A simple implementation can flush the local instruction
@@ -61,7 +61,7 @@ given address specified in _rs1_, and/or allowing software to use an ABI
 that relies on machine-mode cache-maintenance operations.
 ====
 
-include::images/wavedrom/zifencei-ff.adoc[]
+include::images/wavedrom/zifencei-ff.edn[]
 [[zifencei-ff]]
 //.FENCE.I instruction
 (((FENCE.I, synchronization)))
diff --git a/src/zihintntl.adoc b/src/zihintntl.adoc
index 8e225cb..7ddbb4b 100644
--- a/src/zihintntl.adoc
+++ b/src/zihintntl.adoc
@@ -178,7 +178,7 @@ preferentially take the interrupt before the NTL, rather than between
 the NTL and the memory access.
 ====
 '''
-[TIP]
+[NOTE]
 ====
 Since the NTL instructions are encoded as ADDs, they can be used within
 LR/SC loops without voiding the forward-progress guarantee. But, since
diff --git a/src/zihintpause.adoc b/src/zihintpause.adoc
index 9df71f3..12fde13 100644
--- a/src/zihintpause.adoc
+++ b/src/zihintpause.adoc
@@ -40,7 +40,7 @@ performance.
 PAUSE is encoded as a FENCE instruction with _pred_=`W`, _succ_=`0`, _fm_=`0`,
 _rd_=`x0`, and _rs1_=`x0`.
 
-//include::images/wavedrom/zihintpause-hint.adoc[]
+//include::images/wavedrom/zihintpause-hint.edn[]
 //[zihintpause-hint]
 //.Zihintpause fence instructions
 
diff --git a/src/zimop.adoc b/src/zimop.adoc
index ab88a4a..307d9a1 100644
--- a/src/zimop.adoc
+++ b/src/zimop.adoc
@@ -32,7 +32,7 @@ Unless redefined by another extension, these instructions simply write 0 to
 `x[rd]`.  Their encoding allows future extensions to define them to read `x[rs1]`,
 as well as write `x[rd]`.
 
-include::images/wavedrom/mop-r.adoc[]
+include::images/wavedrom/mop-r.edn[]
 [[mop-r]]
 
 The Zimop extension additionally defines 8 MOP instructions named
@@ -41,7 +41,7 @@ Unless redefined by another extension, these instructions simply
 write 0 to `x[rd]`.  Their encoding allows future extensions to define them to
 read `x[rs1]` and `x[rs2]`, as well as write `x[rd]`.
 
-include::images/wavedrom/mop-rr.adoc[]
+include::images/wavedrom/mop-rr.edn[]
 [[mop-rr]]
 
 NOTE: The recommended assembly syntax for MOP.R.__n__ is MOP.R.__n__ rd, rs1,
@@ -74,9 +74,9 @@ are defined to _not_ write any register.
 Their encoding allows future extensions to define them to read register
 `x[__n__]`.
 
-The Zcmop extension requires the Zca extension.
+The Zcmop extension depends upon the Zca extension.
 
-include::images/wavedrom/c-mop.adoc[]
+include::images/wavedrom/c-mop.edn[]
 [[c-mop]]
 
 NOTE: Very few suitable 16-bit encoding spaces exist.  This space was chosen