diff options
Diffstat (limited to 'src/priv-csrs.adoc')
| -rw-r--r-- | src/priv-csrs.adoc | 378 |
1 files changed, 329 insertions, 49 deletions
diff --git a/src/priv-csrs.adoc b/src/priv-csrs.adoc index 5104164..b46c2d4 100644 --- a/src/priv-csrs.adoc +++ b/src/priv-csrs.adoc @@ -86,8 +86,8 @@ Note that not all registers are required on all implementations. [.monofont] |=== 3+^|CSR Address 2.2+|Hex 3.2+|Use and Accessibility -|[11:10] |[9:8] |[7:4] -8+|Unprivileged and User-Level CSRs +|[11:10] |[9:8] |[7:4] +8+|Unprivileged and User-Level CSRs m|00 m|00 m|XXXX 2+m| 0x000-0x0FF 3+|Standard read/write |`01` |`00` |`XXXX` 2+| `0x400-0x4FF` 3+|Standard read/write |`10` |`00` |`XXXX` 2+| `0x800-0x8FF` 3+|Custom read/write @@ -145,7 +145,7 @@ m|00 m|00 m|XXXX 2+m| 0x000-0x0FF 3+|Standard read/write `0x003` |URW + URW + -URW +URW |`fflags` + `frm` + `fcsr` @@ -153,16 +153,59 @@ URW Floating-Point Dynamic Rounding Mode. + Floating-Point Control and Status Register (`frm` +`fflags`). +4+^|Unprivileged Vector CSRs + +|`0x008` + +`0x009` + +`0x00A` + +`0x00F` + +`0xC20` + +`0xC21` + +`0xC22` +|URW + +URW + +URW + +URW + +URO + +URO + +URO +|`vstart` + +`vxsat` + +`vxrm` + +`vcsr` + +`vl` + +`vtype` + +`vlenb` +|Vector start position. + +Fixed-point accrued saturation flag. + +Fixed-point rounding mode. + +Vector control and status register. + +Vector length. + +Vector data type register. + +Vector register length in bytes. + 4+^|Unprivileged Zicfiss extension CSR |`0x011` + |URW + |`ssp` + |Shadow Stack Pointer. + +4+^|Unprivileged Entropy Source Extension CSR +|`0x015` + +|URW + +|`seed` + +|Seed for cryptographic random bit generators. + + +4+^|Unprivileged Zcmt Extension CSR +|`0x017` + +|URW + +|`jvt` + +|Table jump base vector and control register. + + 4+^|Unprivileged Counter/Timers |`0xC00` + -`0xC01` + +`0xC01` + `0xC02` + `0xC03` + `0xC04` + @@ -174,7 +217,7 @@ Floating-Point Control and Status Register (`frm` +`fflags`). `0xC83` + `0xC84` +   + -`0xC9F` +`0xC9F` |URO + URO + URO + @@ -188,20 +231,20 @@ URO + URO + URO +   + -URO +URO |`cycle` + -`time` + -`instret` + -`hpmcounter3` + -`hpmcounter4` + +`time` + +`instret` + +`hpmcounter3` + +`hpmcounter4` + ⋮ + -`hpmcounter31` + +`hpmcounter31` + `cycleh` + -`timeh` + -`instreth` + -`hpmcounter3h` + +`timeh` + +`instreth` + +`hpmcounter3h` + `hpmcounter4h` + -⋮ + +⋮ + `hpmcounter31h` |Cycle counter for RDCYCLE instruction. + Timer for RDTIME instruction. + @@ -238,7 +281,7 @@ SRW + SRW |`sstatus` + `sie` + -`stvec` + +`stvec` + `scounteren` |Supervisor status register. + Supervisor interrupt-enable register. + @@ -273,23 +316,65 @@ SRO `stval` + `sip` + `scountovf` -|Scratch register for supervisor trap handlers. + +|Supervisor scratch register. + Supervisor exception program counter. + Supervisor trap cause. + -Supervisor bad address or instruction. + +Supervisor trap value. + Supervisor interrupt pending. + Supervisor count overflow. +4+^|Supervisor Indirect + +|`0x150` + +`0x151` + +`0x152` + +`0x153` + +`0x155` + +`0x156` + +`0x157` +|SRW + +SRW + +SRW + +SRW + +SRW + +SRW + +SRW +|`siselect` + +`sireg` + +`sireg2` + +`sireg3` + +`sireg4` + +`sireg5` + +`sireg6` +|Supervisor indirect register select. + +Supervisor indirect register alias. + +Supervisor indirect register alias 2. + +Supervisor indirect register alias 3. + +Supervisor indirect register alias 4. + +Supervisor indirect register alias 5. + +Supervisor indirect register alias 6. + 4+^|Supervisor Protection and Translation |`0x180` |SRW |`satp` |Supervisor address translation and protection. +4+^|Supervisor Timer Compare + +|`0x14D` + +`0x15D` +|SRW + +SRW +|`stimecmp` + +`stimecmph` +|Supervisor timer compare. + +Upper 32 bits of `stimecmp`, RV32 only. + 4+^|Debug/Trace Registers |`0x5A8` |SRW |`scontext` |Supervisor-mode context register. -//4+^|Supervisor Resource Management Configuration -//|`0x181` |SRW |`srmcfg` |Supervisor Resource Management Configuration. +4+^|Supervisor Resource Management Configuration +|`0x181` |SRW |`srmcfg` |Supervisor Resource Management Configuration. 4+^|Supervisor State Enable Registers |`0x10C` + @@ -309,6 +394,20 @@ Supervisor count overflow. Supervisor State Enable 2 Register. + Supervisor State Enable 3 Register. +4+^|Supervisor Control Transfer Records Configuration +|`0x14E` + + `0x14F` + + `0x15F` +|SRW + + SRW + + SRW +|`sctrctl` + + `sctrstatus` + + `sctrdepth` +|Supervisor Control Transfer Records Control Register. + + Supervisor Control Transfer Records Status Register. + + Supervisor Control Transfer Records Depth Register. + |=== <<< @@ -327,18 +426,18 @@ Supervisor count overflow. `0x606` + `0x607` + `0x612` -|HRW + +|HRW + HRW + HRW + HRW + HRW + HRW + -HRW +HRW |`hstatus` + `hedeleg` + -`hideleg` + -`hie` + -`hcounteren` + +`hideleg` + +`hie` + +`hcounteren` + `hgeie` + `hedelegh` |Hypervisor status register. + @@ -355,7 +454,7 @@ Upper 32 bits of `hedeleg`, RV32 only. `0x644` + `0x645` + `0x64A` + -`0xE12` +`0xE12` |HRW + HRW + HRW + @@ -363,10 +462,10 @@ HRW + HRO |`htval` + `hip` + -`hvip` + +`hvip` + `htinst` + `hgeip` -|Hypervisor bad guest physical address. + +|Hypervisor trap value. + Hypervisor interrupt pending. + Hypervisor virtual interrupt pending. + Hypervisor trap instruction (transformed). + @@ -377,9 +476,9 @@ Hypervisor guest external interrupt pending. |`0x60A` + `0x61A` |HRW + -HRM +HRW |`henvcfg` + -`henvcfgh` +`henvcfgh` |Hypervisor environment configuration register. + Upper 32 bits of `henvcfg`, RV32 only. @@ -446,7 +545,7 @@ Upper 32 bits of `htimedelta`, RV32 only. `0x242` + `0x243` + `0x244` + -`0x280` +`0x280` |HRW + HRW + HRW + @@ -455,15 +554,15 @@ HRW + HRW + HRW + HRW + -HRW +HRW |`vsstatus` + `vsie` + -`vstvec` + +`vstvec` + `vsscratch` + `vsepc` + -`vscause` + +`vscause` + `vstval` + -`vsip` + +`vsip` + `vsatp` |Virtual supervisor status register. + Virtual supervisor interrupt-enable register. + @@ -471,10 +570,58 @@ Virtual supervisor trap handler base address. + Virtual supervisor scratch register. + Virtual supervisor exception program counter. + Virtual supervisor trap cause. + -Virtual supervisor bad address or instruction. + +Virtual supervisor trap value. + Virtual supervisor interrupt pending. + Virtual supervisor address translation and protection. +4+^|Virtual Supervisor Indirect + +|`0x250` + +`0x251` + +`0x252` + +`0x253` + +`0x255` + +`0x256` + +`0x257` +|HRW + +HRW + +HRW + +HRW + +HRW + +HRW + +HRW +|`vsiselect` + +`vsireg` + +`vsireg2` + +`vsireg3` + +`vsireg4` + +`vsireg5` + +`vsireg6` +|Virtual supervisor indirect register select. + +Virtual supervisor indirect register alias. + +Virtual supervisor indirect register alias 2. + +Virtual supervisor indirect register alias 3. + +Virtual supervisor indirect register alias 4. + +Virtual supervisor indirect register alias 5. + +Virtual supervisor indirect register alias 6. + +4+^|Virtual Supervisor Timer Compare + +|`0x24D` + +`0x25D` +|HRW + +HRW +|`vstimecmp` + +`vstimecmph` +|Virtual supervisor timer compare. + +Upper 32 bits of `vstimecmp`, RV32 only. + +4+^|Virtual Supervisor Control Transfer Records Configuration +|`0x24E` +|HRW +|`vsctrctl` +|Virtual Supervisor Control Transfer Records Control Register. + |=== <<< @@ -527,9 +674,9 @@ MRW + MRW + MRW + MRW + -MRW +MRW |`mstatus` + -`misa` + +`misa` + `medeleg` + `mideleg` + `mie` + @@ -547,6 +694,25 @@ Machine counter enable. + Additional machine status register, RV32 only. + Upper 32 bits of `medeleg`, RV32 only. +4+^|Machine Counter Configuration + +|`0x321` + +`0x322` + +`0x721` + +`0x722` +|MRW + +MRW + +MRW + +MRW +|`mcyclecfg` + +`minstretcfg` + +`mcyclecfgh` + +`minstretcfgh` +|Machine cycle counter configuration register. + +Machine instret counter configuration register. + +Upper 32 bits of `mcyclecfg`, RV32 only. + +Upper 32 bits of `minstretcfg`, RV32 only. + 4+^|Machine Trap Handling |`0x340` + @@ -555,7 +721,7 @@ Upper 32 bits of `medeleg`, RV32 only. `0x343` + `0x344` + `0x34A` + -`0x34B` +`0x34B` |MRW + MRW + MRW + @@ -569,27 +735,58 @@ MRW `mtval` + `mip` + `mtinst` + -`mtval2` -|Scratch register for machine trap handlers. + +`mtval2` +|Machine scratch register. + Machine exception program counter. + Machine trap cause. + -Machine bad address or instruction. + +Machine trap value. + Machine interrupt pending. + Machine trap instruction (transformed). + -Machine bad guest physical address. +Machine second trap value. + +4+^|Machine Indirect + +|`0x350` + +`0x351` + +`0x352` + +`0x353` + +`0x355` + +`0x356` + +`0x357` +|MRW + +MRW + +MRW + +MRW + +MRW + +MRW + +MRW +|`miselect` + +`mireg` + +`mireg2` + +`mireg3` + +`mireg4` + +`mireg5` + +`mireg6` +|Machine indirect register select. + +Machine indirect register alias. + +Machine indirect register alias 2. + +Machine indirect register alias 3. + +Machine indirect register alias 4. + +Machine indirect register alias 5. + +Machine indirect register alias 6. 4+^|Machine Configuration |`0x30A` + `0x31A` + `0x747` + -`0x757` +`0x757` |MRW + MRW + MRW + -MRW +MRW |`menvcfg` + -`menvcfgh` + +`menvcfgh` + `mseccfg` + `mseccfgh` |Machine environment configuration register. + @@ -626,7 +823,7 @@ MRW `pmpcfg2` + `pmpcfg3` + ⋯ + -`pmpcfg14` + +`pmpcfg14` + `pmpcfg15` + `pmpaddr0` + `pmpaddr1` + @@ -691,7 +888,7 @@ Physical memory protection address register. |`0x740` + `0x741` + `0x742` + -`0x744` +`0x744` |MRW + MRW + MRW + @@ -767,7 +964,7 @@ Upper 32 bits of `mhpmcounter31`, RV32 only. `0x724` +   + `0x73F` -|MRW + +|MRW + MRW + MRW +   + @@ -795,6 +992,11 @@ Upper 32 bits of `mhpmevent4`, RV32 only. +   + Upper 32 bits of `mhpmevent31`, RV32 only. +4+^|Machine Control Transfer Records Configuration +|`0x34E` +|MRW +|`mctrctl` +|Machine Control Transfer Records Control Register. 4+^|Debug/Trace Registers (shared with Debug Mode) @@ -840,6 +1042,84 @@ Debug scratch register 0. + Debug scratch register 1. |=== +[[indcsrs-m]] +.Currently allocated RISC-V indirect CSR (Smcsrind) mappings - M-mode +[float="center",align="center",options="header"] +|=== +| `miselect` | `mireg` | `mireg2` | `mireg3` | `mireg4` | `mireg5` | `mireg6` +| 0x30 | `iprio0` | none | none | none | none | none +| ... | ... | ... | ... | ... | ... | ... +| 0x3F | `iprio15` | none | none | none | none | none +| 0x70 | `eidelivery` | none | none | none | none | none +| 0x71 | 0 | none | none | none | none | none +| 0x72 | `eithreshold` | none | none | none | none | none +| 0x73 | 0 | none | none | none | none | none +| ... | ... | ... | ... | ... | ... | ... +| 0x7F | 0 | none | none | none | none | none +| 0x80 | `eip0` | none | none | none | none | none +| ... | ... | ... | ... | ... | ... | ... +| 0xBF | `eip63` | none | none | none | none | none +| 0xC0 | `eie0` | none | none | none | none | none +| ... | ... | ... | ... | ... | ... | ... +| 0xFF | `eie63` | none | none | none | none | none +|=== + +[[indcsrs-s]] +.Currently allocated RISC-V indirect CSR (Smcsrind/Sscsrind) mappings - S-mode +[float="center",align="center",options="header"] +|=== +| `siselect` | `sireg` | `sireg2` | `sireg3` | `sireg4` | `sireg5` | `sireg6` +| 0x30 | `iprio0` | none | none | none | none | none +| ... | ... | ... | ... | ... | ... | ... +| 0x3F | `iprio15` | none | none | none | none | none +| 0x40 | `cycle` | `cyclecfg` | none | `cycleh` | `cyclecfgh` | none +| 0x41 | none | none | none | none | none | none +| 0x42 | `instret` | `instretcfg` | none | `instreth` | `instretcfgh` | none +| 0x43 | `hpmcounter3` | `hpmevent3` | none | `hpmcounter3h` | `hpmevent3h` | none +| ... | ... | ... | ... | ... | ... | ... +| 0x5F | `hpmcounter31` | `hpmevent31` | none | `hpmcounter31h` | `hpmevent31h` | none +| 0x70 | `eidelivery` | none | none | none | none | none +| 0x71 | 0 | none | none | none | none | none +| 0x72 | `eithreshold` | none | none | none | none | none +| 0x73 | 0 | none | none | none | none | none +| ... | ... | ... | ... | ... | ... | ... +| 0x7F | 0 | none | none | none | none | none +| 0x80 | `eip0` | none | none | none | none | none +| ... | ... | ... | ... | ... | ... | ... +| 0xBF | `eip63` | none | none | none | none | none +| 0xC0 | `eie0` | none | none | none | none | none +| ... | ... | ... | ... | ... | ... | ... +| 0xFF | `eie63` | none | none | none | none | none +| 0x200 | `ctrsource0` | `ctrtarget0` | `ctrdata0` | 0 | 0 | 0 +| ... | ... | ... | ... | ... | ... | ... +| 0x2FF | `ctrsource255` | `ctrtarget255` | `ctrdata255` | 0 | 0 | 0 +|=== + +[[indcsrs-vs]] +.Currently allocated RISC-V indirect CSR (Smcsrind/Sscsrind) mappings - VS-mode +[float="center",align="center",options="header"] +|=== +| `vsiselect` | `vsireg` | `vsireg2` | `vsireg3` | `vsireg4` | `vsireg5` | `vsireg6` +| 0x30 | `iprio0` | none | none | none | none | none +| ... | ... | ... | ... | ... | ... | ... +| 0x3F | `iprio15` | none | none | none | none | none +| 0x70 | `eidelivery` | none | none | none | none | none +| 0x71 | 0 | none | none | none | none | none +| 0x72 | `eithreshold` | none | none | none | none | none +| 0x73 | 0 | none | none | none | none | none +| ... | ... | ... | ... | ... | ... | ... +| 0x7F | 0 | none | none | none | none | none +| 0x80 | `eip0` | none | none | none | none | none +| ... | ... | ... | ... | ... | ... | ... +| 0xBF | `eip63` | none | none | none | none | none +| 0xC0 | `eie0` | none | none | none | none | none +| ... | ... | ... | ... | ... | ... | ... +| 0xFF | `eie63` | none | none | none | none | none +| 0x200 | `ctrsource0` | `ctrtarget0` | `ctrdata0` | 0 | 0 | 0 +| ... | ... | ... | ... | ... | ... | ... +| 0x2FF | `ctrsource255` | `ctrtarget255` | `ctrdata255` | 0 | 0 | 0 +|=== + === CSR Field Specifications The following definitions and abbreviations are used in specifying the |