diff options
Diffstat (limited to 'src/indirect-csr.adoc')
| -rw-r--r-- | src/indirect-csr.adoc | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/src/indirect-csr.adoc b/src/indirect-csr.adoc index 09e040a..adaccbb 100644 --- a/src/indirect-csr.adoc +++ b/src/indirect-csr.adoc @@ -99,8 +99,8 @@ value that is not implemented, is UNSPECIFIED. [%unbreakable] [NOTE] ==== -It is expected that implementations will typically raise an illegal -instruction exception for such accesses, so that, for example, they can +It is expected that implementations will typically raise an illegal-instruction +exception for such accesses, so that, for example, they can be identified as software bugs. Platform specs, profile specs, and/or the Privileged ISA spec may place more restrictions on behavior for such accesses. @@ -115,7 +115,7 @@ which the `miselect` value is allocated. [NOTE] ==== Ordinarily, each `mireg`*_i_* will access register state, access -read-only 0 state, or raise an illegal instruction exception. +read-only 0 state, or raise an illegal-instruction exception. For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is recommended that the lower 32 bits of the register are accessed through one of `mireg`, `mireg2`, or `mireg3`, while the upper 32 bits are accessed through `mireg4`, `mireg5`, or `mireg6`, respectively. ==== @@ -170,7 +170,7 @@ holds a value that is not implemented at supervisor level, is UNSPECIFIED. [%unbreakable] [NOTE] ==== -It is recommended that implementations raise an illegal instruction +It is recommended that implementations raise an illegal-instruction exception for such accesses, to facilitate possible emulation (by M-mode) of these accesses. ==== @@ -194,7 +194,7 @@ allocated. ==== Ordinarily, each `sireg`*_i_* will access register state, access read-only 0 state, or, unless executing in a virtual machine (covered in -the next section), raise an illegal instruction exception. +the next section), raise an illegal-instruction exception. ==== Note that the widths of `siselect` and `sireg*` are always the @@ -257,21 +257,21 @@ most-significant bit of `vsiselect` moves to the new position, retaining its value from before. For alias CSRs `sireg*` and `vsireg*`, the hypervisor extension’s usual -rules for when to raise a virtual instruction exception (based on +rules for when to raise a virtual-instruction exception (based on whether an instruction is HS-qualified) are not applicable. The rules given in this section for `sireg` and `vsireg` apply instead, unless overridden by the requirements specified in the section below, which take precedence over this section when extension Smstateen is also implemented. -A virtual instruction exception is raised for attempts from VS-mode or VU-mode to directly access `vsiselect` or `vsireg*`, or attempts from VU-mode to access `siselect` or `sireg*`. - -The behavior upon accessing `vsireg*` from M-mode or HS-mode, or accessing `sireg*` (really `vsireg*`) from VS-mode, while `vsiselect` holds a value that is not implemented at HS level, is UNSPECIFIED. +A virtual-instruction exception is raised for attempts from VS-mode or VU-mode to directly access `vsiselect` or `vsireg*`, or attempts from VU-mode to access `siselect` or `sireg*`. + +The behavior upon accessing `vsireg*` from M-mode or HS-mode, or accessing `sireg*` (really `vsireg*`) from VS-mode, while `vsiselect` holds a value that is not implemented at HS level, is UNSPECIFIED. [%unbreakable] [NOTE] ==== -It is recommended that implementations raise an illegal instruction exception for such accesses, to facilitate possible emulation (by M-mode) of these accesses. +It is recommended that implementations raise an illegal-instruction exception for such accesses, to facilitate possible emulation (by M-mode) of these accesses. ==== Otherwise, while `vsiselect` holds a number in a standard-defined and @@ -284,7 +284,7 @@ allocated. [%unbreakable] [NOTE] ==== -Ordinarily, each `vsireg`*_i_* will access register state, access read-only 0 state, or raise an exception (either an illegal instruction exception or, for select accesses from VS-mode, a virtual instruction exception). When `vsiselect` holds a value that is implemented at HS level but not at VS level, attempts to access `sireg*` (really `vsireg*`) from VS-mode will typically raise a virtual instruction exception. But there may be cases specific to an extension where different behavior is more appropriate. +Ordinarily, each `vsireg`*_i_* will access register state, access read-only 0 state, or raise an exception (either an illegal-instruction exception or, for select accesses from VS-mode, a virtual-instruction exception). When `vsiselect` holds a value that is implemented at HS level but not at VS level, attempts to access `sireg*` (really `vsireg*`) from VS-mode will typically raise a virtual-instruction exception. But there may be cases specific to an extension where different behavior is more appropriate. ==== Like `siselect` and `sireg*`, the widths of `vsiselect` and `vsireg*` are always @@ -299,7 +299,7 @@ If extension Smstateen is implemented together with Smcsrind, bit 60 of state-enable register `mstateen0` controls access to `siselect`, `sireg*`, `vsiselect`, and `vsireg*`. When `mstateen0`[60]=0, an attempt to access one of these CSRs from a privilege mode less privileged than M-mode results -in an illegal instruction exception. As always, the state-enable CSRs do +in an illegal-instruction exception. As always, the state-enable CSRs do not affect the accessibility of any state when in M-mode, only in less privileged modes. For more explanation, see the documentation for extension @@ -308,7 +308,7 @@ https://github.com/riscv/riscv-state-enable/releases/download/v1.0.0/Smstateen.p Other extensions may specify that certain mstateen bits control access to registers accessed indirectly through `siselect` + `sireg*`, and/or `vsiselect` + `vsireg*`. However, regardless of any other mstateen bits, if -`mstateen0`[60] = 1, a virtual instruction exception is raised as +`mstateen0`[60] = 1, a virtual-instruction exception is raised as described in the previous section for all attempts from VS-mode or VU-mode to directly access `vsiselect` or `vsireg*`, and for all attempts from VU-mode to access `siselect` or `sireg*`. @@ -318,8 +318,8 @@ in hypervisor CSR `hstateen0`, but controls access to only `siselect` and `sireg (really `vsiselect` and `vsireg*`), which is the state potentially accessible to a virtual machine executing in VS or VU-mode. When `hstateen0`[60]=0 and `mstateen0`[60]=1, all attempts from VS or VU-mode to -access `siselect` or `sireg*` raise a virtual instruction exception, not an -illegal instruction exception, regardless of the value of `vsiselect` or +access `siselect` or `sireg*` raise a virtual-instruction exception, not an +illegal-instruction exception, regardless of the value of `vsiselect` or any other mstateen bit. Extension Ssstateen is defined as the supervisor-level view of |