Age | Commit message (Collapse) | Author | Files | Lines | |
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2024-08-14 | Fit riscv-tests to newest riscv spec: renaming sptbr,sbadaddr,mbadaddr (#578) | HUJIYONG | 3 | -5/+5 | |
issue#577 In the newest riscv spec(2021 or later), two csr register "sptbr"(0x180) "s/mbadaddr"(0x243) were removed, and upgraded to "satp" "s/mtval". Together with more functions. This commit rename them to pass compile. | |||||
2023-02-13 | Fix ma_fetch test for norvc (#454) | Yujia Qiao | 1 | -1/+1 | |
The trap handler for norvc systems has an incorrect jump offset Signed-off-by: Yujia Qiao <code@rapiz.me> | |||||
2023-01-19 | Fix ma_fetch test for writable misa.C (#449) | Jerry Zhao | 1 | -3/+3 | |
2022-12-28 | Fix ma_fetch test to support systems where no RVC does not imply IALIGN=32 | Jerry Zhao | 1 | -9/+31 | |
2022-12-07 | zicntr: separate cycle/instret accessibility test (#439) | Chih-Min Chao | 1 | -8/+0 | |
It is allowed that M-mode only implementation could skip cycle/instret if the Zicntr is not included. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com> | |||||
2022-06-07 | Set TESTNUM before executing code. | Tim Newsome | 1 | -3/+2 | |
Tests that might cause a trap during their code need TESTNUM (gp) set so the trap handler can correctly identify which test is running, and also report that to the user in case the test fails. Fix up shamt.S and csr.S to handle the new behavior. | |||||
2021-07-21 | Move the Svnapot test to its own folder (#351) | Daniel Lustig | 2 | -173/+0 | |
...since not all implementations will support it | |||||
2021-07-19 | Add a test for Svnapot (#349) | Daniel Lustig | 2 | -0/+173 | |
2021-06-01 | Enable access to cycle counter before trying to write it | Andrew Waterman | 1 | -0/+13 | |
There are two reasons that writing the cycle counter might trap: - Because it's a read-only CSR - Because mcounteren.CY=0 or scounteren.CY=0 We want to make sure we're testing the first property, so set up the other bits accordingly. | |||||
2021-06-01 | Test all four ways of reading a read-only CSR | Andrew Waterman | 1 | -0/+8 | |
2021-05-12 | Fix for rv64mi/sbreak and rv64mi/scall that I broke in my previous commit: ↵ | SLAMET RIANTO | 2 | -0/+2 | |
(#337) Added "#define stvec mtvec" under __MACHINE_MODE ifdef. Co-authored-by: Slamet Rianto <slametr@gamma04.internal.sifive.com> | |||||
2021-05-10 | Fixes for illegal.S to support Bare-SMode and sbreak.S & scall.S to support ↵ | SLAMET RIANTO | 2 | -0/+14 | |
CLIC mode. (#336) illegal.S: - After the test enters supervisor mode, check if paging is supported. - If paging is NOT supported (i.e. Bare S-mode), jump to a new section of code that checks the following: -- SFENCE.VMA causing illegal instruction trap regardless of TVM. -- Access to SATP does not trap. -- Jump to the same TSR check as regular S-mode -- End test sbreak.S & scall.S: - Before checking for scause, check if the core is in CLIC-mode (mtvec[1]). - If we're in CLIC-mode, mask off scause bits[(XLEN-1):8] before checing its value. - Otherwise, don't mask off any scause bits as in the original test. Co-authored-by: Slamet Rianto <slametr@gamma04.internal.sifive.com> | |||||
2020-12-08 | Add rd=x0 test case to csr test (#308) | Takahiro | 1 | -0/+1 | |
2020-11-20 | Only attempt to build tests supported by compiler | Andrew Waterman | 1 | -2/+0 | |
Resolves #303 | |||||
2020-03-21 | Fix regression introduced by 24d7d6b68c5581c36cbdef354b1882a7a8dd52c5 | Andrew Waterman | 1 | -7/+7 | |
2020-03-18 | Have both rs=rd and rs!=rd cases in csr.S (#263) | Takahiro | 1 | -12/+15 | |
2020-03-11 | Add comment explaining convoluted rv64mi-p-scall behavior | Andrew Waterman | 1 | -0/+6 | |
2020-03-11 | Revert "scall: make the intention of the test in machine mode more clear (#246)" | Andrew Waterman | 1 | -6/+1 | |
This reverts commit 6fa1896b2a3f581359f0b6a952542f814e30602c. Resolves #256 | |||||
2020-03-11 | Setup a multilevel page table to avoid misaligned superpages caused by ↵ | Cedric Orban | 1 | -0/+4 | |
variable DRAM_BASE (#255) * setup a multilevel page table to avoid misaligned superpages * Revert "setup a multilevel page table to avoid misaligned superpages" This reverts commit 73c142df7dbdd3a5347ef228a368fb58b0b12be5. * statically fail if DRAM_BASE is not superpage-aligned | |||||
2020-03-06 | Don't assume reset state of mscratch (#254) | Paul Donahue | 1 | -1/+1 | |
* Bump riscv-test-env * Merge master * Don't assume that mscratch is initialized to a particular value on reset | |||||
2020-02-21 | scall: make the intention of the test in machine mode more clear (#246) | Nils Asmussen | 1 | -1/+6 | |
2020-02-20 | Fix rv64mi-p-csr on systems with FPUs | Andrew Waterman | 1 | -2/+3 | |
3a98ec2e306938cce07ab15e3678d670611aa66d introduced a subtle bug because of the value of TESTNUM at the point an expected exception was taken. Fix by moving the new tests earlier in the program. | |||||
2020-01-31 | Added CSR test cases on whether writing 0 to CSR works, as that might get ↵ | Torbjørn Viem Ness | 1 | -0/+2 | |
overlooked by implementors because some CSR operations should ignore writes if source is x0 (#236) | |||||
2019-11-04 | Remove cruft from icache-alias test | Andrew Waterman | 1 | -35/+0 | |
2019-11-04 | Add rv64si-p-icache-alias | Andrew Waterman | 2 | -0/+177 | |
This test checks that an I$ appears to be physically indexed. | |||||
2018-08-21 | Changing the register mstatus is read into (#152) | Srivatsa Yogendra | 1 | -2/+2 | |
The mstatus reading overwrites the expected user mode cause value. | |||||
2018-08-20 | Revert "Fix to solve the failing tests shamt, csr and scall (#151)" | Andrew Waterman | 2 | -52/+5 | |
This reverts commit 31a91823b7c7becacd06c9c32e44180eea5e4fe7. These changes should be made to the test environment, not the tests themselves. | |||||
2018-08-17 | Fix to solve the failing tests shamt, csr and scall (#151) | Srivatsa Yogendra | 2 | -5/+52 | |
* making mtvec_handler global * Adding the pmp configuration inst The PMP config instructions are added as the test jumps to user mode * Adding pmp config inst Adding pmp config instructions as the test jumps to user mode * changing to PMP macros * changing to PMP Macros * moving the #endif after pmp initialization * Removing the unwanted label | |||||
2018-03-21 | Make misa.C test conform to Hauser proposal | Andrew Waterman | 1 | -43/+10 | |
See https://github.com/riscv/riscv-isa-manual/commit/0472bcdd166f45712492829a250e228bb45fa5e7 | |||||
2018-02-27 | Add test for clearing misa.C while PC is misaligned (#117) | Andrew Waterman | 1 | -1/+79 | |
See https://github.com/riscv/riscv-isa-manual/pull/139 | |||||
2017-11-27 | Rename sbadaddr to satp | Andrew Waterman | 1 | -1/+1 | |
2017-11-22 | Check sepc for rv64si/scall test. (#107) | Christopher Celio | 1 | -0/+4 | |
Closes #105. | |||||
2017-11-11 | Make sure that code is 4-byte aligned before disabling rvc (#100) | Andrew Waterman | 1 | -0/+1 | |
2017-11-09 | Make rv64mi-p-ecall work when U-mode is not present | Andrew Waterman | 1 | -1/+17 | |
2017-11-09 | Use mstatus.MPP to check existence of U-mode | Andrew Waterman | 1 | -5/+6 | |
misa is allowed to be hardwired to 0, so checking its U bit could incorrectly suggest that U-mode is not supported. | |||||
2017-11-01 | SBREAK test now checks EPC value. (#92) | Christopher Celio | 1 | -0/+4 | |
Closes #89 | |||||
2017-10-30 | Declare trap handlers as global symbols. (#87) | Richard Xia | 5 | -0/+5 | |
This allows them to be referenced by other files, such as a test environment that lives in a separate compilation unit. | |||||
2017-10-26 | Verify that mtval/stval is written correctly on misaligned fetch | Andrew Waterman | 1 | -1/+9 | |
2017-10-26 | Fix rv64mi-csr for the case where U-mode is not available. (#86) | Richard Xia | 1 | -0/+16 | |
2017-09-01 | Improve ma_fetch test to cover JAL and branches | Andrew Waterman | 1 | -1/+48 | |
2017-08-07 | rv64[ms]i-csr: Only emit F instructions when compiled for F. | Richard Xia | 1 | -1/+6 | |
2017-05-05 | Check UXL in sstatus | Andrew Waterman | 1 | -0/+5 | |
2017-05-05 | Test that superpage PTEs trap when PPN LSBs are set | Andrew Waterman | 1 | -0/+18 | |
2017-05-05 | Regularize control flow in dirty-bit test | Andrew Waterman | 1 | -8/+12 | |
2017-03-30 | Expand dirty-bit test to test MPRV and SUM | Andrew Waterman | 1 | -27/+30 | |
2017-03-27 | Separate page faults from physical memory access exceptions | Andrew Waterman | 1 | -1/+1 | |
2017-03-21 | Allow supervisor access to user pages in dirty-bit test | Andrew Waterman | 1 | -1/+1 | |
2017-03-09 | Permit flexible dirty-bit behavior | Andrew Waterman | 1 | -16/+26 | |
2016-11-01 | Make sure FP stores don't write memory if mstatus.FS=0. | Andrew Waterman | 1 | -8/+22 | |
2016-08-26 | Update to new breakpoint & counter spec | Andrew Waterman | 1 | -6/+6 | |